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Keith Diefendorff
REPORT Compaq Chooses SMT for Alpha Simultaneous Multithreading
Prozessorarchitektur Am Beispiel Des Amdathlon
A Bibliography of Publications in IEEE Micro
Optimizing SIMD Execution in HW/SW Co-Designed Processors
UNIVERSITY of CALIFORNIA, SAN DIEGO Holistic Design for Multi-Core Architectures a Dissertation Submitted in Partial Satisfactio
Sony's Emotionally Charged Chip
Commemorative Booklet for the Thirty-Fifth Asilomar Microcomputer Workshop April 15-17, 2009
Selective Vectorization for Short-Vector Instructions Samuel Larsen, Rodric Rabbah, and Saman Amarasinghe
HP, Intel Complete IA-64 Rollout:4/10/00
Low Overhead Memory Subsystem Design for a Multicore Parallel DSP Processor
Commemorative Booklet for the Thirty-Fifth Asilomar Microcomputer Workshop April 15-17, 2009 Programs from the 1975-2009 Worksho
Altivec Extension to Powerpc Accelerates Media Processing
MICROPROCESSORS I-INTRODUCTION: Microprocessors
Survey on Combinatorial Register Allocation and Instruction Scheduling ACM Computing Surveys
PC Processor Microarchitecture
Redefining Intellectual Property Value
Power4 Focuses on Memory Bandwidth IBM Confronts IA-64, Says ISA Not Important
CMOS Sensors ♦ Intel/FTC ♦ X86 Testing ♦ Wilkes 2
Top View
Decoupled Vector-Fetch Architecture with a Scalarizing Compiler By
Cache Performance for Multimedia Applications
General-Purpose Architectures for Media Processing and Database Applications
A Bibliography of Publications on Visual Instruction Sets
Optimising HEVC Decoding Using Intel AVX512 SIMD Extensions
Clock Rate Versus IPC: the End of the Road for Conventional Microarchitectures
Nagarajanr54359.Pdf (2.985Mb)
Katmai Enhances MMX: 10/5/98
Oral History of Gary Davidian, Part 2 of 2
Hwacha Decoupled Vector Accelerator Rocket
Implementation of 128/256 Bit Data Bus Microprocessor Core on FPGA
Branch Path Re-Aliasing Daniel A
Exploring the Tradeoffs Between Programmability and Efficiency In
(12) United States Patent (10) Patent No.: US 6,336,178 B1 Favor (45) Date of Patent: Jan
A New Direction for Computer Architecture Research
Pentium III = Pentium II + SSE: 3/8/99
IBM Research Report IBM Power Architecture Tejas S. Karkhanis
Decoupled Vector-Fetch Architecture with a Scalarizing Compiler