DOCSLIB.ORG

Altivec Extension to Powerpc Accelerates Media Processing

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

ALTIVEC EXTENSION TO POWERPC ACCELERATES MEDIA PROCESSING DESIGNED AROUND THE PREMISE THAT MULTIMEDIA WILL BE THE PRIMARY CONSUMER OF PROCESSING CYCLES IN FUTURE PCS, ALTIVEC—WHICH APPLE CALLS THE VELOCITY ENGINE—INCREASES PERFORMANCE ACROSS A BROAD SPECTRUM OF MEDIA PROCESSING APPLICATIONS. There is a clear trend in personal com- extension to a general-purpose architecture. puting toward multimedia-rich applications. But the similarity ends there. Whereas the These applications will incorporate a wide vari- other extensions were obviously constrained ety of multimedia technologies, including audio by backward compatibility and a desire to and video compression, 2D image processing, limit silicon investment to a small fraction of 3D graphics, speech and handwriting recogni- the processor die area, the primary goal for Keith Diefendorff tion, media mining, and narrow-/broadband AltiVec was high functionality. It was designed signal processing for communication. from scratch around the premise that multi- Microprocessor Report In response to this demand, major micro- media will become the primary consumer of processor vendors have announced architec- processing cycles8 in future PCs and therefore tural extensions to their general-purpose deserves first-class treatment in the CPU. Pradeep K. Dubey processors in an effort to improve their multi- Unlike most other extensions, which over- media performance. Intel extended IA-32 with load their floating-point (FP) registers to IBM Research Division MMX1 and SSE (alias KNI),2 Sun enhanced accommodate multimedia data, AltiVec ded- Sparc with VIS,3 Hewlett-Packard added icates a large new register file exclusively to it. MAX4 to its PA-RISC architecture, Silicon Although overloading the FP registers avoids Ron Hochsprung Graphics extended the MIPS architecture with new architectural state, eliminating the need MDMX,5 and Digital (now Compaq) added to modify the operating system, it also signif- Apple Computer MVI to Alpha. This article describes the most icantly compromises performance, which was recent, and what we believe to be the most not acceptable for AltiVec. comprehensive, addition to this list: Power- AltiVec treats multimedia data as first-class Hunter Scales PC’s AltiVec.6,7 AltiVec speeds not only media data in the form of vectors. Vector elements processing but also nearly any application in include all of the major data types found in Motorola Corporation which data parallelism exists, as demonstrat- 3D graphics, image processing, digital audio ed by a cycle-accurate simulation of Motoro- and video, speech recognition, data mining, la’s MPC 7400, the heart of Apple G4 systems. and other multimedia applications. AltiVec’s powerful data reorganization capa- Highlights and performance summary bility goes far beyond that of any previous Like all the other extensions, AltiVec is a SIMD engine, making AltiVec uniquely well SIMD (single-instruction, multiple-data) suited to the bit-parallel algorithms found in 0272-1732/00/$10.00 2000 IEEE 85 ALTIVEC EXTENSION Table 1. Data types for various media tasks. 128-bit vector, loop overheads tend to be small, giving Data type AltiVec processors perfor- 8-bit integer 16-bit integer Single-precision float mance approaching that of Task Unsigned Signed Unsigned Signed Signed true vector machines. Video Low quality High quality On the basis of cycle- Audio Low quality High quality accurate simulations of more Image processing Low quality High quality than 40 media processing ker- 3D graphics Low quality High quality nels, we found that AltiVec Speech recognition Low quality High quality delivered an average speedup Communication Crypto Crypto of 6.5 on integer kernels and Media mining High quality 5.1 on floating-point kernels, over the same PowerPC processor without AltiVec. digital signal processing (DSP) domains. The speedups often approach—and sometimes These include error correction, bit-packing even exceed—the theoretical SIMD paral- kernels, and many others. lelism, which is 16 on 8-bit data (for example, AltiVec extends the scalar PowerPC archi- video), eight on 16-bit data (for example, tecture with a powerful new set of SIMD modem filters), and four on 32-bit integers and instructions. These instructions execute from floats (for example, 3D graphics and high- the same instruction stream as the PowerPC’s fidelity audio). Speedups greater than the theo- scalar integer, floating-point, and branch retical parallelism arise from the ability to use instructions. new algorithms that are inappropriate for scalar AltiVec’s major architectural characteristics processors or for less capable SIMD processors. include AltiVec architecture • fixed-length 128-bit vectors, each com- One of the attributes that enable large prising four, eight, or 16 data elements; speedups across such a broad spectrum of • a separate vector register file with a 32- media processing applications is AltiVec’s sup- register namespace, each register holding port for all of the important media data types. one 128-bit vector; Table 1 shows the various data types that a • vector-element data types of 8-, 16-, and processor must support if it is to perform well 32-bit signed or unsigned integers, as on media processing tasks. To date, AltiVec is well as IEEE single-precision floats; the only SIMD architectural extension to sup- • 162 new SIMD-style instructions opti- port all these types. mized for digital signal processing; AltiVec’s large vector register file provides • saturation or modulo arithmetic; quick access to a large number of values, such • a four-operand, nondestructive instruc- as the transform or filter coefficients that are tion format (three sources, one destina- accessed frequently in signal processing loops. tion); and The large register namespace facilitates soft- • modeless operation for zero overhead use ware pipelining and loop unrolling necessary of AltiVec instructions. to cover the long latencies associated with media streams. With a separate register file, SIMD parallelism is well matched to the the general-purpose and floating-point regis- parallelism found in the packed-data streams ters are not encumbered with multimedia of media applications. To use SIMD process- data, so media processing doesn’t interfere ing, algorithms typically break long data with scalar processing. The separate file also streams into sequences of short fixed-length permits the vector registers to be physically vector operands. SIMD instructions then optimized for the wide SIMD execution units. process these vectors iteratively in loops, each Another important AltiVec feature is its instruction performing the same operation on four-operand instruction format (three source all corresponding elements in the source- operands, one destination). This feature gives operand vectors in parallel. With AltiVec’s long each instruction extraordinarily high operand 86 IEEE MICRO Table 2. AltiVec instruction-set summary.* Arithmetic Source elements Destination elements Instruction class Signed Unsigned Modulo Saturate Operands Bytes Halfwords Words Floats Vectors Bytes Halfwords Words Floats Vectors Load/store X X X X X Stream prefetch X Add/sub X X X X 2 X X X X X X X X Multiply X X X 2 X X X X X X Multiply-add X X X X 3 X X X X Multiply-sum X X X X 3 X X X Sum across X X 2 Partial sum across X X X 2 X X X X X X Average X X X 2 X X X X X X Logicals X 2 X X Rotate/shift X X X 2 X X X X X X Compare X X 2 X X X X X X X X Select 2 X X Pack X X X X 2 X X X X Unpack/merge X X 2 X X X X Splat X X X 2 X X X X X X Permute X X 3 X X Shift elements 2 X X Round to integer X 1 X X Convert w/scale X X 1 X X X X Max/min X X X 2 X X X X X X X X 1/x estimate X 1 X X 1/sqrt(x) estimate X 1 X X Log/power estimates X 1 X X *This table summarizes AltiVec capabilities in a concise form. Not all combinations shown are available for every instruction in a given class. bandwidth and supports the encoding of pow- many digital-media-processing algorithms erful instructions such as multiply-add, per- into a set of generalized primitives that sup- mute, and select (described later). Since the port common operations such as saturation four-operand format is nondestructive, it also arithmetic. Using this approach, the design eliminates the excess register shuffling and can support a wide spectrum of media appli- copying that comes with destructive two- cations while avoiding the highly specialized operand formats like that of the x86 architec- instructions commonly found in traditional ture. Thus, AltiVec’s instruction format allows DSPs. Counting all variations of data types programs to use registers efficiently, minimiz- and arithmetic (modulo, saturation, signed, ing spill/fill traffic to memory and producing and unsigned), AltiVec adds 162 new instruc- a short instruction path, which are both tions to the PowerPC architecture, as sum- important for efficient signal processing loops. marized in Table 2. AltiVec is based on a simple RISC-style The AltiVec design criteria called for all load/store architecture, but instructions oper- instructions to be easily pipelined and suitable ate on vector operands rather than on the sim- for superscalar, out-of-order dispatch. All ple scalar operands of classical RISC engines. AltiVec processors are expected to implement The AltiVec instruction set was distilled from the full architectural vector width and to fully MARCH–APRIL 2000 87 ALTIVEC EXTENSION vector instructions with Pow- VC 01 04 08 00 1F 15 09 0A 05 1F 02 03 07 0D 0B 0E erPC scalar instructions. VB 1 Permute power Much of AltiVec’s perfor- VA 0 mance and flexibility derives from the permute instruction 0123456789ABCDEF (vperm), illustrated in Figure 1a.
Recommended publications
  • RISC-V Vector Extension Webinar II

    RISC-V Vector Extension Webinar II

    RISC-V Vector Extension Webinar II August 3th, 2021 Thang Tran, Ph.D. Principal Engineer Webinar II - Agenda • Andes overview • Vector technology background – SIMD/vector concept – Vector processor basic • RISC-V V extension ISA – Basic – CSR • RISC-V V extension ISA – Memory operations – Compute instructions • Sample codes – Matrix multiplication – Loads with RVV versions 0.8 and 1.0 • AndesCore™ NX27V • Summary Copyright© 2020 Andes Technology Corp. 2 Terminology • ACE: Andes Custom Extension • ISA: Instruction Set Architecture • CSR: Control and Status Register • GOPS: Giga Operations Per Second • SEW: Element Width (8-64) • GFLOPS: Giga Floating-Point OPS • ELEN: Largest Element Width (32 or 64) • XRF: Integer register file • XLEN: Scalar register length in bits (64) • FRF: Floating-point register file • FLEN: FP register length in bits (16-64) • VRF: Vector register file • VLEN: Vector register length in bits (128-512) • SIMD: Single Instruction Multiple Data • LMUL: Register grouping multiple (1/8-8) • MMX: Multi Media Extension • EMUL: Effective LMUL • SSE: Streaming SIMD Extension • VLMAX/MVL: Vector Length Max • AVX: Advanced Vector Extension • AVL/VL: Application Vector Length • Configurable: parameters are fixed at built time, i.e. cache size • Extensible: added instructions to ISA includes custom instructions to be added by customer • Standard extension: the reserved codes in the ISA for special purposes, i.e. FP, DSP, … • Programmable: parameters can be dynamically changed in the program Copyright© 2020 Andes Technology Corp. 3 RISC-V V Extension ISA Basic Copyright© 2020 Andes Technology Corp. 4 Vector Register ISA • Vector-Register ISA Definition: − All vector operations are between vector registers (except for load and store).
  • Vxworks Architecture Supplement, 6.2

    Vxworks Architecture Supplement, 6.2

    VxWorks Architecture Supplement VxWorks® ARCHITECTURE SUPPLEMENT 6.2 Copyright © 2005 Wind River Systems, Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means without the prior written permission of Wind River Systems, Inc. Wind River, the Wind River logo, Tornado, and VxWorks are registered trademarks of Wind River Systems, Inc. Any third-party trademarks referenced are the property of their respective owners. For further information regarding Wind River trademarks, please see: http://www.windriver.com/company/terms/trademark.html This product may include software licensed to Wind River by third parties. Relevant notices (if any) are provided in your product installation at the following location: installDir/product_name/3rd_party_licensor_notice.pdf. Wind River may refer to third-party documentation by listing publications or providing links to third-party Web sites for informational purposes. Wind River accepts no responsibility for the information provided in such third-party documentation. Corporate Headquarters Wind River Systems, Inc. 500 Wind River Way Alameda, CA 94501-1153 U.S.A. toll free (U.S.): (800) 545-WIND telephone: (510) 748-4100 facsimile: (510) 749-2010 For additional contact information, please visit the Wind River URL: http://www.windriver.com For information on how to contact Customer Support, please visit the following URL: http://www.windriver.com/support VxWorks Architecture Supplement, 6.2 11 Oct 05 Part #: DOC-15660-ND-00 Contents 1 Introduction
  • SIMD Extensions

    SIMD Extensions

    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
  • Optimizing Packed String Matching on AVX2 Platform

    Optimizing Packed String Matching on AVX2 Platform

    Optimizing Packed String Matching on AVX2 Platform M. Akif Aydo˘gmu¸s1,2 and M.O˘guzhan Külekci1 1 Informatics Institute, Istanbul Technical University, Istanbul, Turkey [email protected], [email protected] 2 TUBITAK UME, Gebze-Kocaeli, Turkey Abstract. Exact string matching, searching for all occurrences of given pattern P on a text T , is a fundamental issue in computer science with many applica- tions in natural language processing, speech processing, computational biology, information retrieval, intrusion detection systems, data compression, and etc. Speeding up the pattern matching operations benefiting from the SIMD par- allelism has received attention in the recent literature, where the empirical results on previous studies revealed that SIMD parallelism significantly helps, while the performance may even be expected to get automatically enhanced with the ever increasing size of the SIMD registers. In this paper, we provide variants of the previously proposed EPSM and SSEF algorithms, which are orig- inally implemented on Intel SSE4.2 (Streaming SIMD Extensions 4.2 version with 128-bit registers). We tune the new algorithms according to Intel AVX2 platform (Advanced Vector Extensions 2 with 256-bit registers) and analyze the gain in performance with respect to the increasing length of the SIMD registers. Profiling the new algorithms by using the Intel Vtune Amplifier for detecting performance bottlenecks led us to consider the cache friendliness and shared-memory access issues in the AVX2 platform. We applied cache op- timization techniques to overcome the problems particularly addressing the search algorithms based on filtering. Experimental comparison of the new solutions with the previously known-to- be-fast algorithms on small, medium, and large alphabet text files with diverse pattern lengths showed that the algorithms on AVX2 platform optimized cache obliviously outperforms the previous solutions.
  • REPORT Compaq Chooses SMT for Alpha Simultaneous Multithreading

    REPORT Compaq Chooses SMT for Alpha Simultaneous Multithreading

    VOLUME 13, NUMBER 16 DECEMBER 6, 1999 MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE Compaq Chooses SMT for Alpha Simultaneous Multithreading Exploits Instruction- and Thread-Level Parallelism by Keith Diefendorff Given a full complement of on-chip memory, increas- ing the clock frequency will increase the performance of the As it climbs rapidly past the 100-million- core. One way to increase frequency is to deepen the pipeline. transistor-per-chip mark, the micro- But with pipelines already reaching upwards of 12–14 stages, processor industry is struggling with the mounting inefficiencies may close this avenue, limiting future question of how to get proportionally more performance out frequency improvements to those that can be attained from of these new transistors. Speaking at the recent Microproces- semiconductor-circuit speedup. Unfortunately this speedup, sor Forum, Joel Emer, a Principal Member of the Technical roughly 20% per year, is well below that required to attain the Staff in Compaq’s Alpha Development Group, described his historical 60% per year performance increase. To prevent company’s approach: simultaneous multithreading, or SMT. bursting this bubble, the only real alternative left is to exploit Emer’s interest in SMT was inspired by the work of more and more parallelism. Dean Tullsen, who described the technique in 1995 while at Indeed, the pursuit of parallelism occupies the energy the University of Washington. Since that time, Emer has of many processor architects today. There are basically two been studying SMT along with other researchers at Washing- theories: one is that instruction-level parallelism (ILP) is ton. Once convinced of its value, he began evangelizing SMT abundant and remains a viable resource waiting to be tapped; within Compaq.
  • Prozessorarchitektur Am Beispiel Des Amdathlon

    Prozessorarchitektur Am Beispiel Des Amdathlon

    PROZESSORARCHITEKTUR AM BEISPIEL DES AMD ATHLON AUSGEARBEITET VON ALEXANDER TABAKOFF Betreuender Lehrer: Prof. Wolfgang Schinwald VERÖFFENTLICHT AM 26.2.2001 PROZESSORARCHITEKTUR INHALTSVERZEICHNIS: 1 Historische / allgemeine Einführung 1.1Die Anwendungsbereiche von Prozessoren 1.2Der erste Prozessor 1.3Die Entwicklung bis zum 586 1.4Der AMD Athlon und der Pentium III - Entwicklungsgeschichte 2 Grundlegende Dinge zur Prozessorarchitektur und dem Bau von Prozessoren 2.1Physikalisch 2.1.1Der Aufbau eines Transistors 2.1.2Die Auswirkungen in die Praxis 2.2Logisch 2.3Die Herstellung von Prozessoren und ihre Grenzen 2.4Der Von-Neumann-Rechner 3 Die Prozessorarchitektur des AMD Athlon im Vergleich zu seinen Konkurrenten 3.1Das Design des AMD Athlon 3.2Das Bussytem des AMD Athlon 3.3Die Cachearchitektur des AMD Athlon 3.4Vor- und Nachteile gegenüber anderen Designs 3.5Interview mit Jan Gütter, Public Relations Sprecher von AMD 4 Anhang 4.1Der Grund dieser Arbeit 4.2Glossar 4.3Literaturverzeichnis 4.4Begleitprotokoll 4.5Bildnachweis Inhaltsverzeichnis: - Seite 2 PROZESSORARCHITEKTUR 1 HISTORISCHE / ALLGEMEINE EINFÜHRUNG 1.1Die Anwendungsbereiche von Prozessoren Prozessoren haben heute verschiedenste Anwendungsbereiche. Sie werden in Autos, Set Top Boxen, Spielekonsolen, Handys, Taschenrechnern, PCs usw. verwendet. Dabei macht der Marktanteil der PC Prozessoren nur rund 2%1 aus. Trotz dieser vergleichsweise geringen Produktion genießen PC Prozessoren einen bedeutend höheren Bekanntheitsgrad. Fast jeder kennt PC Prozessoren wie den Intel Pentium
  • Optimizing Software Performance Using Vector Instructions Invited Talk at Speed-B Conference, October 19–21, 2016, Utrecht, the Netherlands

    Optimizing Software Performance Using Vector Instructions Invited Talk at Speed-B Conference, October 19–21, 2016, Utrecht, the Netherlands

    Agner Fog, Technical University of Denmark Optimizing software performance using vector instructions Invited talk at Speed-B conference, October 19–21, 2016, Utrecht, The Netherlands. Abstract Microprocessor factories have a problem obeying Moore's law because of physical limitations. The answer is increasing parallelism in the form of multiple CPU cores and vector instructions (Single Instruction Multiple Data - SIMD). This is a challenge to software developers who have to adapt to a moving target of new instruction set additions and increasing vector sizes. Most of the software industry is lagging several years behind the available hardware because of these problems. Other challenges are tasks that cannot easily be executed with vector instructions, such as sequential algorithms and lookup tables. The talk will discuss methods for overcoming these problems and utilize the continuously growing power of microprocessors on the market. A few problems relevant to cryptographic software will be covered, and the outlook for the future will be discussed. Find more on these topics at author website: www.agner.org/optimize Moore's law The clock frequency has stopped growing due to physical limitations. Instead, the number of CPU cores and the size of vector registers is growing. Hierarchy of bottlenecks Program installation Program load, JIT compile, DLL's System database Network access Speed → File input/output Graphical user interface RAM access, cache utilization Algorithm Dependency chains CPU pipeline and execution units Remove
  • Multi-Platform Auto-Vectorization

    Multi-Platform Auto-Vectorization

    H-0236 (H0512-002) November 30, 2005 Computer Science IBM Research Report Multi-Platform Auto-Vectorization Dorit Naishlos, Richard Henderson* IBM Research Division Haifa Research Laboratory Mt. Carmel 31905 Haifa, Israel *Red Hat Research Division Almaden - Austin - Beijing - Haifa - India - T. J. Watson - Tokyo - Zurich LIMITED DISTRIBUTION NOTICE: This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. I thas been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g ,. payment of royalties). Copies may be requested from IBM T. J. Watson Research Center , P. O. Box 218, Yorktown Heights, NY 10598 USA (email: [email protected]). Some reports are available on the internet at http://domino.watson.ibm.com/library/CyberDig.nsf/home . Multi-Platform Auto-Vectorization Dorit Naishlos Richard Henderson IBM Haifa Labs Red Hat [email protected] [email protected] Abstract. The recent proliferation of the Single Instruction Multiple Data (SIMD) model has lead to a wide variety of implementations. These have been incorporated into many platforms, from gaming machines and em- bedded DSPs to general purpose architectures. In this paper we present an automatic vectorizer as implemented in GCC - the most multi-targetable compiler available today. We discuss the considerations that are involved in developing a multi-platform vectorization technology, and demonstrate how our vectorization scheme is suited to a variety of SIMD architectures.
  • A Bibliography of Publications in IEEE Micro

    A Bibliography of Publications in IEEE Micro

    A Bibliography of Publications in IEEE Micro Nelson H. F. Beebe University of Utah Department of Mathematics, 110 LCB 155 S 1400 E RM 233 Salt Lake City, UT 84112-0090 USA Tel: +1 801 581 5254 FAX: +1 801 581 4148 E-mail: [email protected], [email protected], [email protected] (Internet) WWW URL: http://www.math.utah.edu/~beebe/ 16 September 2021 Version 2.108 Title word cross-reference -Core [MAT+18]. -Cubes [YW94]. -D [ASX19, BWMS19, DDG+19, Joh19c, PZB+19, ZSS+19]. -nm [ABG+16, KBN16, TKI+14]. #1 [Kah93i]. 0.18-Micron [HBd+99]. 0.9-micron + [Ano02d]. 000-fps [KII09]. 000-Processor $1 [Ano17-58, Ano17-59]. 12 [MAT 18]. 16 + + [ABG+16]. 2 [DTH+95]. 21=2 [Ste00a]. 28 [BSP 17]. 024-Core [JJK 11]. [KBN16]. 3 [ASX19, Alt14e, Ano96o, + AOYS95, BWMS19, CMAS11, DDG+19, 1 [Ano98s, BH15, Bre10, PFC 02a, Ste02a, + + Ste14a]. 1-GHz [Ano98s]. 1-terabits DFG 13, Joh19c, LXB07, LX10, MKT 13, + MAS+07, PMM15, PZB+19, SYW+14, [MIM 97]. 10 [Loc03]. 10-Gigabit SCSR93, VPV12, WLF+08, ZSS+19]. 60 [Gad07, HcF04]. 100 [TKI+14]. < [BMM15]. > [BMM15]. 2 [Kir84a, Pat84, PSW91, YSMH91, ZACM14]. [WHCK18]. 3 [KBW95]. II [BAH+05]. ∆ 100-Mops [PSW91]. 1000 [ES84]. 11- + [Lyl04]. 11/780 [Abr83]. 115 [JBF94]. [MKG 20]. k [Eng00j]. µ + [AT93, Dia95c, TS95]. N [YW94]. x 11FO4 [ASD 05]. 12 [And82a]. [DTB01, Dur96, SS05]. 12-DSP [Dur96]. 1284 [Dia94b]. 1284-1994 [Dia94b]. 13 * [CCD+82]. [KW02]. 1394 [SB00]. 1394-1955 [Dia96d]. 1 2 14 [WD03]. 15 [FD04]. 15-Billion-Dollar [KR19a].
  • Compiler-Based Data Prefetching and Streaming Non-Temporal Store Generation for the Intel R Xeon Phitm Coprocessor

    Compiler-Based Data Prefetching and Streaming Non-Temporal Store Generation for the Intel R Xeon Phitm Coprocessor

    Compiler-based Data Prefetching and Streaming Non-temporal Store Generation for the Intel R Xeon PhiTM Coprocessor Rakesh Krishnaiyer†, Emre K¨ult¨ursay†‡, Pankaj Chawla†, Serguei Preis†, Anatoly Zvezdin†, and Hideki Saito† † Intel Corporation ‡ The Pennsylvania State University TM Abstract—The Intel R Xeon Phi coprocessor has software used, and generating them. In this paper, we: TM prefetching instructions to hide memory latencies and spe- • Present how the Intel R Xeon Phi coprocessor soft- cial store instructions to save bandwidth on streaming non- ware prefetch and non-temporal streaming store instructions temporal store operations. In this work, we provide details on R compiler-based generation of these instructions and evaluate are generated by the Intel Composer XE 2013, TM their impact on the performance of the Intel R Xeon Phi • Evaluate the impact of these mechanisms on the overall coprocessor using a wide range of parallel applications with performance of the coprocessor using a variety of parallel different characteristics. Our results show that the Intel R applications with different characteristics. Composer XE 2013 compiler can make effective use of these Our experimental results demonstrate that (i) a large mechanisms to achieve significant performance improvements. number of applications benefit significantly from software prefetching instructions (on top of hardware prefetching) that I. INTRODUCTION are generated automatically by the compiler for the Intel R TM TM The Intel R Xeon Phi coprocessor based on Intel R Xeon Phi coprocessor, (ii) some benchmarks can further Many Integrated Core Architecture (Intel R MIC Architec- improve when compiler options that control prefetching ture) is a many-core processor with long vector (SIMD) units behavior are used (e.g., to enable indirect prefetching), targeted for highly parallel workloads in the High Perfor- and (iii) many applications benefit from compiler generated mance Computing (HPC) segment.
  • Optimizing SIMD Execution in HW/SW Co-Designed Processors

    Optimizing SIMD Execution in HW/SW Co-Designed Processors

    Optimizing SIMD Execution in HW/SW Co-designed Processors Rakesh Kumar Department of Computer Architecture Universitat Politècnica de Catalunya Advisors: Alejandro Martínez Intel Barcelona Research Center Antonio González Intel Barcelona Research Center Universitat Politècnica de Catalunya A thesis submitted in fulfillment of the requirements for the degree of Doctor of Philosophy / Doctor per la UPC ABSTRACT SIMD accelerators are ubiquitous in microprocessors from different computing domains. Their high compute power and hardware simplicity improve overall performance in an energy efficient manner. Moreover, their replicated functional units and simple control mechanism make them amenable to scaling to higher vector lengths. However, code generation for these accelerators has been a challenge from the days of their inception. Compilers generate vector code conservatively to ensure correctness. As a result they lose significant vectorization opportunities and fail to extract maximum benefits out of SIMD accelerators. This thesis proposes to vectorize the program binary at runtime in a speculative manner, in addition to the compile time static vectorization. There are different environments that support runtime profiling and optimization support required for dynamic vectorization, one of most prominent ones being: 1) Dynamic Binary Translators and Optimizers (DBTO) and 2) Hardware/Software (HW/SW) Co-designed Processors. HW/SW co-designed environment provides several advantages over DBTOs like transparent incorporations of new hardware features, binary compatibility, etc. Therefore, we use HW/SW co-designed environment to assess the potential of speculative dynamic vectorization. Furthermore, we analyze vector code generation for wider vector units and find out that even though SIMD accelerators are amenable to scaling from hardware point of view, vector code generation at higher vector length is even more challenging.
  • Vybrid Controllers Technical Overview

    Vybrid Controllers Technical Overview

    TM June 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. • Overview of Vybrid Family • Vybrid Tower Board • Vybrid System Modules • QuadSPI Flash • Vybrid Clock System • Vybrid Power System • Vybrid Boot Operation • High Assurance Boot • Vybrid Trusted Execution • LinuxLink and MQX Embedded Software • DS-5 compiler TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 2 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg.