DOCSLIB.ORG

Optimizing SIMD Execution in HW/SW Co-Designed Processors

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Optimizing SIMD Execution in HW/SW Co-Designed Processors Optimizing SIMD Execution in HW/SW Co-designed Processors Rakesh Kumar Department of Computer Architecture Universitat Politècnica de Catalunya Advisors: Alejandro Martínez Intel Barcelona Research Center Antonio González Intel Barcelona Research Center Universitat Politècnica de Catalunya A thesis submitted in fulfillment of the requirements for the degree of Doctor of Philosophy / Doctor per la UPC ABSTRACT SIMD accelerators are ubiquitous in microprocessors from different computing domains. Their high compute power and hardware simplicity improve overall performance in an energy efficient manner. Moreover, their replicated functional units and simple control mechanism make them amenable to scaling to higher vector lengths. However, code generation for these accelerators has been a challenge from the days of their inception. Compilers generate vector code conservatively to ensure correctness. As a result they lose significant vectorization opportunities and fail to extract maximum benefits out of SIMD accelerators. This thesis proposes to vectorize the program binary at runtime in a speculative manner, in addition to the compile time static vectorization. There are different environments that support runtime profiling and optimization support required for dynamic vectorization, one of most prominent ones being: 1) Dynamic Binary Translators and Optimizers (DBTO) and 2) Hardware/Software (HW/SW) Co-designed Processors. HW/SW co-designed environment provides several advantages over DBTOs like transparent incorporations of new hardware features, binary compatibility, etc. Therefore, we use HW/SW co-designed environment to assess the potential of speculative dynamic vectorization. Furthermore, we analyze vector code generation for wider vector units and find out that even though SIMD accelerators are amenable to scaling from hardware point of view, vector code generation at higher vector length is even more challenging. The two major factors impeding vectorization for wider SIMD units are: 1) Reduced dynamic instruction stream coverage for vectorization and 2) Large number of permutation instructions. To solve the first problem we propose Variable Length Vectorization that iteratively vectorizes for multiple vector lengths to improve dynamic instruction stream coverage. Secondly, to reduce the number of permutation instructions we propose Selective Writing that selectively writes to different parts of a vector register and avoids permutations. Finally, we tackle the problem of leakage energy in SIMD accelerators. Since SIMD accelerators consume significant amount of real estate on the chip, they become the principle source of leakage if not utilized judiciously. Power gating is one of the most widely used techniques to reduce leakage energy of functional units. However, power gating has its own energy and performance overhead associated with it. We propose to selectively devectorize the vector code when higher SIMD lanes are used intermittently. This selective devectorization keeps the higher SIMD lanes idle and power gated for maximum duration. Therefore, resulting in overall leakage energy reduction. i ii Table of Contents Abstract i List of Figures vii List of Tables xi List of Algorithms xiii 1. Introduction ................................................................................................................. 1 1.1 SIMD Execution Model .................................................................................... 2 1.2 Challenges in SIMD Execution ........................................................................ 3 1.2.1 Static Vectorization Limitations .............................................................. 3 1.2.2 Wider Vector Units .................................................................................. 4 1.2.3 Leakage in SIMD accelerators ................................................................. 5 1.3 Contributions..................................................................................................... 5 1.3.1 Speculative Dynamic Vectorization ........................................................ 5 1.3.2 Vectorizing for Wider Vector Units ........................................................ 6 1.3.3 Dynamic Selective Devectorization ......................................................... 6 1.4 HW/SW Co-designed Processors ..................................................................... 7 1.5 Why HW/SW Co-designed Environment ......................................................... 7 1.6 Thesis Organization .......................................................................................... 8 2. Background ............................................................................................................... 11 2.1 Microarchitectural Innovations to Exploit Parallelism ................................... 12 2.1.1 Extracting Instruction Level Parallelism ............................................... 12 2.1.2 Extracting Thread Level Parallelism ..................................................... 13 2.1.3 Extracting Data Level Parallelism ......................................................... 15 2.2 SIMD ISA Extensions..................................................................................... 16 2.2.1 Intel´s SIMD Extensions ........................................................................ 17 2.2.2 PowerPC Altivec .................................................................................... 20 iii 2.2.3 ARM Neon ............................................................................................. 20 2.3 Code Generation for SIMD Accelerators ....................................................... 21 2.3.1 Traditional Compiler Vectorization ....................................................... 21 2.3.2 Superword Level Parallelism ................................................................. 22 2.3.3 SLP in Presence of Control Flow........................................................... 23 2.3.4 Speculative Dynamic Vectorization ...................................................... 24 2.3.5 Liquid SIMD .......................................................................................... 24 2.3.6 Vapor SIMD........................................................................................... 25 2.4 Code Optimizations ........................................................................................ 25 2.4.1 Static Compiler Optimizations ............................................................... 26 2.4.2 Dynamic Binary Optimizations ............................................................. 26 2.4 Hardware/Software Co-designed Processors .................................................. 28 2.4.1 Memory System in HW/SW Co-designed Processors ........................... 29 2.4.2 TOL translator/optimizer ....................................................................... 30 2.4.3 Hardware Support in HW/SW Co-designed Processors ........................ 32 2.4.4 Salient features of HW/SW Co-designed Processors ............................ 33 3. Experimental Framework ........................................................................................ 35 3.1 Main Components ........................................................................................... 36 3.2 Execution Flow ............................................................................................... 37 3.3 Translation Optimization Layer ...................................................................... 39 3.3.1 Interpretation .......................................................................................... 39 3.3.2 Basic Block Translation ......................................................................... 40 3.3.3 Superblocks and Optimizations ............................................................. 42 3.4 Speculation and Recovery............................................................................... 44 3.5 The Timing Model .......................................................................................... 46 3.6 TOL Configuration ......................................................................................... 48 3.6.1 Optimal Promotion Threshold ............................................................... 49 3.6.2 Optimized Code Distribution ................................................................. 51 3.6.3 Emulation Cost....................................................................................... 52 3.6.4 Dynamic Instruction and Overhead Distribution ................................... 52 3.6.5 Floating Point and Integer Instruction Distribution ............................... 54 3.7 Host ISA Extension......................................................................................... 55 3.8 McPAT ............................................................................................................ 56 iv 3.8.1 Power Modeling ..................................................................................... 57 4. Speculative Dynamic Vectorization ......................................................................... 59 4.1 Introduction ..................................................................................................... 59 4.2 Motivation ....................................................................................................... 61 4.3 Dynamic Vectorization Algorithm ................................................................. 64 4.3.1 The Vectorizer ......................................................................................
Load more

Recommended publications
  • Data-Flow Prescheduling for Large Instruction Windows in Out-Of-Order Processors
    Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors Pierre Michaud, Andr´e Seznec IRISA/INRIA Campus de Beaulieu, 35042 Rennes Cedex, France {pmichaud, seznec}@irisa.fr Abstract We introduce data-flow prescheduling. Instructions are sent to the issue buffer in a predicted data-flow order instead The performance of out-of-order processors increases of the sequential order, allowing a smaller issue buffer. The with the instruction window size. In conventional proces- rationale of this proposal is to avoid using entries in the is- sors, the effective instruction window cannot be larger than sue buffer for instructions which operands are known to be the issue buffer. Determining which instructions from the yet unavailable. issue buffer can be launched to the execution units is a time- In our proposal, this reordering of instructions is accom- critical operation which complexity increases with the issue plished through an array of schedule lines. Each schedule buffer size. We propose to relieve the issue stage by reorder- line corresponds to a different depth in the data-flow graph. ing instructions before they enter the issue buffer. This study The depth of each instruction in the data-flow graph is de- introduces the general principle of data-flow prescheduling. termined, and the instruction is inserted in the correspond- Then we describe a possible implementation. Our prelim- ing schedule line. Lines are consumed by the issue buffer inary results show that data-flow prescheduling makes it sequentially. possible to enlarge the effective instruction window while Section 2 briefly describes issue buffers and discusses re- keeping the issue buffer small.
    [Show full text]
  • Jetson TX2 • NVIDIA Jetson Xavier • GPU Programming • Algorithm Mapping: • Convolutions Parallel Algorithm Execution
    GPU and multicore CPU architectures. Algorithm mapping Contributors: N. Tsapanos, I. Karakostas, I. Pitas Aristotle University of Thessaloniki, Greece Presenter: Prof. Ioannis Pitas Aristotle University of Thessaloniki [email protected] www.multidrone.eu Presentation version 1.3 GPU and multicore CPU architectures. Algorithm mapping • GPU and multicore CPU processing boards • Graphics cards • NVIDIA Jetson TX2 • NVIDIA Jetson Xavier • GPU programming • Algorithm mapping: • Convolutions Parallel algorithm execution • Graphics computing: • Highly parallelizable • Linear algebra parallelization: • Vector inner products: 푐 = 풙푇풚. • Matrix-vector multiplications 풚 = 푨풙. • Matrix multiplications: 푪 = 푨푩. Parallel algorithm execution • Convolution: 풚 = 푨풙 • CNN architectures, linear systems, signal filtering. • Correlation: 풚 = 푨풙 • template matching, tracking. • Signal transforms (DFT, DCT, Haar, etc): • Matrix vector product form: 푿 = 푾풙 • 2D transforms (matrix product form): 푿’ = 푾푿. Processing Units • Multicore (CPU): • MIMD. • Focused on latency. • Best single thread performance. • Manycore (GPU): • SIMD. • Focused on throughput. • Best for embarrassingly parallel tasks. Pascal microarchitecture https://devblogs.nvidia.com/inside-pascal/gp100_block_diagram-2/ Pascal microarchitecture https://devblogs.nvidia.com/inside-pascal/gp100_sm_diagram/ GeForce GTX 1080 • Microarchitecture: Pascal. • DRAM: 8 GB GDDR5X at 10000 MHz. • SMs: 20. • Memory bandwidth: 320 GB/s. • CUDA cores: 2560. • L2 Cache: 2048 KB. • Clock (base/boost): 1607/1733 MHz. • L1 Cache: 48 KB per SM. • GFLOPs: 8873. • Shared memory: 96 KB per SM. GPU and multicore CPU architectures. Algorithm mapping • GPU and multicore CPU processing boards • Graphics cards • NVIDIA Jetson TX2 • NVIDIA Jetson Xavier • GPU programming • Algorithm mapping: • Convolutions ARM Cortex-A57: High-End ARMv8 CPU • ARMv8 architecture • Architecture evolution that extends ARM’s applicability to all markets. • Full ARM 32-bit compatibility, streamlined 64-bit capability.
    [Show full text]
  • REPORT Compaq Chooses SMT for Alpha Simultaneous Multithreading
    VOLUME 13, NUMBER 16 DECEMBER 6, 1999 MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE Compaq Chooses SMT for Alpha Simultaneous Multithreading Exploits Instruction- and Thread-Level Parallelism by Keith Diefendorff Given a full complement of on-chip memory, increas- ing the clock frequency will increase the performance of the As it climbs rapidly past the 100-million- core. One way to increase frequency is to deepen the pipeline. transistor-per-chip mark, the micro- But with pipelines already reaching upwards of 12–14 stages, processor industry is struggling with the mounting inefficiencies may close this avenue, limiting future question of how to get proportionally more performance out frequency improvements to those that can be attained from of these new transistors. Speaking at the recent Microproces- semiconductor-circuit speedup. Unfortunately this speedup, sor Forum, Joel Emer, a Principal Member of the Technical roughly 20% per year, is well below that required to attain the Staff in Compaq’s Alpha Development Group, described his historical 60% per year performance increase. To prevent company’s approach: simultaneous multithreading, or SMT. bursting this bubble, the only real alternative left is to exploit Emer’s interest in SMT was inspired by the work of more and more parallelism. Dean Tullsen, who described the technique in 1995 while at Indeed, the pursuit of parallelism occupies the energy the University of Washington. Since that time, Emer has of many processor architects today. There are basically two been studying SMT along with other researchers at Washing- theories: one is that instruction-level parallelism (ILP) is ton. Once convinced of its value, he began evangelizing SMT abundant and remains a viable resource waiting to be tapped; within Compaq.
    [Show full text]
  • Computer Architecture Out-Of-Order Execution
    Computer Architecture Out-of-order Execution By Yoav Etsion With acknowledgement to Dan Tsafrir, Avi Mendelson, Lihu Rappoport, and Adi Yoaz 1 Computer Architecture 2013– Out-of-Order Execution The need for speed: Superscalar • Remember our goal: minimize CPU Time CPU Time = duration of clock cycle × CPI × IC • So far we have learned that in order to Minimize clock cycle ⇒ add more pipe stages Minimize CPI ⇒ utilize pipeline Minimize IC ⇒ change/improve the architecture • Why not make the pipeline deeper and deeper? Beyond some point, adding more pipe stages doesn’t help, because Control/data hazards increase, and become costlier • (Recall that in a pipelined CPU, CPI=1 only w/o hazards) • So what can we do next? Reduce the CPI by utilizing ILP (instruction level parallelism) We will need to duplicate HW for this purpose… 2 Computer Architecture 2013– Out-of-Order Execution A simple superscalar CPU • Duplicates the pipeline to accommodate ILP (IPC > 1) ILP=instruction-level parallelism • Note that duplicating HW in just one pipe stage doesn’t help e.g., when having 2 ALUs, the bottleneck moves to other stages IF ID EXE MEM WB • Conclusion: Getting IPC > 1 requires to fetch/decode/exe/retire >1 instruction per clock: IF ID EXE MEM WB 3 Computer Architecture 2013– Out-of-Order Execution Example: Pentium Processor • Pentium fetches & decodes 2 instructions per cycle • Before register file read, decide on pairing Can the two instructions be executed in parallel? (yes/no) u-pipe IF ID v-pipe • Pairing decision is based… On data
    [Show full text]
  • CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 1 Datapath of Ooo Execution Processor
    Fiscal Year 2020 Ver. 2021-01-25a Course number: CSC.T433 School of Computing, Graduate major in Computer Science Advanced Computer Architecture 10. Multi-Processor: Distributed Memory and Shared Memory Architecture www.arch.cs.titech.ac.jp/lecture/ACA/ Room No.W936 Kenji Kise, Department of Computer Science Mon 14:20-16:00, Thr 14:20-16:00 kise _at_ c.titech.ac.jp CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 1 Datapath of OoO execution processor Instruction flow Instruction cache Branch handler Instruction fetch Instruction decode Renaming Register file Dispatch Integer Floating-point Memory Memory dataflow RS Instruction window ALU ALU Branch FP ALU Adr gen. Adr gen. Store Reorder buffer (ROB) queue Data cache Register dataflow CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH Reservation station (RS) 2 Growth in clock rate of microprocessors From CAQA 5th edition CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 3 From multi-core era to many-core era Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction, MICRO-36 CSC.T433 Advanced Computer Architecture, Department of Computer Science, TOKYO TECH 4 Aside: What is a window? • A window is a space in the wall of a building or in the side of a vehicle, which has glass in it so that light can come in and you can see out. (Collins) Instruction window 8 6 5 4 7 (a) Instruction window Instructions to be executed for an application Large instruction
    [Show full text]
  • Prozessorarchitektur Am Beispiel Des Amdathlon
    PROZESSORARCHITEKTUR AM BEISPIEL DES AMD ATHLON AUSGEARBEITET VON ALEXANDER TABAKOFF Betreuender Lehrer: Prof. Wolfgang Schinwald VERÖFFENTLICHT AM 26.2.2001 PROZESSORARCHITEKTUR INHALTSVERZEICHNIS: 1 Historische / allgemeine Einführung 1.1Die Anwendungsbereiche von Prozessoren 1.2Der erste Prozessor 1.3Die Entwicklung bis zum 586 1.4Der AMD Athlon und der Pentium III - Entwicklungsgeschichte 2 Grundlegende Dinge zur Prozessorarchitektur und dem Bau von Prozessoren 2.1Physikalisch 2.1.1Der Aufbau eines Transistors 2.1.2Die Auswirkungen in die Praxis 2.2Logisch 2.3Die Herstellung von Prozessoren und ihre Grenzen 2.4Der Von-Neumann-Rechner 3 Die Prozessorarchitektur des AMD Athlon im Vergleich zu seinen Konkurrenten 3.1Das Design des AMD Athlon 3.2Das Bussytem des AMD Athlon 3.3Die Cachearchitektur des AMD Athlon 3.4Vor- und Nachteile gegenüber anderen Designs 3.5Interview mit Jan Gütter, Public Relations Sprecher von AMD 4 Anhang 4.1Der Grund dieser Arbeit 4.2Glossar 4.3Literaturverzeichnis 4.4Begleitprotokoll 4.5Bildnachweis Inhaltsverzeichnis: - Seite 2 PROZESSORARCHITEKTUR 1 HISTORISCHE / ALLGEMEINE EINFÜHRUNG 1.1Die Anwendungsbereiche von Prozessoren Prozessoren haben heute verschiedenste Anwendungsbereiche. Sie werden in Autos, Set Top Boxen, Spielekonsolen, Handys, Taschenrechnern, PCs usw. verwendet. Dabei macht der Marktanteil der PC Prozessoren nur rund 2%1 aus. Trotz dieser vergleichsweise geringen Produktion genießen PC Prozessoren einen bedeutend höheren Bekanntheitsgrad. Fast jeder kennt PC Prozessoren wie den Intel Pentium
    [Show full text]
  • STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers
    2012 Third International Conference on Networking and Computing STRAIGHT: Realizing a Lightweight Large Instruction Window by using Eventually Consistent Distributed Registers Hidetsugu IRIE∗, Daisuke FUJIWARA∗, Kazuki MAJIMA∗, Tsutomu YOSHINAGA∗ ∗The University of Electro-Communications 1-5-1 Chofugaoka, Chofu-shi, Tokyo 182-8585, Japan E-mail: [email protected], [email protected], [email protected], [email protected] Abstract—As the number of cores as well as the network size programs. For scale-out applications, we assume the manycore in a processor chip increases, the performance of each core is processor structure, which consists of a number of STRAIGHT more critical for the improvement of the total chip performance. architecture cores (SAC) that are loosely connected each other. However, to improve the total chip performance, the performance per power or per unit area must be improved, making it difficult Being the first report on this novel processor architecture, in to adopt a conventional approach of superscalar extension. In this paper, we discuss the concept behind STRAIGHT, propose this paper, we explore a new core structure that is suitable for basic principles, and estimate the performance and budget manycore processors. We revisit prior studies of new instruction- expectation. The rest of the paper consists of following sec- level (ILP) and thread-level parallelism (TLP) architectures tions. Section II revisits studies of new architectures that were and propose our novel STRAIGHT processor architecture. By introducing the scheme of distributed key-value-store to the designed to improve the ILP/TLP performance of superscalar register file of clustered microarchitectures, STRAIGHT directly processors, and discusses the dilemma of both scalability executes the operation with large logical registers, which are approach and quick worker approach.
    [Show full text]
  • A Bibliography of Publications in IEEE Micro
    A Bibliography of Publications in IEEE Micro Nelson H. F. Beebe University of Utah Department of Mathematics, 110 LCB 155 S 1400 E RM 233 Salt Lake City, UT 84112-0090 USA Tel: +1 801 581 5254 FAX: +1 801 581 4148 E-mail: [email protected], [email protected], [email protected] (Internet) WWW URL: http://www.math.utah.edu/~beebe/ 16 September 2021 Version 2.108 Title word cross-reference -Core [MAT+18]. -Cubes [YW94]. -D [ASX19, BWMS19, DDG+19, Joh19c, PZB+19, ZSS+19]. -nm [ABG+16, KBN16, TKI+14]. #1 [Kah93i]. 0.18-Micron [HBd+99]. 0.9-micron + [Ano02d]. 000-fps [KII09]. 000-Processor $1 [Ano17-58, Ano17-59]. 12 [MAT 18]. 16 + + [ABG+16]. 2 [DTH+95]. 21=2 [Ste00a]. 28 [BSP 17]. 024-Core [JJK 11]. [KBN16]. 3 [ASX19, Alt14e, Ano96o, + AOYS95, BWMS19, CMAS11, DDG+19, 1 [Ano98s, BH15, Bre10, PFC 02a, Ste02a, + + Ste14a]. 1-GHz [Ano98s]. 1-terabits DFG 13, Joh19c, LXB07, LX10, MKT 13, + MAS+07, PMM15, PZB+19, SYW+14, [MIM 97]. 10 [Loc03]. 10-Gigabit SCSR93, VPV12, WLF+08, ZSS+19]. 60 [Gad07, HcF04]. 100 [TKI+14]. < [BMM15]. > [BMM15]. 2 [Kir84a, Pat84, PSW91, YSMH91, ZACM14]. [WHCK18]. 3 [KBW95]. II [BAH+05]. ∆ 100-Mops [PSW91]. 1000 [ES84]. 11- + [Lyl04]. 11/780 [Abr83]. 115 [JBF94]. [MKG 20]. k [Eng00j]. µ + [AT93, Dia95c, TS95]. N [YW94]. x 11FO4 [ASD 05]. 12 [And82a]. [DTB01, Dur96, SS05]. 12-DSP [Dur96]. 1284 [Dia94b]. 1284-1994 [Dia94b]. 13 * [CCD+82]. [KW02]. 1394 [SB00]. 1394-1955 [Dia96d]. 1 2 14 [WD03]. 15 [FD04]. 15-Billion-Dollar [KR19a].
    [Show full text]
  • Multithreading
    CS 152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Lecture 14 – Multithreading Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste http://inst.eecs.berkeley.edu/~cs152 Last Time Lecture 13: VLIW § In a classic VLIW, compiler is responsible for avoiding all hazards -> simple hardware, complex compiler. § Later VLIWs added more dynamic hardware interlocks, which reduce relative hardware benefits § Use loop unrolling and software pipelining for loops, trace scheduling for more irregular code § Static scheduling difficult in presence of unpredictable branches and variable latency memory § VLIW has failed in general-purpose computing, but still used in deeply embedded processors and DSPs 2 Thread-Level Parallelism (TLP) § Difficult to continue to extract instruction-level parallelism (ILP) from a single sequential thread of control § Many workloads can make use of thread-level parallelism: – TLP from multiprogramming (run independent sequential jobs) – TLP from multithreaded applications (run one job faster using parallel threads) § Multithreading uses TLP to improve utilization of a single processor 3 Multithreading How can we guarantee no dependencies between instructions in a pipeline? One way is to interleave execution of instructions from different program threads on same pipeline Interleave 4 threads, T1-T4, on non-bypassed 5-stage pipe t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 T1:LD x1,0(x2) F D X M W Prior instruction in a T2:ADD x7,x1,x4
    [Show full text]
  • UNIVERSITY of CALIFORNIA, SAN DIEGO Holistic Design for Multi-Core Architectures a Dissertation Submitted in Partial Satisfactio
    UNIVERSITY OF CALIFORNIA, SAN DIEGO Holistic Design for Multi-core Architectures A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science (Computer Engineering) by Rakesh Kumar Committee in charge: Professor Dean Tullsen, Chair Professor Brad Calder Professor Fred Chong Professor Rajesh Gupta Dr. Norman P. Jouppi Professor Andrew Kahng 2006 Copyright Rakesh Kumar, 2006 All rights reserved. The dissertation of Rakesh Kumar is approved, and it is acceptable in quality and form for publication on micro- film: Chair University of California, San Diego 2006 iii DEDICATIONS This dissertation is dedicated to friends, family, labmates, and mentors { the ones who taught me, indulged me, loved me, challenged me, and laughed with me, while I was also busy working on my thesis. To Professor Dean Tullsen for teaching me the values of humility, kind- ness,and caring while trying to teach me football and computer architecture. For always encouraging me to do the right thing. For always letting me be myself. For always believing in me. For always challenging me to dream big. For all his wisdom. And for being an adviser in the truest sense, and more. To Professor Brad Calder. For always caring about me. For being an inspiration. For his trust. For making me believe in myself. For his lies about me getting better at system administration and foosball even though I never did. To Dr Partha Ranganathan. For always being there for me when I would get down on myself. And that happened often. For the long discussions on life, work, and happiness.
    [Show full text]
  • Sony's Emotionally Charged Chip
    VOLUME 13, NUMBER 5 APRIL 19, 1999 MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE Sony’s Emotionally Charged Chip Killer Floating-Point “Emotion Engine” To Power PlayStation 2000 by Keith Diefendorff rate of two million units per month, making it the most suc- cessful single product (in units) Sony has ever built. While Intel and the PC industry stumble around in Although SCE has cornered more than 60% of the search of some need for the processing power they already $6 billion game-console market, it was beginning to feel the have, Sony has been busy trying to figure out how to get more heat from Sega’s Dreamcast (see MPR 6/1/98, p. 8), which has of it—lots more. The company has apparently succeeded: at sold over a million units since its debut last November. With the recent International Solid-State Circuits Conference (see a 200-MHz Hitachi SH-4 and NEC’s PowerVR graphics chip, MPR 4/19/99, p. 20), Sony Computer Entertainment (SCE) Dreamcast delivers 3 to 10 times as many 3D polygons as and Toshiba described a multimedia processor that will be the PlayStation’s 34-MHz MIPS processor (see MPR 7/11/94, heart of the next-generation PlayStation, which—lacking an p. 9). To maintain king-of-the-mountain status, SCE had to official name—we refer to as PlayStation 2000, or PSX2. do something spectacular. And it has: the PSX2 will deliver Called the Emotion Engine (EE), the new chip upsets more than 10 times the polygon throughput of Dreamcast, the traditional notion of a game processor.
    [Show full text]
  • Commemorative Booklet for the Thirty-Fifth Asilomar Microcomputer Workshop April 15-17, 2009
    35 Commemorative Booklet for the Thirty-Fifth Asilomar Microcomputer Workshop April 15-17, 2009 Programs from the 1975-2009 Workshops This file available at www.amw.org AMW: 3dh Workshop Prologue - Ted Laliotis The Asilomar Microcomputer Workshop (AMW) has played a very important role during its 30 years ofexistence. Perhaps, that is why it continues to be well attended. The workshop was founded in 1975 as an IEEE technical workshop sponsored by the Western Area Committee ofthe IEEE Computer Society. The intentional lack of written proceedings and the exclusion of general press representatives was perhaps the most distinctive characteristic of AMW that made it so special and successful. This encouraged the scientists and engineers who were at the cutting edge ofthe technology, the movers and shakers that shaped Silicon Valley, the designers of the next generation microprocessors, to discuss and debate freely the various issues facing microprocessors. In fact, many features, or lack of, were born during the discussions and debates at AMW. We often referred to AMW and its attendees as the bowels of Silicon Valley, even though attendees came from all over the country, and the world. Another characteristic that made AMW special was the "required" participation and contribution by all attendees. Every applicant to attend AMW had to convince the committee that he had something to contribute by speaking during one of the sessions or during the open mike session. In the event that someone slipped through and was there only to listen, that person was not invited back the following year. The decades ofthe 70's and 80's were probably the defining decades for the amazing explosion of microcomputers.
    [Show full text]