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Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
Microcode Revision Guidance August 31, 2019 MCU Recommendations
Vxworks Architecture Supplement, 6.2
CPUID Handling for Guests
SIMD Extensions
Multiprocessing Contents
Intermediate Intel X86: Assembly, Architecture, Applications, and Alliteration
Intel® Xeon® E-2100 Processor Family Datasheet, Vol. 1
Intel® Software Guard Extensions (Intel® SGX)
Alphaserver ES40 Service Guide
Computer Architectures an Overview
Intel Processor Identification and the CPUID Instruction
6Th Generation Intel® Processor Family
Intel® Architecture Instruction Set Extensions and Future Features
The X86 Is Dead. Long Live the X86!
10Th Gen Intel® Core™ Processor Families Datasheet, Vol. 1
Intel® Processor Identification and the CPUID Instruction
Intel Processor Identification and the CPUID Instruction
Top View
Intel® Trusted Execution Technology Preliminary Architecture Specification
Intel SGX Virtualization KVM Forum 2018 Traditional VM Landscape
Maccpuid V3.0 Info CPU Model: Intel(R)
Intel SGX Explained
Intel® 64 and IA-32 Architectures Software Developer's Manual
Cryptography Processing with 3Rd Gen Intel Xeon Scalable Processors
Everything You Should Know About Intel SGX Performance On
Intel® Architecture Instruction Set Extensions Programming Reference
Vmotion Between Apples and Oranges Understanding CPU
How to Detect New Instruction Support in the 4Th Generation Intel® Core™ Processor Family
Vmware Vmotion and CPU Compatibility Vmware® Infrastructure 3
PC Magazine® Linux® Solutions
Using Advanced Vector Extensions AVX-512 for MPI Reductions
Simplex: Repurposing Intel® Memory Protection Extensions for Information Hiding Salvaging Endangered Hardware Features for Security
Intel® Architecture Instruction Set Extensions Programming Reference
The Microarchitecture of Intel, AMD and VIA Cpus: an Optimization Guide for Assembly Programmers and Compiler Makers
Intel® Software Guard Extensions Developer Guide
Intel® SSE4 Programming Reference
An Exploratory Analysis of Microcode As a Building Block for System Defenses
Second Generation Intel® Xeon® Scalable Processors
Automatic Core Specialization for AVX-512 Applications
Cross Platform Feature Comparison
Vxworks® 5.5
Intel® SSE4 Programming Reference
Intel® Memory Protection Extensions Enabling Guide
CPUID Specification
Intel® Processor Identification and the CPUID Instruction Application Note
4. Instruction Tables Lists of Instruction Latencies, Throughputs and Micro-Operation Breakdowns for Intel, AMD, and VIA Cpus
Secure Processors Part II: Intel SGX Security Analysis and MIT Sanctum Architecture
Intel® Software Guard Extensions (Intel® SGX) SGX2
Intel® SSE4 Programming Reference
Intel® 64 and IA-32 Architectures Optimization Reference Manual
Intel® AVX-512
6Th Generation Intel® Processor Family
Architecture-Instruction-Set-Extensions-Programming-Reference-812319.Pdf
Linux Kernel User Documentation Release 4.13.0-Rc4+
Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
Intel® Memory Protection Extensions (Intel® MPX) Enabling Guide
Intel® Trusted Execution Technology (Intel® TXT)
Fair Scheduling for AVX2 and AVX-512 Workloads
Software Guard Extensions Programming Reference
DPD Presentation Template Based on New Intel Foil Format
Core Specialization for AVX-512 Using Fault-And-Migrate
Analysis of Intel IA-64 Processor Support for a Secure Virtual Machine Monitor
Prescott New Instructions Software Developer's Guide
Intel® Architecture Instruction Set Extensions and Future Features Programming Reference