DOCSLIB.ORG

Intel® Xeon® E-2100 Processor Family Datasheet, Vol. 1

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Intel® Xeon® E-2100 Processor Family Datasheet, Vol. 1 Intel® Xeon® E-2100 Processor Family Datasheet, Volume 1 of 2 August 2018 Revision 001 Document Number: 338012-001 Legal Lines and Disclaimers Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/ technology/turboboost. Warning: Altering PC clock or memory frequency and/or voltage may (i) reduce system stability and use life of the system, memory and processor; (ii) cause the processor and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system data integrity. Intel assumes no responsibility that the memory, included if used with altered clock frequencies and/or voltages, will be fit for any particular purpose. Check with memory manufacturer for warranty and additional details. Intel does not control or audit third-party benchmark data or the web sites referenced in this document. You should visit the referenced web site and confirm whether referenced data are accurate. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548- 4725 or by visiting www.intel.com/design/literature.htm. Intel, Intel Core, Intel SpeedStep, Intel VTune, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2018, Intel Corporation. All rights reserved. 2 Intel® Xeon® E-2100 Processor Family Datasheet, Volume 1 of 2, August 2018 Contents 1Introduction..............................................................................................................9 1.1 Supported Technologies ..................................................................................... 12 1.2 Power Management Support ............................................................................... 12 1.2.1 Processor Core Power Management........................................................... 12 1.2.2 System Power Management..................................................................... 12 1.2.3 Memory Controller Power Management...................................................... 13 1.2.4 Processor Graphics Power Management ..................................................... 13 1.3 Thermal Management Support ............................................................................ 13 1.4 Package Support ............................................................................................... 14 1.5 Ballout Information............................................................................................ 14 1.6 Processor Testability .......................................................................................... 14 1.7 Terminology ..................................................................................................... 14 1.8 Related Documents ........................................................................................... 16 2Interfaces................................................................................................................ 18 2.1 System Memory Interface .................................................................................. 18 2.1.1 System Memory Technology Supported ..................................................... 18 2.1.2 System Memory Timing Support............................................................... 19 2.1.3 System Memory Organization Modes......................................................... 20 2.1.4 System Memory Frequency...................................................................... 21 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA).......... 21 2.1.6 Data Scrambling .................................................................................... 22 2.1.7 DDR I/O Interleaving .............................................................................. 22 2.1.8 Data Swapping ...................................................................................... 23 2.1.9 DRAM Clock Generation........................................................................... 23 2.1.10 DRAM Reference Voltage Generation......................................................... 23 2.2 PCI Express* Graphics Interface (PEG)................................................................. 23 2.2.1 PCI Express Support ............................................................................... 23 2.2.2 PCI Express Architecture ......................................................................... 25 2.2.3 PCI Express Configuration Mechanism ....................................................... 26 2.2.4 PCI Express Equalization Methodology....................................................... 26 2.3 Direct Media Interface (DMI)............................................................................... 27 2.3.1 DMI Lane Reversal and Polarity Inversion .................................................. 27 2.3.2 DMI Error Flow....................................................................................... 28 2.3.3 DMI Link Down ...................................................................................... 28 2.4 Processor Graphics ............................................................................................ 29 2.4.1 Operating Systems Support ..................................................................... 29 2.4.2 API Support (Windows*) ......................................................................... 29 2.4.3 Media Support (Intel® QuickSync and Clear Video Technology HD) ............... 30 2.4.4 Switchable/Hybrid Graphics ..................................................................... 32 2.4.5 Gen 9 LP Video Analytics ......................................................................... 33 2.4.6 Gen 9 LP (9th Generation Low Power) Block Diagram .................................. 34 2.4.7 GT2 Graphic Frequency ........................................................................... 34 2.5 Display Interfaces ............................................................................................. 35 2.5.1 DDI Configuration .................................................................................. 35 2.5.2 eDP* Bifurcation .................................................................................... 36 2.5.3 Display Technologies .............................................................................. 36 2.5.4 DisplayPort* .......................................................................................... 39 2.5.5 High-Definition Multimedia Interface (HDMI*) ............................................ 39 2.5.6 Digital Video Interface (DVI).................................................................... 40 2.5.7 embedded DisplayPort* (eDP*) ................................................................ 40 Intel® Xeon® E-2100 Processor Family 3 Datasheet, Volume 1 of 2, August 2018 2.5.8 Integrated Audio ....................................................................................40 2.5.9 Multiple Display Configurations (Dual Channel DDR) ....................................41 2.5.10 Multiple Display Configurations (Single Channel DDR) ..................................42 2.5.11 High-Bandwidth Digital Content Protection (HDCP) ......................................42 2.5.12 Display Link Data Rate Support ................................................................43 2.5.13 Display Bit Per Pixel (BPP) Support............................................................44 2.5.14 Display Resolution per Link Width .............................................................44 2.6 Platform Environmental Control Interface (PECI) ....................................................44
Load more

Recommended publications
  • Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
    Intel® Architecture Instruction Set Extensions and Future Features Programming Reference 319433-037 MAY 2019 Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifica- tions. Current characterized errata are available on request. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Intel does not guarantee the availability of these interfaces in any future product. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1- 800-548-4725, or by visiting http://www.intel.com/design/literature.htm. Intel, the Intel logo, Intel Deep Learning Boost, Intel DL Boost, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation in the U.S.
    [Show full text]
  • Microcode Revision Guidance August 31, 2019 MCU Recommendations
    microcode revision guidance August 31, 2019 MCU Recommendations Section 1 – Planned microcode updates • Provides details on Intel microcode updates currently planned or available and corresponding to Intel-SA-00233 published June 18, 2019. • Changes from prior revision(s) will be highlighted in yellow. Section 2 – No planned microcode updates • Products for which Intel does not plan to release microcode updates. This includes products previously identified as such. LEGEND: Production Status: • Planned – Intel is planning on releasing a MCU at a future date. • Beta – Intel has released this production signed MCU under NDA for all customers to validate. • Production – Intel has completed all validation and is authorizing customers to use this MCU in a production environment.
    [Show full text]
  • Vxworks Architecture Supplement, 6.2
    VxWorks Architecture Supplement VxWorks® ARCHITECTURE SUPPLEMENT 6.2 Copyright © 2005 Wind River Systems, Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means without the prior written permission of Wind River Systems, Inc. Wind River, the Wind River logo, Tornado, and VxWorks are registered trademarks of Wind River Systems, Inc. Any third-party trademarks referenced are the property of their respective owners. For further information regarding Wind River trademarks, please see: http://www.windriver.com/company/terms/trademark.html This product may include software licensed to Wind River by third parties. Relevant notices (if any) are provided in your product installation at the following location: installDir/product_name/3rd_party_licensor_notice.pdf. Wind River may refer to third-party documentation by listing publications or providing links to third-party Web sites for informational purposes. Wind River accepts no responsibility for the information provided in such third-party documentation. Corporate Headquarters Wind River Systems, Inc. 500 Wind River Way Alameda, CA 94501-1153 U.S.A. toll free (U.S.): (800) 545-WIND telephone: (510) 748-4100 facsimile: (510) 749-2010 For additional contact information, please visit the Wind River URL: http://www.windriver.com For information on how to contact Customer Support, please visit the following URL: http://www.windriver.com/support VxWorks Architecture Supplement, 6.2 11 Oct 05 Part #: DOC-15660-ND-00 Contents 1 Introduction
    [Show full text]
  • CPUID Handling for Guests
    CPUID handling for guests Andrew Cooper Citrix XenServer Friday 26th August 2016 Andrew Cooper (Citrix XenServer) CPUID handling for guests Friday 26th August 2016 1 / 11 Return information about the processor I Identifying information (GenuineIntel, AuthenticAMD, etc) I Feature information (available instructions, MSRs, etc) I Topology information (sockets, cores, threads, caches, TLBs, etc) Unpriveleged I Useable by userspace I Doesn't trap to supervisor mode The CPUID instruction Introduced in 1993 I Takes input parameters in %eax and %ecx I Returns values in %eax, %ebx, %ecx and %edx Andrew Cooper (Citrix XenServer) CPUID handling for guests Friday 26th August 2016 2 / 11 Unpriveleged I Useable by userspace I Doesn't trap to supervisor mode The CPUID instruction Introduced in 1993 I Takes input parameters in %eax and %ecx I Returns values in %eax, %ebx, %ecx and %edx Return information about the processor I Identifying information (GenuineIntel, AuthenticAMD, etc) I Feature information (available instructions, MSRs, etc) I Topology information (sockets, cores, threads, caches, TLBs, etc) Andrew Cooper (Citrix XenServer) CPUID handling for guests Friday 26th August 2016 2 / 11 The CPUID instruction Introduced in 1993 I Takes input parameters in %eax and %ecx I Returns values in %eax, %ebx, %ecx and %edx Return information about the processor I Identifying information (GenuineIntel, AuthenticAMD, etc) I Feature information (available instructions, MSRs, etc) I Topology information (sockets, cores, threads, caches, TLBs, etc) Unpriveleged I Useable by userspace I Doesn't trap to supervisor mode Andrew Cooper (Citrix XenServer) CPUID handling for guests Friday 26th August 2016 2 / 11 Some kernels binary patch themselves (e.g.
    [Show full text]
  • SIMD Extensions
    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
    [Show full text]
  • P72 User Guide
    P72 User Guide Note: Before using this information and the product it supports, ensure that you read and understand the following: • Safety and Warranty Guide • Setup Guide • “Important safety information” on page iii Lenovo makes constant improvement on the documentation of your computer, including this User Guide. To get all the latest documents, go to: https://support.lenovo.com Depending on the version of operating systems, some user interface instructions might not be applicable to your computer. Second Edition (April 2019) © Copyright Lenovo 2019. LIMITED AND RESTRICTED RIGHTS NOTICE: If data or software is delivered pursuant to a General Services Administration “GSA” contract, use, reproduction, or disclosure is subject to restrictions set forth in Contract No. GS- 35F-05925. Contents Important safety information . iii Using the TrackPoint pointing device. 19 Read this first. iii Using the trackpad with buttons . 20 Important information about using your computer . iii Using the trackpad touch gestures . 20 Conditions that require immediate action . v Customizing the ThinkPad pointing device . 21 Service and upgrades . vi Replacing the cap on the pointing stick . 21 Power cords and power adapters . vii Power management . 22 Extension cords and related devices. vii Using the ac power adapter . 22 Plugs and outlets . viii Using the battery . 22 Power supply statement . viii Managing the battery power . 24 External devices . ix Power-saving modes . 24 General battery notice . ix Cabled Ethernet connections . 24 Notice for built-in rechargeable battery. ix Wireless connections . 25 Notice for non-rechargeable coin-cell battery . x Using the wireless-LAN connection . 25 Heat and product ventilation . xi Using the Bluetooth connection.
    [Show full text]
  • Performance Best Practices for Vmware Workstation Vmware Workstation 7.0
    Performance Best Practices for VMware Workstation VMware Workstation 7.0 This document supports the version of each product listed and supports all subsequent versions until the document is replaced by a new edition. To check for more recent editions of this document, see http://www.vmware.com/support/pubs. EN-000294-00 Performance Best Practices for VMware Workstation You can find the most up-to-date technical documentation on the VMware Web site at: http://www.vmware.com/support/ The VMware Web site also provides the latest product updates. If you have comments about this documentation, submit your feedback to: [email protected] Copyright © 2007–2009 VMware, Inc. All rights reserved. This product is protected by U.S. and international copyright and intellectual property laws. VMware products are covered by one or more patents listed at http://www.vmware.com/go/patents. VMware is a registered trademark or trademark of VMware, Inc. in the United States and/or other jurisdictions. All other marks and names mentioned herein may be trademarks of their respective companies. VMware, Inc. 3401 Hillview Ave. Palo Alto, CA 94304 www.vmware.com 2 VMware, Inc. Contents About This Book 5 Terminology 5 Intended Audience 5 Document Feedback 5 Technical Support and Education Resources 5 Online and Telephone Support 5 Support Offerings 5 VMware Professional Services 6 1 Hardware for VMware Workstation 7 CPUs for VMware Workstation 7 Hyperthreading 7 Hardware-Assisted Virtualization 7 Hardware-Assisted CPU Virtualization (Intel VT-x and AMD AMD-V)
    [Show full text]
  • Product Change Notification #111151
    Product Change Notification #111151 - 01 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Should you have any issues with the timeline or content of this change, please contact the Intel Representative(s) for your geographic location listed below. No response from customers will be deemed as acceptance of the change and the change will be implemented pursuant to the key milestones set forth in this attached PCN. Americas Contact: [email protected] Asia Pacific Contact: [email protected] Europe Email: [email protected] Japan Email: [email protected] Copyright © Intel Corporation 2011. Other names and brands may be claimed as the property of others. BunnyPeople, Celeron, Celeron Inside, Centrino, Centrino Inside, Cilk, Core Inside, i960, Intel, the Intel logo, Intel AppUp, Intel Atom, Intel Atom Inside, Intel Core,
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • Intermediate Intel X86: Assembly, Architecture, Applications, and Alliteration
    Intermediate Intel x86: Assembly, Architecture, Applications, and Alliteration Xeno Kovah – 2010 xkovah at gmail All materials are licensed under a Creative Commons “Share Alike” license. • http://creativecommons.org/licenses/by-sa/3.0/ 2 Credits Page • Your name here! Just tell me something I didn’t know which I incorporate into the slides! • Veronica Kovah for reviewing slides and suggesting examples & questions to answer • Murad Kahn for Google NaCl stuff 3 Answer me these questions three • What, is your name? • What, is your quest? • What…is your department? 4 Agenda • Part 1 - Segmentation • Part 2 - Paging • Part 3 - Interrupts • Part 4 – Debugging, I/O, Misc fun on a bun 5 Miss Alaineous • Questions: Ask ‘em if you got ‘em – If you fall behind and get lost and try to tough it out until you understand, it’s more likely that you will stay lost, so ask questions ASAP. • Browsing the web and/or checking email during class is a great way to get lost ;) • 2 hours, 10 min break, 2 hours, 1 hour lunch, 1 hour at a time with 5 minute breaks after lunch • Adjusted depending on whether I’m running fast or slow (or whether people are napping 6 after lunch :P) Class Scope • We’re going to only be talking about 32bit architecture (also called IA-32). No 16bit or 64bit. • Also not really going to deal with floating point assembly or registers since you don’t run into them much unless you’re analyzing math/3d code. • This class focuses on diving deeper into architectural features • Some new instructions will be covered, but mostly in support of understanding the architectural topics, only two are learning new instruction’s sake.
    [Show full text]
  • Product Change Notification 111325
    Product Change Notification 111325 - 01 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Should you have any issues with the timeline or content of this change, please contact the Intel Representative(s) for your geographic location listed below. No response from customers will be deemed as acceptance of the change and the change will be implemented pursuant to the key milestones set forth in this attached PCN. Americas Contact: [email protected] Asia Pacific/PRC Contact: [email protected] Europe Email: [email protected] Japan Email: [email protected] Copyright © Intel Corporation 2012. Other names and brands may be claimed as the property of others. BunnyPeople, Celeron, Celeron Inside, Centrino, Centrino Inside, Cilk, Core Inside, i960, Intel, the Intel logo, Intel AppUp, Intel Atom, Intel Atom Inside, Intel Core,
    [Show full text]
  • Enhanced Intel Speedstep Technology for the Intel Pentium M Processor
    Enhanced Intel® SpeedStep® Technology for the Intel® Pentium® M Processor White Paper March 2004 Order Number: 301170-001 ® ® ® ® Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. This document as well as the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document.
    [Show full text]