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Hindawi Publishing Corporation Active and Passive Electronic Components Volume 2008, Article ID 632549, 6 pages doi:10.1155/2008/632549

Research Article Ka Band Phase Locked Loop Oscillator Dielectric Resonator Oscillator for Satellite EHF Band Receiver

S. Coco,1 F. Di Maggio,2 A. Laudani,1 and I. Pomona2

1 DIEES, University of Catania, V. A. Doria 6, 95125 Catania, Italy 2 Selex Communications, V. S. Sonnino 6, 95045 Misterbianco (CT), Italy

Correspondence should be addressed to A. Laudani, [email protected]

Received 30 November 2007; Revised 5 May 2008; Accepted 28 July 2008

Recommended by T. Kalkur

This paper describes the design and fabrication of a Ka Band PLL DRO having a fundamental oscillation frequency of 19.250 GHz, used as local oscillator in the low-noise block of a down converter (LNB) for an EHF band receiver. Apposite circuital models have been created to describe the behaviour of the dielectric resonator and of the active component used in the oscillator core. The DRO characterization and measurements have shown very good agreement with simulation results. A good phase noise performance is obtained by using a very high Q dielectric resonator.

Copyright © 2008 S. Coco et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

1. INTRODUCTION totypes have been constructed and a full characterization has been carried out and the measurements show very good In satellite network links, the phase noise performance and agreement with simulation results and then the PLL DRO has the required spectral purity of the local oscillator of the been integrated in a low-noise block down converter for EHF LNB receiver are very important issues [1–3]. In this case, band satellite communication terminals. a fundamental local oscillator locked to a very stable external The design, simulations, fabrication, and measurements reference can be the best architectural solution. have been carried out at Selex-Communications site of In this paper, we present the design and fabrication of Misterbianco (CT), Italy. a Ka band phase locked loop (PLL) dielectric resonator oscillator (DRO) used as local oscillator in the low-noise 2. OSCILLATOR DESIGN blockofadownconverter(LNB)foranEHFbandreceiver. In order to obtain the best performance in terms of The fundamental oscillation frequency is 19250 GHz. The low-phase noise and output spurious the dielectric res- architecture of the DRO circuit is based on a series feedback onator oscillator architecture at the fundamental frequency network, exhibiting a good performance in terms of a (19250 GHz) has been chosen. A good phase noise per- low drift of the oscillation frequency with respect to load formance is obtained by using a very high Q dielectric variations [4–7]. A GaAs FET (Excelics EPB018A7) was resonator. In order to analyze the behavior of the dielectric chosen as active component both for its easy assembling resonator and the active component used in the oscillator and for its good gain and noise performance at working core, apposite circuital models have been created. The circuit frequencies. simulations have been performed by using the harmonic Because of the scarce information provided by the balance solver available in advanced design system (ADS) manufacturer for this component (only S parameters and simulation tool. gain at 1 dB compression point are given), it has been The oscillator circuit is fabricated by using SMT com- necessary to create an apposite nonlinear model to be used ponents mounted on a multilayer substrate: this represents for the simulations. As starting point we used a Triquint own a quite unusual realization for EHF applications. Two pro- model available in the advance design system simulation tool 2 Active and Passive Electronic Components

Table 1: LNB receiver performances. an apposite S parameters model was created. This model foresees two microstrip lines placed in close proximity of ÷ Input frequency range 202 21.2 GHz the resonator and an apposite block describing the coupling ÷ Output frequency range 90 1950 MHz effects between the dielectric resonator and the microstrip Gain 55 dB lines by using S parameters. Noise figure 1.6 dB The simulation results for this model gives a resonant Gain flatness frequency of 19.250 GHz as expected. Any 500 MHz 3.5 dB To obtain good phase noise performance, the oscillator Any40MHz 1.6dB has been locked to an external reference by using a PLL Spurious emission >60 dBc architecture. The block diagram of the PLL is shown in Phase noise Figure 3. The DRO output is compared with a 10 MHz reference in the main PLL circuit. The external reference @ 1 KHz 78 dBc/Hz signal is first filtered by another PLL circuit (cleaner) used @ 10 KHz 84 dBc/Hz to lock the output signal of a voltage controlled crystal @ 100 KHz 105 dBc/Hz oscillator (VCXO). The charge pump output is used to drive @ 1 MHz 120 dBc/Hz a varactor loaded with a microstrip inside the cavity in which the overall DRO is housed. The loop bandwidth is then optimized according to the phase noise specifications. A microcontroller shown in Figure 3 manages frequency D’ assignment for the two PLLs.

Rd 3. TECHNOLOGY Qgd Rid + − Bare die devices mounted on the traditional hard sub- Y strate (Alumina) are generally used for EHF applications. On the other hand, in very complex circuits for low- Igd Rdb Idb frequency applications multilayer substrates and surface Rg mounted technology are normally used. For the realiza- Ids tion of this PLL DRO oscillator we made the choice of B Cds G’ using a new ceramic multilayer substrate and packaged Igs Cbs surface mounted devices (SMD), now available for high- frequency applications. In this way, all the complex oscillator circuit has been compactly fabricated in a small-size area C employing easy mounting and low-cost materials. The + − multilayer substrate is composed by a ceramic layer (εr = Qgs Ris Rs 9.9), on which the microstrip lines have been realized, and four FR4 (εr = 4.4) layers used for the other intercon- nections. The final compact layout is shown in Figure 4. S’ The dielectric resonator is visible inside the cavity. Even Figure 1: Triquint own model. if at these frequencies distributed DC-blocks are generally used because of their low-insertion losses, in our case a more compact solution employing ceramic capacitances has been adopted. The prototype fabricated is shown in (Figure 1). This model has been improved by adding series Figure 5. The board has been housed inside a metallic inductances and resistances to the three device terminals and structure, closed by a cylindrical metallic waterproof cover other capacitances in order to take into account the parasitic (Figure 5). effects of the package (Figure 2). Modelparametershavebeenevaluatedbyusingthe 4. SIMULATIONS AND MEASUREMENTS information available from the manufacture. A dielectric resonator of high permittivity ceramic material has been The two circuital models have been used in the simulation chosen as resonant element; it is characterized by high of the complete oscillator circuit (Figure 6). Each lumped temperature stability and a dielectric constant ranging and distributed component has been optimized in order between30and40.Inordertoobtainhighvaluesof to reach the required phase noise and output power. The the quality factor (1000–40000), a metallic cover has been computed phase noise and output signal spectrum are shown used. The desired phase noise characteristics are achieved in Figure 7. The phase noise and the output spectrum thanks to the high-impedance path coupling the DRO to measured at the LNB output interface are shown in Figure 8. the other components. In order to simulate the behavior The CW input signal at 20700 MHz has been fed by a of the dielectric resonator within the oscillator circuit, source generator. The measurements exhibit a very good S. Coco et al. 3

C C3 C = Cdg pF

L Port L R Port Lo Ro P1 P2 L2 L = Lo nH Num = 2 R = Ro Ohm Num = 1 L = Ld nH R = 0Ohm R = 0Ohm R R Rd = Rg R Rd Ohm = R Rg Ohm TOM TOM2 L Model = TOMM2 L1 L = Lg nH R Rs1 R = 0Ohm R = Rs Ohm L L3 L = Ls nH R = 0Ohm

C C C1 C2 C = Cpg pF C = Cpd pF Port P3 Num = 3 Figure 2: Improved model taking into account the parasitic effects of the package.

IF out IF RF 10 MHz input filter Mux IF DC input LNA amplifier 10 MHz input DC input

RF Regulator Mux +8 V +5 V 10 MHz DRO Loop PLL Loop filter ADF4001 filter 19250 MHz

Divider/4 PLL ADF4107 TCXO 10 MHz Micro Cleaner

Figure 3: PLL block diagram.

performance both in terms of phase noise and in terms of spectral purity.

5. LNBTESTRESULTS

The PLL DRO described above has been integrated in the low-noise block of the down converter for EHF band satellite communication terminals. The most significant Figure 4: Final compact layout. performances obtained are summarized in Table 1. 4 Active and Passive Electronic Components

Figure 5: The prototype.

VAR VAR4 q0 = 20000 MSub DC VAR q = q0/(k +1) V + MSUB VAR14 = SRC1 teta 0 MLOC − MSub1 = R Vdc = 5V AF 1.79 d = (freq − F0)/F0 TL7 H = 20 mil = − R1 KF 1e 008 = Subst = “MSub1” R = R1ohm Er = 3.48 k 6 = F0 = RFFREQ W = 1.12 mm Mur 1 L = 2.475 mm Cond. = 1E +50 VAR Hu = 5mm VAR1 VAR MLIN T = 20 μm = VAR5 R2 39 TL8 tan = 0 0037 = RFFREQ =19.25 GHz D . R1 120 Subst = “MSub1” Rough = 0mil W = 0.2mm L = 5.335 mm Harmonic balance MLIN MLIN MLOC TL1 TL2 TL4 HarmonicBalance Subst = “MSub1” Subst = “MSub1” Subst = “MSub1” HB1 W = 1.12 mm W = 1.12 mm W = 1.12 mm Freq[1] = RFFREQ = = Model EPB = L 5mm L 5.456 mm L 1.7mm Order[1] = 3 12 X2 AF=AF C KF=KF C1 OSCPort C = 1pF R S2P Eqn R3 Osc1 Vout 2 1 = R = 50 ohm S P V MLIN MLIN = = R S[1, 1] s11 Z 1.1ohm TL6 TL5 = R3 S[1, 2] = s12 NumOctaves 2 = Subst = “MSub1” = = Subst “MSub1” R 50 ohm S[2, 1] = s21 Steps 10 W = 1.12 mm W = 0.2mm S[2, 2] = s22 Fundindex = 1 L = 2.5mm L = 6.6mm = Z[1] = 50 MaxLoopGainStep MLOC = R TL3 Z[2] 50 Subst = “MSub1” R2 = R = R2ohm W 1.12 mm L = 2.7mm

VAR VAR2 s11 = (k/(1 + k +2∗ j∗d∗q))∗ exp(−2∗ j∗teta) s12 = ((1 + 2∗ j∗q∗d)/(1 + k +2∗ j∗q∗d))∗ exp(−2∗ j∗teta) s21 = ((1 + 2∗ j∗q∗d)/(1 + k +2∗ j∗q∗d))∗ exp(−2∗ j∗teta) s22 = (k/(1 + k +2∗ j∗d∗q))∗ exp(−2∗ j∗teta)

Figure 6: The complete oscillator circuit used for simulation. S. Coco et al. 5

0 m1 0 m2 −50 m3 −10

m4 −20 −100 out (dB) pnfm (dBc) −30 −150 V −40

−200 −50 1E21E31E41E51E61E71E8 0 102030405060 Noisefreq (Hz) Frequency (GHz) m2 m1 Noisefreq = 1kHz m2 =−46.71 dBc Frequency = 19.24 GHz m1 =−3.017 m3 Noisefreq = 10 kHz m3 =−76.65 dBc m4 Noisefreq = 100 kHz m4 =−106.1dBc

Figure 7: Simulation results.

10 dB/ Spot FRQ = 10 kHz Atten. 10 dB MKR −60.67 dBm RL −50 dBc/Hz −84 dBc/Hz RL 0 dBm 10 dB/ 1.22 GHz

1 Frequency offset 1 Center 1.45 GHz Span 1 GHz kHz from 1.45 GHz carrier MHz kRBW 30 kHz VBW 30 kHz SWP 2.8s Figure 8: The phase noise and the output spectrum measured at the LNB output interface.

Agilent 11 : 59 : 40 Oct 26, 2007 Frequency

Freq. mode Mkr1 1.7475 GHz 1.202 dB 58.4dB sweep

2 Start freq. 950 MHz 1 NFIG Scale/ Stop freq. 0.2 1.95 GHz dB Center freq. 0 1.45 GHz 60 1 Freq. span Gain 1GHz Scale/ 1 Fixed freq. dB 14.75 GHz

50 More Start 950 MHz BW 4 MHz Points 11 Stop 1.95 GHz 1of2 Tcold 308.28 K Avgs off Att 5/ −−dB Loss on Corr

Figure 9: LNB gain and noise figure. 6 Active and Passive Electronic Components

The phase noise measured is compatible with end-to- end forward performances as recommended in DVB-S2 standard. The LNB noise figure and gain are shown in Figure 9.

6. CONCLUSIONS

In this paper, a state-of-the-art phase locked DRO for an EHF low-noise block down converter is presented. The circuital models, appositely created to describe the behavior of the dielectric resonator and the active component used in the oscillator core, have provided a good methodology in order to speed the design process. The DRO has been used in a low-noise block down converter for EHF band satellite communication terminals. The phase noise obtained makes this LNB receiver particularly suitable for DVB-S2 applications.

REFERENCES

[1] R. G. Rogers, LowPhaseNoiseMicrowaveOscillatorDesign, Artech House, Boston, Mass, USA, 1991. [2] B. Hitch and T. Holden, “Phase locked DRO/CRO for space use,” in Proceedings of the 51st IEEE International Frequency Control Symposium, pp. 1015–1023, Orlando, Fla, USA, May 1997. [3] D. H. Shin, K. K. Ryu, D. P. Chang, M. Q. Lee, and I. B. Yom, “A 26.4 GHz phase locked oscillator for space application,” in Proceedings of the 17th Asia-Pacific Microwave Conference (APMC ’05), vol. 5, p. 4, Suzhou, China, December 2005. [4]W.H.Hayward,Introduction to Frequency Design,The American Radio Relay League, Newington, Conn, USA, 1994. [5] R. W. Rhea, Oscillator Design and Simulation,Noble,Mumbai, India, 1995. [6] U. L. Rohde, Microwave and Synthesizers: Theory and Design, Wiley-Interscience, New York, NY, USA, 1997. [7] E. A. Sweet, MIC & MMIC Amplifier and Oscillator Circuit Design, Artech House, Boston, Mass, USA, 1990. International Journal of

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