Moore's Law: Stephen H

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September 2006 Vol. 20, No. 3 www.ieee.org/sscs-news SSCSSSSCSSSSCCSS IEEE SOLID-STATE CIRCUITS SOCIETY NEWSLETTER

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Editor’s Column

elcome to AdCom at the 2006 ISSCC. the content will be organized into sec- the first The goal of the redesign is to tions, and a table of contents will be Wfull-color enhance membership benefits in provided in each issue. Third, the print edition of the three ways: newsletter will include articles that Solid-State Circuits (1) adding technical content and fea- help members' careers, such as short Society Quarterly ture articles, reports by SSCS Distinguished Lectur- News! Starting with (2) organizing existing content, ers and SSCS pre-doctoral fellowship this issue (September 2006), we will (3) adding articles to help careers of winners, short articles on SSCS Award be mailing a hard copy to all 11,500 members. winners, and reprints of articles with SSCS members. Starting in 2007, First, technical content and feature career advice from the IEEE Profes- SSCS plans to publish four issues of articles will include 2-3 page Research sional Communications Society (PCS). the SSCS newsletter each year, with Highlights from academia, industry, The theme of this issue is “The one each in Winter, Spring, Summer, and government, as well as shorter Technical Impact of Moore’s Law.” and Fall. This newsletter redesign articles on hot topics in circuits and This issue contains two Research was approved by the SSCS Publica- periodic Special Issues on special top- Highlights articles: tions Committee and the SSCS ics of interest to members. Second, (1) “Where CMOS is Going: Trendy Hype vs. Real Technology,” by T. C. Chen at the IBM T. J. Watson IEEE Solid-State Circuits Society AdCom Research Center in Yorktown President: Newsletter Coeditor: Richard C. Jaeger Mary Y. Lanzerotti Heights, NY (USA); Alabama Microelectronics Center IBM T.J. Watson Research Center (2) “Overview of CMOS Technology Auburn University, AL [email protected] [email protected] Fax: +1 914 945 1358 Development in the MIRAI Project” Fax: +1 334 844-1888 by T. Masuhara at the Association of Vice President: Elected AdCom Members at Large Terms to 31 Dec. 06: Super-Advanced Electronics Technolo- Willy Sansen K. U. Leuven Bryan Ackland gies (Japan) and M. Hirose at the Leuven, Belgium Gary Baldwin National Institute of Advanced Indus- Tom Lee Secretary: trial Science & Technology in Japan. David A. Johns Jan Rabaey University of Toronto Jan Van der Spiegel This issue also contains five short Toronto, Ontario, Canada Terms to 31 Dec. 07: feature articles that address the Bill Bidermann Treasurer: theme of the issue. The articles are: Rakesh Kumar David Johns Technology Connexions Terri Fiez (1) “Moore’s Law: The Genius Lives On” Poway, CA Takayasu Sakurai by Patrick Gelsinger at Intel; Mehmet Soyuer Past President: Terms to 31 Dec. 08: (2) “The Mythology of Moore's Law: Stephen H. Lewis University of California Wanda K. Gass Why Such a Widely Misunderstood Davis, CA Ali Hajimiri ‘Law’ is So Captivating to So Many,” Paul J. Hurst Other Representatives: Akira Matsuzawa by Tom Halfhill at Microprocessor Representative to Sensors Council Ian Young Report; Darrin Young Representative from CAS to SSCS Chairs of Standing Committees: (3) “The Impact of Moore’s Law” by Domine Leenaerts Awards David Hodges Robert Keyes at IBM; Representative to CAS from SSCS Chapters Jan Van der Speigel Un-Ku Moon (4) “The Wider Impact of Moore’s Law,” Education CK Ken Yang Newsletter Editor: Meetings Anantha Chandrakasan by David Liddle at U.S. Venture Lewis Terman Membership Bruce Hecht Partners; IBM T. J. Watson Research Center Nominations Stephen H. Lewis (5) “Back to the Future, Part IV: Moore’s [email protected] Publications Bernhard Boser Fax: +1 914 945-4160 Law, The Legend, and the Man,” by For detailed contact information, see the Soci- Gene Meieren at Intel. ety e-News: www.ieee.org/portal/site/sscs We are also reprinting Dr. For questions regarding Society business, contact the SSCS Executive Office. Moore’s original articles on pages Contributions for the Winter 2007 issue of the Newsletter must be received by 33, 36, and 37. 8 November 2006 at the SSCS Executive Office. An Electronic Only Newsletter will be emailed to members in November. Deadline for that notice is 12 October. Thank you for taking the time to read the SSCS newsletter. We appre- Anne O’Neill, Executive Director Katherine Olstein, SSCS Administrator IEEE SSCS IEEE SSCS ciate all of your comments and feed- 445 Hoes Lane 445 Hoes Lane, back! Please send comments to Piscataway, NJ 08854 Piscataway, NJ 08854 [email protected]. Tel: +1 732 981 3400 Tel: +1 732 981 3410 Fax: +1 732 981 3401 Fax: +1 732 981 3401 M. Y. Lanzerotti Email: [email protected] Email: [email protected]

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Photo of Gordon Moore courtesy of Intel Sept 2006 Volume 20, Number 3

Editor’s Column ...... 2

President’s Message ...... 4

Editor’s Message ...... 4

RESEARCH HIGHLIGHTS Where CMOS is Going: Trendy Hype vs. Real Technology ...... 5 Overview of CMOS Technology Development in the MIRAI Project . .9

TECHNICAL LITERATURE Moore’s Law - The Genius Lives On ...... 18 The Mythology of Moore’s Law ...... 21 The Impact of Moore’s Law ...... 25 The Wider Impact of Moore’s Law ...... 28 Back to the Future, Part IV: Moore’s Law, the Legend, and the Man . .30 6 Craming More Components onto Integrated Circuits ...... 33 Progress in Digital Integrated Electronics ...... 36 Lithography and the Future of Moore’s Law ...... 37

PEOPLE Mishra and Popplewell Receive Predoctoral Fellowships for 2006-2007 43 Congratulations New Senior Members ...... 44 Tools: How to Write Readable Reports and Winning Proposals . . .44 SSCS Membership Offers More for 2007 ...... 45 15 CHAPTER NEWS Serbia and Montenegro ED/SSC Chapter Promotes EE as a Career . .46 SSCS Taipei a Key Player in the Asian IC Community ...... 48 SSCS Subsidizes Short Course on Linear Regulator Design in Taipei . .50

CONFERENCES Challenges for the e-life at 2nd A-SSCC ...... 51 Van der Spiegel will Speak at IBERSENSOR 2006 ...... 52 ICCAD 2006 will Focus on Current Applications and Challenges Faced by Future Technologies ...... 52 32 CSIC Symposium Meets in San Antonio, 12-15 November, 2006 . . .53

NEWS Try “Expert Now IEEE” for Free ...... 54

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President's Message

et me add my As I mentioned in the January SSCS-supported conferences con- welcome to Newsletter, the Solid-State Circuits tinue to be a vibrant part of society Lthe new SSCS Society is in good health. Our finan- activities. The recent VLSI Sym- Quarterly News. cial reserves have returned to near posia, held in June in Hawaii, were You will find a sub- their historic peak, and the AdCom highly successful. I encourage you stantial increase in approved the award of new Solid- to participate in one or more of the technical and society State Circuits Fellowships and expan- upcoming SSCS conferences this content, and we hope you will find the sion of both its Distinguished Lectur- fall: ESSCIRC (Montreaux, Switzer- new format and content appealing and er Program and support for Chapter land), CICC (San Jose, CA), BCTM useful. We are extremely fortunate to activities. Two awardees have been (Maastricht, Netherlands), and A- have Mary Lanzerotti as the new co- selected to receive Solid-State Cir- SSCC (Hangzhou, China). I hope to editor. Mary has done a terrific job in cuits Society PreDoctoral Fellow- see you at some of these meetings. developing the enhanced publication ships: Chinmaya Mishra, of Texas Also, please be sure to take advan- and bringing the project to fruition. A&M University in College Station, tage of the Distinguished Lecturer Please send us your comments and Texas and Peter Popplewell of Car- Program to enhance your local suggestions for improving the Quarter- leton University in Ottawa, Canada. I chapter meetings. ly News, as well as for technical topics congratulate our highly deserving that you would find of interest. winners of the latest fellowships. Richard C. Jaeger

Editor’s Message

t is with great exceptional publication. layout very helpful in finding infor- pleasure that I Mary has done a terrific job on mation in the issue. Iwelcome Mary this issue, making major changes in My thanks to the SSCS Officers Lanzerotti as co-edi- style and content. She also over- and Board, which enthusiastically tor of the SSCS saw the shift to a full-color publica- supported this upgrading of the News. We are very tion, which was no mean feat in newsletter. fortunate to have itself. The papers on Moore’s Law I hope you enjoy the new Mary join us. A very experienced give a very interesting range of newsletter and, as always, we wel- newsletter editor, she engineered a views on a law that has been a come your feedback. major upgrading of the LEOS driving icon of the industry. I think newsletter and made it into a truly you will find the new format and Lewis Terman

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RESEARCH HIGHLIGHTS Where CMOS is Going: Trendy Hype vs. Real Technology Tze-Chiang (T.C.) Chen, IBM Fellow, VP of Science and Technology, T.J. Watson Research Center, IBM Research Division

he continuous and systematic increase in tran- insure at least another decade of continued CMOS sistor density and performance, guided by development. TCMOS scaling theory [1] and described in Power dissipation and increasing variability emerge “Moore’s Law” [2], has been a highly successful as first order concerns which must be addressed process for the development of silicon technology for effectively in process development as well as in cir- the past 40 years. As the silicon industry moves into cuit design (Figure 2). How effectively these con- the 45 nm node and beyond, two of the most impor- cerns are addressed depends on how well designers tant challenges facing Moore’s Law and continued and process developers work together. CMOS scaling are the growing standby power dissipation and the increasing variability in device characteristics. These complaints are frequently cited as the reason Moore’s Law is “broken”, or why CMOS scaling is coming to an end. Actually, these effects are the embodiments of approaching atomistic and quantum- mechanical physics boundaries. However, the infu- sion of new materials (Figure 1) and device structures will continue to extend CMOS device performance for a long time to come. Cooperative circuit/technology co-design, and architectures developed concurrently with these new device innovations will provide a comprehensive solution to the challenges of deep Circuit designers and process engineers must work togeth- submicron CMOS. er to address power dissipation and increasing variability concerns.

The history of CMOS development is marked by a series of challenges which have been overcome by ingenuity and hard work. In the first 35 years of process development, MOSFET scaling efforts were focused on extending performance, both by improving device speed as well as integrating more devices and functionality on chip. In the last 5 years, there has been a growing emphasis on managing power consumption. Contributors to the growing power problem include increased device density, device electrical parameter tolerance degradation, rising subthreshold leakage currents, exponential gate tunneling current New materials will continue to extend CMOS device performance. growth, and elevated device temperatures. Delay variation, induced by spatial and temporal process I. INTRODUCTION parameter tolerance, and voltage and temperature CMOS’ approach towards atomistic and quantum- variation profoundly challenges timing precision. The mechanical boundaries has motivated some pundits inability to reduce gate insulator thickness prevents to profile devices based on nanotechnology, bio-elec- further channel length reductions, and leads to this tronics, or quantum computing as urgently-needed crisis in the control of common device phenomena CMOS replacements which must be developed and such as static leakage, short channel effect, and drain- made immediately available for general design use. In voltage-induced barrier lowering. practice, these alternatives need many years for their Inevitably, continued growth of active and static support infrastructure to be developed; they are also power arises from this inability to scale. The process not yet desperately needed. New materials coupled development message to circuit designers is, howev- with effective circuit design and architecture practices er, that help is on the way: the introduction of high-k

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gate dielectrics and metal gates in the near future will 10°C with a typical package, resulting in higher chip reduce gate insulator tunneling by several orders of frequency with improved reliability. Alternatively, if magnitude, and renew device length scaling. Feature the on-chip power density can be decreased by size tolerance issues then become the ultimate limit to 10W/cm2 at constant thermal cooling capability and scaling, presenting profound limitations at the 22 nm constant junction temperature, supply voltage can be node. At roughly 2.5 years per CMOS generation raised back up to the package power limit, to return introduction, high-k innovations will extend CMOS to the same total chip power but with increased chip lifetime by approximately 10 more years. frequency. Finally, reduced power dissipation density As CMOS approaches the 22 nm node, stochastic per device, with constant cooling capability and/or threshold variation caused by dopant implant position reduced voltage, can be traded for more devices on in ultra-small inversion regions will give rise to more the chip. These additional devices can increase paral- than 100 mV of threshold variation. In addition, lelism to recapture performance lost to lower frequen- process proximity effects induced by layout, loading cy from diminished overdrive. A key to making the effects caused by device density, and gate line-edge above scenarios viable is for the designer to advance roughness will bring additional contributions to varia- circuit topologies and processor architectures which tion. At the technology level, over the past 5 years, reduce active power and logical vector activity. Optical Proximity Correction (OPC) and Reticle Enhancement Technologies (RET) have attempted to mitigate these effects, but in the future, closer cooperation between the process engineer, the circuit designer, and the EDA developer will be needed to integrate deeper into the technology what OPC and RET initiated. At the circuit level, emerging issues such as distortion in analog circuits (e.g. phase-locked loops and I/O receivers), and instability and parameter tracking in bi-stable circuits (e.g. latches and SRAM cells) Power maps of fully operational microprocessors obtained require much more active intervention. At the archi- from images of temperature-dependent infra-red (IR) tecture level, initiatives such as self-healing systems, emissions. self-biasing substrates, and simultaneous circuit/device diagnostics will extend the circuit’s ability to survive and function given a wider range of sensitivities. With Dennard scaling, power density ideally remains constant. In practice this is no longer valid, as II. MITIGATING THE CMOS POWER CRISIS gate oxide thickness scaling has slowed. Oxide thick- The chip package’s cooling capability defines the max- ness non-scaling further limits voltage scaling, and imum power dissipation possible in the chip. Die tem- leads to worse short channel effect. This is shown peratures exceeding the package’s cooling capability schematically in Figure 4, which illustrates the effect will cause lower performance, dramatically degraded of increasing gate current (at longer channel length) reliability, and thermal runaway. Although packag- and increasing sub-threshold leakage at short channel ing/cooling technology is being advanced, the need to length. reduce total chip power remains even more urgent. Figure 3 shows detailed power maps of fully operational microprocessors obtained by imaging the temperature-dependent infra-red (IR) emission while the chip is cooled by a custom designed IR transparent heat sink [3]. Measurements of the thermal distribution of a fully operational IBM microprocessor during boot- up of an operating system (2 GHz, Vdd=1.4 V, average power 50 W/cm2) revealed local peaks, or “hot spots”, far exceeding 100 W/cm2. Chip temperatures for all processors can exceed 70oC for selected hot spots, even using state of the art packaging and cooling methods, impacting performance and reliability. If on-chip power density can be decreased by 10W/cm2 Gate oxide thickness scaling has slowed due to increasing at constant thermal cooling capability and constant gate current, at longer channel length, and sub-threshold supply voltage, junction temperatures will decrease by leakage, at short channel length.

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Figure 5 shows the reduction in the inversion thick- ment enabled VLSI integration, ultimately delivering ness (Tinv) and the silicon dioxide leakage equivalent much more performance than that lost by MOSFETs. thickness (ToxGL) from the 130nm to 45nm nodes. Now once again, our industry is called upon to reduce The Tinv thickness is scaled as the Lpoly decreases in power dramatically. A dramatic efficiency improvement each successive node. Inversion thickness scaling is can be realized by operating at reduced Vdd. It is iron- achieved by either reducing the physical thickness or ic to note that, just as with CMOS’ replacement of HBTs, increasing the dielectric constant. As the gate a lower performance / lower power technology ulti- dielectrics are thinned, the corresponding gate tun- mately will deliver superior system throughput because neling increases exponentially. As the dielectric film of the higher integration it enables. Blue Gene-L, the has scaled from Tinv of 23 Angstroms to 17 world’s fastest supercomputer, uses processors running Angstroms the gate leakage has increased from at 700 MHz - substantially slower and cooler than high approximately 1A/cm2 to several hundred A/cm2. In performance 2-3GHz workstation uniprocessors. With the latest technology node, deviation from continued reduced power, heat-sensitive 3D chip technologies may inversion thickness scaling to avoid this tunneling is enable even higher integration. The quadratic power noteworthy; unanswered, it will result in loss of gate dependence on voltage identifies reduced Vdd as being channel control. The lack of scaling in the 65nm node the best driver to introduce 3D integration. is driven primarily by excessive gate leakage and reliability. Figure 5 shows future Tinv and gate leakage reduction exhibited by high-k and metal gates. The introduction of these materials allows our industry to continue electrical thickness scaling. Going back to Figure 4, high-k dielectrics return CMOS static power to that of classic scaling by mitigating the tunneling current, and by improving channel control. The lower capacitance of shorter channels enabled by better short channel control (resulting from lower effective oxide thickness or “EOT”) and lower Vdd reduce active power as well.

In the transition from heterojunction bipolar transistors ("HBT's") to MOSFETs, performance dropped 3X and power dropped 10X -- an order-of-magnitude improvement that enabled VLSI integration. III. VARIABILITY Chip variability influences yield and overall chip-level performance. This is especially critical given the trend towards multiple microprocessor cores. Variability manifests itself in a multitude of processes and can be global (chip to chip, wafer to wafer, etc.) or local Inversion thickness and silicon dioxide leakage equivalent (inherent to the circuit instance), see Figure 7. thickness decline in 130nm - 45nm nodes. The second means of addressing power consumption is to reduce operating voltage [4]. Supply voltage reduction quadratically mitigates active as well as static power. Further, reducing Vdd significantly reduces gate insulator tunneling for a fixed dielectric thickness. But because overdrive has become precious in deep submicron CMOS, operating at reduced voltages requires adding complexity in supply distribution and modulation. Performance in the new CMOS, however, must be measured in total system throughput rather than in GHz. Our industry learned in the transition from heterojunction bipolar transistors (“HBTs”) to MOSFETs that although performance dropped 3X, power dropped 10X Chip variability, which can be local or global, influences as shown in Figure 6. This order-of-magnitude improve- yield and overall chip-level performance.

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Advanced process controls (APC) (i.e. run-by- run control, fault detection and classification) can effectively address chip-to-chip, wafer-to-wafer and lot-to-lot mean variations by minimizing global variation. Regional systematic variations across the wafer and across the chip are typically corrected by process modifications. ACLV, for example, can be partially corrected by judiciously adjusting the exposure dose across the wafer during the step-and-scan wafer exposure. Regional yet non- systematic in-chip variation cannot be addressed by APC, process design or process modification; it requires a far more advanced solution. In the future, self-correcting, autonomic circuits will be required to address this type of variability. These Examples of restricted design rules for optimizing layout circuits rely upon on-chip monitors to continuous- robustness from the lithography perspective. ly test function and performance, self-correcting by turning on and off peripheral circuits to adapt. IV. ENHANCING DEVICE PERFORMANCE Local in-chip variations resulting from processing The International Roadmap for Semiconductor (ITRS) pattern density effects require process design mod- projects that MOSFETs with equivalent oxide thick- ifications. Examples include optical proximity cor- ness of 5A and junction depths less than 10nm will be rection (OPC) in advanced lithography to minimize in production in the next decade [6]. While 6nm gate across-chip linewidth variation (ACLV). Other lengths MOSFETs have been demonstrated [7], per- examples include the addition of pattern fill in formance and manufacturability challenges remain. CMP to improve BEOL copper planarization and High-k/metal gates to mitigating gate leakage, alter- STI divot reduction. Thermally-induced variation native doping techniques for shallower more abrupt during rapid-annealing is the more recent of these junctions, and alternative device structures will likely effects and can be mitigated through the thin film be needed for sub-30nm devices. design. Highly localized in-chip variations due to Although ever more challenging to increase CMOS the fundamental, underlying physics or chemistry device performance, innovative CMOS device design- of some processes cannot be resolved by the ers continue to be successful. A number of tech- aforementioned techniques. niques have enhanced CMOS device performance The three major challenges in dealing with random appreciably. These include strain-induced mobility variability are characterization, reduction, and accom- enhancement, using silicon in unusual crystal orienta- modation. Design can play a vital role in addressing tions, and creating novel device structures, to improve all three. the electrostatics of the devices. The challenge to the Local variations in layout often lead to significant circuit design community is to develop circuits and variations in device parameters through their architectures which deliver high throughput comput- impact on lithography, etch, CMP, and local stress. ing at low power. The process development commu- To reduce variability, future generations of technol- nity will provide materials and solutions such as high- ogy will require an increased focus of design for k dielectrics, three-dimensional chips, and stable low manufacturing (DFM). DFM can optimize layout voltage MOSFETs to enable new design points. robustness against both random and systematic Equipped with these opportunities, future product process yield detractors [5]. DFM from the lithogra- design points will continue to move the state of the phy perspective is the means by which design lay- art forward into yet more astonishing capabilities. outs respect specific restrictions so that they robust- This article is based on the Keynote address given ly print. Examples of such restricted design rules at ISSCC in February 2006. (RDRs), illustrated in Figure 8, include (a) the avoidance of lithographically forbidden pitches; (b) References single orientation of narrow gates; (c) restrictions [1] R. Dennard et al., “Design of Ion-Implanted on the number of linewidths that are allowed, and MOSFET’s with Very Small Physical Dimensions,” (d) placement of narrow features on a quantized IEEE J. Solid-State Circuits, vol. SC-8, pp. 256- grid so that a uniform proximity environment is 268, 1974. attained. RDRs can also afford reduced CD variation [2] G. E. Moore, “Cramming more components on to such as across chip or field linewidth variation integrated circuits”, Electronics, Vol. 38, no. 8, (ACLV, AFLV) that can manifest in device perform- April 19, 1965; “Progress in digital integrated ance variation. electronics”, IEDM Tech Dig. pp.11-13, 1975.

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[3] H.F. Hamann et al., “Spatially resolved imaging Research and Development Center, IBM Microelec- of microprocessor power”, ISSCC Dig.Tech. tronics Division in East Fishkill, New York. During the Papers, p.16, Feb. 2005. period of 1992-1999, he was the Senior Manager [4] J. Cai et al., “Supply voltage strategies for mini- responsible for the 64Mb/256Mb/1Gb DRAM Tech- mizing the power of CMOS processors”, Symp. nology Development in IBM/Siemens/Toshiba DRAM VLSI Tech. p.102, 2002. Development Alliance. Before assuming his role as [5] L. Liebmann et al., “Integrating DfM components the Project Manager in DRAM Development, he held into a cohesive design-to-silicon solution”, in a variety of managerial assignments in his career at Design and Process Integration for Microelec- IBM, including Functional Manager of High-Perfor- tronic Manufacturing III, ed. L.W. Liebmann, mance BiCMOS Technology, Manufacturing Engineer- Proc. SPIE 5756, pp 1-12 (2005) ing Manager in the Bipolar VLSI Line, and Manager of [6] www.itrs.net/Links/2005ITRS/Home2005.htm Optical Lithography Development at Watson Research [7] B. Doris et al., “Extreme scaling with ultra-thin Si Center. channel MOSFETs,” IEDM Tech Dig. pp. 267-270, Dr. Chen received his Ph.D. Degree in Electrical 2002. Engineering from Yale University in 1985. He has published more than 60 papers in technical journals About the Author and conferences. His contributions to advanced bipo- Dr. Tze-chiang (T.C.) Chen joined lar technology had a major impact on IBM S/390 the IBM Thomas J. Watson Research mainframe systems. More recently, his contributions Center, Yorktown Heights, New York to CMOS miniaturization and DRAM devices have had in 1984. He is currently an IBM Fel- a profound impact on IBM?s leadership in CMOS low and the Vice President of Sci- process technology and DRAM manufacturing. Dr. ence and Technology at Thomas J. Chen was elected as a Fellow Member of the Institute Watson Research Center, IBM of Electrical and Electronics Engineers (IEEE) in 1998. Research Division in Yorktown Heights, New York. Dr.Chen has been recognized with several IBM Tech- During the period of Feb. 1999 - Feb. 2003, Dr. nical Innovation Awards and was named IBM Distin- Chen was the Director of Advanced Logic/Memory guished Engineer and IBM Fellow in 1996 and 1999, Technology Development at the Semiconductor respectively.

Overview of CMOS Technology Development in the MIRAI Project Toshiaki Masuhara, MIRAI, [email protected] and Masataka Hirose, MIRAI

Introduction (iv) Interconnect module technology with low-k As the transistor size and the interconnect pitch in materials CMOS integrated circuits are scaled-down, various (v) Lithography related metrology and inspection technology barriers limiting the performance and technology manufacturability are emerging. MIRAI (Millennium In 2006, the Project was reorganized for the 3rd Research for Advanced Information Technology) Pro- Phase (2006-2010) by completing the 2nd phase mis- ject started in 2001 to challenge these barriers, with sion and transferring most of the developed technolo- Dr. Masataka Hirose as Project Leader. The Project is gies to member companies and Semiconductor Lead- funded by the New Energy and Industrial Technology ing Edge Technologies (Selete). This overview briefly Development Organization. summarizes the 1st and 2nd Phase achievements of The purpose of the Project was to provide technol- the MIRAI Project. The organization and operation of ogy solutions for the half-pitch 65nm technology node the 3rd Phase will also be briefly explained. in the 1st Phase (2001-2003), and half-pitch 45nm and beyond in the 2nd Phase (2004-2007). Five research Scope of the MIRAI Project topics were chosen for this purpose: In the 1st and 2nd phases of the MIRAI Project, a vir- (i) Post-fabrication adaptive adjustment circuit tech- tually-single research organization was formed that nology consists of expert researchers from industry, the ii) Gate stack technology with high-k gate National Institute of Advanced Industrial Science and dielectrics Technology (AIST), and academia. Industry (iii) New transistor structure and measurement tech- researchers from semiconductor device, material and nology equipment companies were assigned to the MIRAI

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Project, with the strong intention of applying the R&D results to their own products. The original results of the development are managed to be transferred to industry with the intellectual property right (IPR). The priority of the Project has been, therefore, promoting synergy among researchers with different back- grounds, not only for proposing new ideas and concepts but also for creating IPR.Various kinds of cooperative work between MIRAI and industry or consor- tia have been arranged for the purpose of enhancing opportunities for technology transfer. (a) New Circuits and System Technology - Programmable Delay Circuit Post-fabrication Adaptive Adjustment In CMOS integrated circuits for45nm and beyond, Inverter Flip- Flip- Flip- Flip- ALU variations of the device parameters such as the thresh- flops X 5 flops X 4 flops X flops X 9 flops X flops X 9 flops X

Decoder old voltage Vth, the on-current ION of the transistors and the parasitic capacitances and resistances of the interconnect give rise to significant degradation of the voltage margin, the timing margin and the standby Clock power. These cause practical limitations in the scaling Input Delay Delay Delay Delay Setting Setting Setting Setting of CMOS integrated circuits. Circuits and design technology capable of adjusting multiple parameters in the circuits to optimal values in a very short time after (b) fabrication were developed. The technique consists of specifically designed adjustment circuits and software 100 based on a genetic algorithm (GA). A key application 90.0% example is the clock delay adjustment in high-speed, 80 low-power digital circuits. This is done, first by insert- 䌲 60 ing multiple adjustable delay circuits in the clock Before䌲 After paths at the design stage, and then by automatically 40 Adjustment Adjustment trimming the delay time after chip fabrication. Figure 1 shows an example of the application of the new 20 15.0% adjustment technique for a memory test pattern gen- 1 Operating yield (%) 0 erator circuit . It is seen that operating yield increased 1 1.2 1.4 1.6 1.8 from 15% to 90% after adjustment at 1.4GHz. If the Clock frequency [GHz] adjustment was optimized for maximum clock speed, (c) 25% clock speed increase was realized at the design Fig. 1. Clock timing adjustment by genetic algorithm. Delay clock frequency of 1GHz. If the adjustment was opti- values were adaptively adjusted after the fabrication by mized for low power, the power decreased to 54% of software based on Genetic Algorithm. If the adjustment the original value. A practical level MCU and a signal was optimized for maximum clock speed, 25% increase processor were designed using the technique and 䌲 was realized. If the adjustment was optimized for low performance evaluation is under way. power, the power decreased to 54% of the original value for medium scale memory test pattern generator TEG1. (a) Photomicrograph of the 130nm CMOS TEG. Another example is the optimization of the pre- (b) Circuit for the memory test pattern generator TEG. emphasis of the waveform in high speed signal trans- (c) Operating yield of the memory test pattern generator mission. The pre-emphasis adjustment for the output TEG before and after adjustment. buffer circuits is shown in Figure 22. In this case, pre- emphasized signal wave form was generated in the Project through the Association of Super-Advanced output buffer circuit by tuning parameters V1, V2 and Electronics Technologies (ASET), collaborating with Tp digitally so that the optimal wave forms were members from AIST and more than 10 university lab- observed at the signal receiving point. The adjustment oratories. In the MIRAI Project, the scientific approach was done by a post-fabrication adjustment algorithm. has been particularly emphasized, rather than the The eye pattern at a signal receiving point on a print- empirical approach for overcoming difficult chal- ed-circuit board (PCB) 140 cm away from the signal lenges. Research topics were basically proposed by sending point exhibited a bit-error-rate of below 10-14 the member companies in the planning stage of the at 2GHz data transfer

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(a)

Vo Tp V2 Transmission Line V1 0.4V Transmission Line 500ps 140 cm on PCB (c) (b) Fig. 2. 2.0GHz reconfigurable LSI (FPGA) for Galois field calculation and the post-fabrication pre-emphasis technique2. (a) Photomicrograph of the LSI fabricated by 130 nm CMOS technology. (b) Pre-emphasized signal wave form at the output buffer circuit. Parameters can be adjusted by the post-fabrication adjustment algorithm. (c) Eye pattern at a signal receiving point, 70 cm away from the chip on PCB. A bit error rate below 10-14 is observed.

A parameter extraction tool for the HiSIM MOSFET the leakage current. High dielectric constant (high-k) model was also developed by using genetic algorithm materials with the excellent mobility, threshold volt- adjustment3. The HiSIM model has been developed age controllability and reliability comparable to the by the joint work of Prof. Michiko Miura, Hiroshima conventional oxides must be developed. University and STARC (Semiconductor Technology In the MIRAI Project, the high-k dielectrics with Academic Research Center). The extraction of 34 equivalent gate oxide thickness of less than1.2 nm major model parameters in HiSIM was achieved and metal gate suitable for standard CMOS process through collaboration between Prof. Miura and integration were developed for 45 nmtechnology. MIRAI. Since HiSIM is a surface-potential based HfAlON was chosen as the gate dielectric, and HfO2 model, precise extraction of device parameters is nec- was also studied as a reference. MIRAI developed the essary. Therefore, automatic extraction is essentially Layer-by-Layer Deposition and Annealing (LL-D&A) important in the HiSIM model. As shown in Figure 3, process, where annealing is done at the intermediate the developed tool successfully extracted the 34 step of the atomic layer deposition to reduce the car- model parameters in 23 hours with a PC and resulted bon contamination4. HfAlON gate dielectrics deposit- in a mean RMS error of 1.83% for Compact Modeling ed by LL-D&A showed excellent leakage current char- Council (CMC) benchmark MOSFETs. acteristics as shown in Figure 45. Electron mobility as high as 235 cm2/Vs at 0.8MV/cm is obtained for New Gate Stack Technology with High-k EOT=1.1-1.2 nm for the HfAlON gate stack, and 255 Materials cm2/Vs at 0.8MV/cm was also obtained for n-MOS- MOSFET scaling requires thinner gate dielectrics. FETs (EOT=1.1 nm) with HfO2 dielectric. Commonly used gate dielectrics, such as silicon diox- MOSFETs with high-k gate dielectrics often suffer ide or oxy-nitride have excellent interface characteris- from so-called Fermi-level pinning at the high-k/poly- tics, and hence exhibit good electrical properties and Si or fully-silicided (FUSI) gate interface. The Fermi- reliability. However, it is known that the gate leakage level pinning induces a significant shift of the thresh- current due to tunneling exceeds 103A/cm2 in silicon old voltage particularly for pMOSFETs with p+poly dioxide with thicknesses below 1 nm. Therefore, the gate. Threshold voltage tuning technology by control- gate dielectrics must be replaced by a physically ling the energy level due to Fermi-level pinning was thicker but electrically thinner material to minimize developed, as shown in Figure 5 (a), where Al con-

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HiSIM Model Measured Extracted by Trained Engineer Lg/Wg=100nm/ /2um Vgs=1.0V VBS= 0V (Arb) Vgs=0.9V 5 ds

Mean By Trained Engineer Vgs=0.8V

Vgs=0.7V

RMS Error (%) Mean By GA Vgs=0.6V Vgs=0.5V

Drain Current I Extracted By GA 0 0.2 0.4 0.6 0.8 1 0 0 1.0 2.0 Drain Voltage Vds (V) Gate Length (Pm) (a) (b)

Fig. 3. Parameter extraction for HiSIM MOSFET model using genetic algorithm3. (a) Comparison of Ids-Vds curve for an MOSFET. Measured data were provided by STARC. (b) RMS error of the extracted parameters. Mean RMS error was 1.83%. For GA that is smaller than that by a trained engineer.

centration in the HfAlON layer was changed6. The HfOxN as shown in Figure 5 (b)7. symmetric Vth values for n- and p-MOSFETs were obtained at about 25 at. % of Al in HfAlON for poly- New Transistor Structures and Measurement Si gate MOSFETs, as shown in the figure. For the Technology FUSI-NiSi gate, similar symmetric Vth values were New MOSFET structures having higher carrier mobili- obtained at 7.5 at. % of Al in HfAlON. ty have been developed for the purpose of compen- The other Vth control was achieved by employing sating ION reduction in scaled CMOS transistors. partial silicide (PASI) gate electrode technology, in Locally-strained MOSFETs have become widely used which the Fermi-level pinning effect was relaxed by in CMOS where stress is applied by SiN liner on the reducing the Si atom content in the silicide PtSix on transistors or SiGe source-drain junctions. In MIRAI, ) 2 102 SiO2

1 Gate

10-2 EOT HfAlON Interface Layer -4 10 MIRAI (HfAlON) Si 10-6 HfAlON HfSiON Gate Leakage Current (A/cm 10-8 0.5 1.0 1.5 2.0 2.5 3.0

Equivalent Oxide Thickness EOT (nm) (a) (b)

Fig. 4. Gate leakage current in MIRAI HfAlON formed by Layer-by-Layer Deposition and Annealing (LL-D&A)4. (a) Comparison of gate leakage current in MOSFETs with HfAlON gate insulator and HfSiON5. (b) Cross sectional TEM micrograph of HfAlON/SiO2/Si gate stack formed by Layer-by-Layer Deposition and Annealing.

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Fig. 5. Technology for effective work function control. (a) Effective work function control by changing aluminum concentration in HfAlON6. (b) Effective work function control by partial silicide gate electrode for p-MOSFET7.

high quality silicon-germanium-on-Insulator (SGOI) stant (k) as low as 2.0 was developed for the 45 nm substrate technologies have been developed. In the node and beyond11. Figure 7 (a) shows the developed developed techniques, thermal oxidation of SiGe with Cu damascene interconnect with periodic porous-sili- low Ge content results in the selective oxidation of Si, ca12. One of the major problems of porous low-k and Ge condensation occurs in the remaining SiGe material is the mechanical strength compared to that layer. The epitaxial silicon layer formed on the SiGe of conventional inter-metal dielectrics. Mechanical layer has controlled strain, as illustrated in Figure 6 reinforcement of porous silica was achieved by (a), and exhibits higher mobility. employing tetramethyl-cyclo-tetra-siloxane- 5 - In strained SOI MOSFETs, however, the mobility (TMCTS) gas anneal after formation of the low-k enhancement for a p-MOSFET is smaller than that of an dielectrics. The TMCTS gas molecules penetrate into n-MOSFET, mainly due to the quantum confinement pores and cover micro-defects of the pore wall sur- effect in the inversion layer. If rectangular SiGe mesa is face to effectively enhance the mechanical strength. formed on the SGOI substrate, the strain along the The Young’s modulus of the porous silica wall EW was shorter edge is relaxed and residual strain toward the improved by the TMCTS gas anneal from approxi- direction of the longer edge becomes uniaxial as mately EW=10-23 GPa to EW=40 GPa, as shown in Fig- shown in Figure 6 (c). In the fabricated SGOI p-MOS- ure 7 (b)13. It was also demonstrated that the TMCTS FET on the uniaxially strained SGOI shown in Figure 6 gas anneal recovers the process-induced damages (e), a significant mobility enhancement was observed such as dry etching, ashing, Cu electroplating and 8 for the narrower Wg, as shown in Figure 6 (f) . CMP. The measured interline capacitance shown in If Ge condensation is further performed, a Ge-on- Figure 7 (c) indicates that the effective dielectric con- insulator (GOI) substrate is realized. A surface chan- stant was kept unchanged regardless of the line & nel p-MOSFET on a GOI substrate was fabricated for space of the interconnect14. The leakage current level the first time. The hole mobility improvement factor and interconnect resistance distribution, as well as of 3.1 as compared to the universal hole mobility of TDDB lifetime12, were also satisfactory for the fabri- Si, was obtained9. In MIRAI, Schottky barrier height cated single damascene Cu interconnect structure control technology for optimally designing the source using porous silica with k=2.1. and the drain junction in SGOI or GOI MOSFETs has Several characterization techniques for low-k mate- also been developed10. rials were also developed. These include a reliable Metrology tools with high spatial-resolutions for nano-indentation technique for Young’s modulus dopants, junction potential and localized stress have measurements, accurate adhesion measurements by been developed based on original ideas in MIRAI. four point bending, determination of thermal expansion coefficients of low-k materials by spectroscopic Interconnect Module Technology with Low- ellipsometry, and nondestructive measurements of k Materials elastic constants of thin film multilayers by surface Scalable low-k porous-silica having the dielectric con- acoustic wave (SAW).

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RESEARCH HIGHLIGHTS

Fig. 6. Fabrication of uniaxially strained SGOI (SiGe On Insulator) pMOSFETs and their mobility enhancement8. (a) Strained Si layer on SiGe with controlled strain made by Ge condensation technique. (b) Strained SiGe layer with controlled strain made by Ge condensation technique. (c) Top view of SiGe layer with narrow mesa with uniaxial residual strain. (d) Top view of SiGe layer with wide mesa. (e) Cross-section of uniaxially strained SGOI p-MOSFET. (f) Drain-current enhancement in uniaxially strained SGOI p-MOSFETs. Uniaxially strained SGOI p-MOSFET structure shows 1.8 times higher mobility than that of SOIp-MOSFET for narrow Wg.

Lithography Related Metrology and Conclusion and Future Scope of the MIRAI Inspection Technology Project An atomic force microscope (AFM) tool, able to observe This paper has described selected achievements of ultra fine patterns and their sidewalls, was developed. the MIRAI Project in its 1st and the 2nd Phases. As The technology consists of novel AFM techniques based already noted, the MIRAI Project was reorganized in on tilt-step-in mode operation of a probe tip and a dig- 2006. The 3rd Phase of MIRAI will continue from 2006 ital scanning proving mode operation. With these tech- to 2010, with intermediate evaluation scheduled in niques, sidewall images were successfully obtained and 2007. In the 3rd Phase, Semiconductor Leading Edge line-edge-roughness was clearly measured, as shown in Technologies (Selete), AIST and ASET have joined the Figure 815. A high precision Atomic Force Microscope Project. The mission of the 3rd Phase of MIRAI is to (AFM) with modularized laser interferometers was also provide possible technical solutions for ultrascaled developed. The CD measurement with a precision of CMOS, nano-silicon integration and EUV lithography. 0.3 nm was demonstrated by improving the perform- The Project's 3rd Phase is lead by Dr. Hisatsune ance of the 3-axes scanner and the wafer stage16. These Watanabe as Project Leader, and Dr. Masataka Hirose techniques can be applied to high precision CD and as the Chief Science & Technology Officer. edge-roughness measurements that are of special importance for developing the physical model on vari- Acknowledgements ations of CMOS characteristics. The Project is supported by the New Energy and We have developed several other inspection tech- Industrial Technology Development Organization nologies related to lithography. For mask inspection, (NEDO). The authors wish to thank the Group Lead- a DUV CW laser light source at 199 nm, a TDI (Time ers of MIRAI 1st and 2nd Phases, Prof. AkiraToriumi, Delay and Integration) image sensor, and concurrent Prof. Takamaro Kikkawa, Prof. Shinichi Takagi, Dr. detection optics using transmitted and reflected Tsuneo Terasawa and Dr. Tetsuya Higuchi and Board images were developed. A patterned wafer inspection Members, Dr. Toshihiko Kanayama and Mr. Seiichiro tool using the DUV light was also developed. Kawamura.

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Porous Silica Ta/TaN SiOC Cu Cu

100nm SiN (a) 12 99.99 a a 99.9 P P G G Pa 10 0 0 99 7 4 G = = 23 w w = E w 95 E E Pa 90 8 7 G =1 80 E w 70 50 Line/Space (Pm) 6 Pa =10 G 30 Ew 20 0.16/0.14 0.16/0.16 4 10 5 0.16/0.18 0.16/0.20 Young's Modulus (GPa) 1 0.16/0.30 2 Reinforcement of the EW Cumulative Probability (%) 0.16/0.80 by TMCTS Anneal .1 0.16/1.00 .01 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 2 46810 12 14 Dielectric Constant Capacitance (x10-12F) (b) (c)

Fig. 7. Porous-silica Low-k material technology for interconnect12, 13,14. (a) Cross-section of fabricated Cu-damascene interconnect with porous silica Low-k inter-dielectrics. (b) Mechanical strength reinforcement by TMCTS (Tetra-Methyl-Cyclo-Tetra-Siloxane) gas anneal. (c) Distributions of the interline capacitance in the fabricated Cu damascene interconnect.

Fig. 8. Three dimensional image of the pattern sidewall measured using atomic force microscope15. The pattern is Low-k intermetal dielectrics with ArF resist on top with a height of 400nm and a pitch of 400 nm. (a) Sidewall measured by conventional vertical scanning method (b) Sidewall measured by tilted step-in operation.

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References technique”, in Symp. VLSI Tech. Dig., 2005, pp. 1) E. Takahashi, Y. Kasai, M. Murakawa and T. 178-179. Higuchi, “A post-silicon timing adjustment using 9) S. Nakaharai, T. Tezuka, E. Toyoda, N. Hirashita, genetic algorithms”, in Symp.VLSI Circuits Dig., Y. Moriyama, T. Maeda, T. Numata, N.Sugiyama 2003, pp. 13-16. and S. Takagi, “Hole mobility in fully-depleted 2) N. Endo, Y. Kasai, M. Iwata, E. Takahashi and germanium-on-insulator pMOSFET with 32-nm- T. Higuchi, “Galois field computation LSI: are thick Ge channel layer formed by Ge condensa- configurable chip for high-speed communication technique”, in Ext. Abst. Int. Conf. Solid tion”, in Symp.VLSI Circuits Dig., 2005, State Devices Mater., 2005, pp. 868-869. pp.208-211. 10) K. Ikeda, Y. Yamashita, N. Taoka, N. Sugiyama 3) M. Murakawa, M. Miura-Mattausch and T. and T. Takagi, ”Modulation of NiGe/GeSchottky Higuchi, “Towards automatic parameter extrac- barrier height by dopant and sulfur segregation tion for surface-potential-based MOSFET models during Ni germanidation for metalS/D Ge MOS- with the Genetic Algorithm”, Proc. 2005 Asia FETs, in Ext. Abst. Int. Conf. Solid State Devices South Pacific Design Automation Conference Mater., 2005, pp. 544-545. (ASP-DAC), 2005, pp.204-207.Also M. Miura and 11) T. Kikkawa, S. Chikaki, R. Yagi, M. Shimoyama, M. Murakawa, “Automatic parameter extraction Y. Shishida, N. Fujii, K. Kohmura,H. Tanaka, T. of HiSIM MOS transistor model parameters by Nakayama, S. Hishiya, T. Ono, T. Yamanishi, A. GA”, in Ext. Abst. MIRAI Project Annual Meeting, Ishikawa, H. Matsuo,Y. Seino, N. Hata, T. Oct.2005, pp. 30-39. Yoshino, S. Takada, J. Kawahara, and K. 4) T. Nabatame, K. Iwamoto, H. Ota, K. Tominaga, Kinoshita, "Advanced scalable ultralow-k/Cu H. Hiramatsu, T. Yasuda, K. Yamamoto, interconnect technology for 32 nm CMOS ULSI W.Mizubayashi, Y. Morita, N. Yasuda, M. Ohno, using self-assembled porous silica and self- T. Horikawa and A. Toriumi, “Design and proof aligned CoWP barrier", in IEDM Tech. of high quality HfAlOx film formation for Dig.,2005, pp. 92 - 95. MOSCAPs and nMOSFETs through Layer-by- 12) Y. Oku, K. Yamada, T. Goto, Y. Seino, A. layer deposition and annealing process”, in Ishikawa, T. Ogata, K. Kohmura, N. Fujii, N.Hata, Symp. VLSI Tech. Dig., 2003, pp.25-26. R. Ichikawa, T. Yoshino, C. Negoro, A. Nakano, 5) A. Toriumi, K. Iwamoto, H. Ota, M. Kadoshima, Y. Sonoda, S. Takada, H.Miyoshi, S. Oike, H. W. Mizubayashi, T. Nabatame, A. Ogawa,K. Tanaka, H. Matsuo, K. Kinoshita, and T. Tominaga, T. Horikawa and H. Satake, “Advan- Kikkawa, "Novel self-assembled ultra-low-k tages of HfAlON gate dielectric film for- 7 - porous silica films with high mechanical strength advanced low power CMOS application“, Micro- for 45nm BEOL technology", in IEDM Tech. Dig., electronic Engineering, Elsevier, 80, 2005,pp. 2003, pp. 116-119. 190-197.Also A. Toriumi “High-k gate stack tech- 13) R. Yagi, S. Chikaki, M. Shimoyama, T. Yoshino, nology”, in Ext. Abst. MIRAI Project Annual T. Ono, A. Ishikawa, N. Fujii, N. Hata, Meeting, Oct. 2005, pp. 69-89. T.Nakayama, K. Kohmura, H. Tanaka, T. Goto, 6) M. Kadoshima, A. Ogawa, M. Takahashi, H. Ota, J. Kawahara, Y. Sonoda, H. Matsuo, Y. Seino, K. N. Mise, K. Iwamoto, S. Migita, H.Fujiwara, H. Kinoshita and T. Kikkawa, ”Control of process- Satake, T. Nabatame and A. Toriumi, ”Fermi level induced damages in self-assembled- 8 -porous pinning engineering by Al compositional modu- silica/Cu damascene interconnects for 45nm lation and doped partial silicide for HfAlOx(N) node and beyond”, in Symp. VLSI Tech Dig., CMOSFETs”, in Symp.VLSI Tech. Dig., 2005, pp. 2005, pp. 146-147. 70-73. 14) S. Chikaki, M. Shimoyama, R. Yagi, T. Ono, A. 7) T. Nabatame, M. Kadoshima, K. Iwamoto, N. Ishikawa, N. Fujii, N. Hata, T. Nakayama, K. Mise, S. Migita, M. Ohno, H. Ota, N. Yasuda,A. Kohmura, H. Tanaka, T. Goto, J. Kawahara, Y. Ogawa, K. Tominaga, H. Satake and A. Toriu- Sonoda, H. Matsuo, Y. Seino, S. Takada, mi, “Partial silicides technology for tunable- N.Kunimi, Y. Uchida, S. Hishiya, Y. Shishida, K. work function electrodes on high-k gate Kinoshita and T. Kikkawa, ”Hybrid Low-k/Cu dielectrics-Fermi level pinning controlled PtSix dual dual damascene process for 45-32nm tech- forHfOx(N) pMOSFET”, in IEDM Tech. Dig., nology node using self-assembled porous silica 2004, pp.83-86. ultra Low-k films,” Proc. IEEE IITC, 2005, 8) T. Irisawa, T. Numata, T. Tezuka, K. Usuda, N. pp.48-50. Hirashita, N. Sugiyama, E. Toyoda and S.Takagi, 15) K. Murayama, S. Gonda, H. Koyanagi and T. “High current drive uniaxially-strained SGOI Terasawa, “Three-dimensional metrology for pMOSFETs fabricated by lateral strain relaxation sidewall measurement using tilt-scanning opera-

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tion in digital probing AFM”, Proc. of development of NMOS circuits and high-speed SPIE,Vol.6152, 615216-8, 2006, pp. 615216-1- CMOS memories”. He was the program co-chair 615216-8. and the chair in 1992-, 1993-, and general co-chair 16) S. Gonda, K. Kinoshita, H. Noguchi, T. Kurosawa, and chair in 1996- and 1997-VLSI Circuit Sympo- H. Koyanagi, K. Murayama andT. Terasawa, sium. He was an elected member of the Adminis- “AFM measurement of linewidth with sub- trative Committee, SSCS from 1998 to 2000.He nanometer scale precision,” Proc. of SPIE, Vol. received IEEE Solid-State Circuit Technical Field 5752, 2005, pp.156-162. Award on his contribution to NMOS depletion- load circuits and the development of high speed About the Authors CMOS memories in 1990 and the IEEE third Mil- Toshiaki Masuhara (S768-M’69- lennium Medal in 2000. He has received a Signif- SM’90-Fellow’94), Association of icant Invention Award, Japan in 1994, four Signif- Super-Advanced Electronics Tech- icant Invention Awards, Tokyo, Japan in 1984, nologies (ASET), was born on Mar. 1985, 1988 and 1992, Significant Invention 5, 1945 in Osaka, Japan. He Awards, Yamanashi, Japan in 1995 and Gumma, obtained B.S., M.S. and Ph.D. Japan in 1996. degrees in Electrical Engineering from Kyoto University, Kyoto, Japan in 1967, 1969 Masataka Hirose, MIRAI, Advanced and in 1977, respectively. From 1969 to 1974, he Semiconductor Research Center was a member of the technical staff, 3rd and 7th (ASRC), National Institute of Department at Hitachi Central Research Laborato- Advanced Industrial Science and ry(CRL), Kokubunji, Tokyo, Japan, where he Technology (AIST) was born in worked on depletion-load NMOS integrated circuits Gifu, Japan on September 30, 1939. and on modeling of sub-threshold characteristics of He received the B.S. and M.S. MOS transistors. From 1974 to 1975, he was a spe- degrees in electronic engineering from Nagoya Uni- cial student, Department of Electrical Engineering versity, Nagoya, Japan in 1963 and 196, respectively, and Computer Science, University of California, and the Ph.D. degree in electronic engineering from Berkeley where he worked on double-diffused Tohoku University, Sendai, Japan in 1975. From 1963 MOS transistors and a new CMOS process. In 1975, to 1964, he worked in the Central Research Labora- he returned to Hitachi CRL and worked on new tory, Fuji Electric Co., Ltd. From 1970 to 2001, he was high speed CMOS SRAM. In 1987, he became with the Department of Electrical Engineering in department manager, 7th Dept., Hitachi CRL, devel- Hiroshima University, Higashi-Hiroshima, Japan and oping memories, microprocessors, digital signal was a Professor from 1982 to 2001. His research inter- processors and high frequency silicon devices. He ests include ULSI devices and processes and silicon then became the manager of the 1st Dept. in 1990, quantum nanodevices. From 1986 to 1996, he was performing research on high speed GaAs and bipo- Director of Research Center for Integrated Systems, lar ICs and materials. From 1991 to 1993, he was in Hiroshima University. From 1996 to 2001, he was Telecommunications Division, Hitachi, where he Director of Research Center for Nanodevices and Sys- was responsible for the design of telecom ICs.He tems, Hiroshima University. became General Manager, Technology Develop- Since 2001, he has been Director General, ment Operation (Center) in 1993, General Manager, Advanced Semiconductor Research Center, National Semiconductor Manufacturing Technology Center, Institute of Advanced Industrial Science and Technol- Semiconductor & IC Div. in 1997, and then became ogy, Tsukuba, Japan. From 2001 to 2005, he was Pro- Senior Chief Engineer, Semiconductor Group, ject Leader of MIRAI, and from 2006 he is Chief Sci- Hitachi. In 2001, he assumed his current position, ence & Technology Officer of MIRAI. Executive Director, MIRAI Project, Association of Dr. Hirose is a member of the IEEE, the Japan Super-Advanced Electronics Technologies Society of Applied Physics, and the Institute of Elec- (ASET).He is a member of IEEE and IEICE, Japan. tronics, Information and Communication Engi- He became a fellow of IEEE in 1994 with the cita- neers(IEICE) of Japan. He became a fellow of IEICE, tion, ”For contribution in the invention and the Japan in 2002.

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TECHNICAL LITERATURE Moore’s Law - The Genius Lives On

Pat Gelsinger, Senior Vice President Digital Enterprise Group, Intel, [email protected]

o truly understand the genius behind Gordon TMoore and his famous “Moore’s Law,” you have to remember what the semiconductor industry was like in the mid-1960s when Gordon wrote his famous article in the April 1965 edition of Electronics Magazine. At that time, the industry was capable of integrating only tens of transistors on a single silicon die, and Gordon was projecting the integration of only “65,000 components on a single silicon chip.” Even with that relatively small number, pundits thought his predictions were bold and probably optimistic. The industry has gradually trans- overcome. Now, let’s take a walk on an early microprocessor to formed from those early successes through the four decades since bring compute power into the with tens of transistors to greater Gordon Moore made his wonder- home. It didn’t match the perform- than a billion transistors on a sin- ful prediction. ance of large mainframe comput- gle microprocessor today. When With Moore’s Law in its infancy, ers of the day but it certainly Professor Carver Mead from the the 1970s was the era of invention. opened the door for the revolution California Institute of Technology No one was quite sure what to do that would grip the world in the named Gordon’s prediction with the new abundance of tran- next decade. Engineers had little “Moore’s Law,” he wasn’t referring sistors and so they were used idea at the time that integrated sys- to a law of physics but rather a dis- everywhere: integrated static mem- tems technology would later cipline for the electronics industry ory, dynamic memory, microcon- replace discrete systems. So, one to follow. Later, Robert Dennard1 trollers, and microprocessors to has to ask why was integration so developed scaling theory showing name a few. Innovations were desirable? Really, three fundamen- how Moore’s Law can be realized everywhere, and the sky was the tal factors emerged as driving in practice. Simply put, the rest has limit. Fabrication facilities were rel- forces for integration; namely, inte- been history. The industry has atively inexpensive, allowing grated systems 1) provide better dutifully followed Moore’s Law for Moore’s Law to march on unabat- cost/performance; 2) they take less more than four decades, with no ed as integration capacity rose space; and 3) they are more reli- end in sight. To be sure, the road from tens of transistors to thou- able. And so fulfillment of Moore’s has not always been easy. Chal- sands. Wafer sizes doubled from Law was the ticket to realize these lenges such as yield, design pro- two inches at the start of the benefits. ductivity, lithographic scaling, and decade to four inches in diameter If the 1970s was the era of power dissipation all seemed by 1976. Microprocessor frequen- invention, then the 1980s was the insurmountable in their own time, cies rose from hundreds of kHz in era of scaling and manufacturing but one by one were overcome the early days to tens of MHz later science that made the realization through hard work and persever- in the decade. These were still of Moore’s Law viable and afford- ance. There will surely be more slow compared to discrete logic able. With the success of integrat- challenges to come including in- but they provided the foundation ing thousands of transistors, it die variations, power efficiency, for the general-purpose program- soon became clear that achieving and reliability. But again with hard mable microprocessor that would the integration of millions of tran- work, cooperation throughout aca- dominate the industry in the com- sistors on a single die was within demia and the industry, and vigi- ing decades. Apple introduced the reach. With this level of integra- lant perseverance these too will be first truly personal computer based tion, VLSI was born, providing

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TECHNICAL LITERATURE

both lucrative opportunities and integration rose from a million power limits imposed in each plat- unprecedented performance at transistors in the early 1990s to form segment. For example, cell remarkably low costs. Incremental close to 50 million by the end of phones continue to increase in increases in the fundamental wafer the decade. Silicon wafers function, now capable of email, sizes became instrumental in real- increased to eight inches in diame- music, and video. Laptops are izing significant cost reductions. ter, carried hundreds of micro- ubiquitous in the workplace but Four inch wafers gave way to six processor die, and were manufac- face higher and higher consumer inch wafers in high volume manu- tured in high volumes, making for demands for performance and bat- facturing during this decade. The extraordinary cost reductions. tery life. High-density data centers three big challenges of yields, Advances in CAD and manufactur- such as those created by Google design complexity, and power dis- ing science allowed the industry to are exploding as the world’s data sipation began to emerge during design and produce complex chips store grows exponentially. These this time. In response, a whole in very high volume. Innovative network data centers are increas- new era of manufacturing science manufacturing and design tech- ingly challenged by power deliv- arose to tackle the yield problem. niques, such as redundancy in ery and thermal constraints. To Through the use of statistical con- memory, helped improve yields to increase performance linearly, trols and discipline it became pos- exceptional levels. Perhaps the processors must dissipate power sible to manufacture VLSI compo- most stunning achievement of the quadratically, which is unfortu- nents cost-effectively in very high 1990s was the increase in perform- nately a poor trade-off between volumes. The advent of CAD ance realized in everyday plat- power and energy. In the last two (Computer-Aided Design) and new forms. The quest to deliver higher years, a new paradigm has arisen technologies such as logic synthe- and higher performance fueled an that we call “multi-everywhere,” sis made it possible for small num- exponential growth in frequencies referring to the multiplication of bers of designers to construct these from 25 MHz to more than 1 GHz, functions at every level of the plat- complex designs. Unfortunately, with a corresponding tenfold form, from multiple logic blocks power was quickly becoming an increase in power. In the 1980s, on a chip to multithreading to chip issue. The underlying process the transition from NMOS to CMOS level multiprocessing. Through the technology was NMOS, with was a temporary fix for the prob- increase of thread counts and pro- CMOS on the horizon. CMOS was lem that increasing power present- cessing cores, we’re able to deliv- known to consume less power but ed. Unfortunately, no such savior ering near-linear performance was used for very low power was in sight in the 1990s. Instead, gains with only modest increases applications such as watches and aggressive voltage scaling was in frequency while staying within was considered an underperformer employed to allow these high-per- required power levels. Today, we in applications such as micro- formance microprocessors to fit see the dawn of this “multi-every- processor designs. Nevertheless, into the common desktop, laptop, where” era with dual-core and the drive to realize Moore’s Law and server form factors. As volt- quad-core mainstream processors. continued, and CMOS was the ages scaled so did the transistor In the coming years, you will see technology brought to bear on the threshold voltages, enabling higher core counts increase greatly to the power problem. High-performance frequencies, and hence subthresh- point of possibly hundreds of CMOS designs began to emerge old leakage started increasing at an cores on a single processor allow- and quickly replaced NMOS as the alarming rate. By the end of the ing us to achieve Tera-Scale com- technology of choice. As a result, decade, this leakage power was a puting on a single processor die. the power consumed by these substantial component of the total We see no end to Moore’s Law devices decreased substantially design power. in the coming decade. As before, from tens of watts to just a few As we enter the 21st century, challenges are abundant. However, watts while the frequency rose to Moore’s Law continues unabated, as was true over the last 40 years, tens of MHz. with billions of transistors per chip there are large numbers of brilliant By the early 1980s, Gordon’s and wafers reaching 12 inches in scientists and engineers ready to prediction had two decades under diameter. But the industry has tackle these challenges. Looking its belt, with no end in sight. But shifted its focus to providing ener- ahead, ever-decreasing transistor what followed in the 1990s sur- gy-efficient performance across all geometries will lead to a significant prised even the most optimistic platforms. The challenge is to increase in cross-die variability. industry leaders. The last decade exploit the transistor integration Electric fields in transistors will of the 20th century is most appro- capacity provided by Moore’s Law, continue to increase, threatening priately labeled the era of manu- deliver higher and higher perform- reliability and the useful lifetime of facturing and speed. Transistor ance, and yet stay within the the transistors. But there will be

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billions of them at our disposal. 3. www.intel.com/pressroom/ designs next-generation hardware Besides new features and kits/quickreffam.htm#i486 and software technologies for all increased core counts, we will 4. Intel Moore's Law web site: Intel Architecture platforms for need to find new ways to utilize www.intel.com/technolo- business and consumer market these large numbers of transistors gy/magazine/silicon/moores- segments. to circumvent ever-increasing relia- law-0405.htm Previously, Gelsinger led the bility and variability concerns. At Desktop Products Group, where the same time, with such an abun- About the Author he was responsible for Intel's desk- dance of transistors, we can envi- top processors, chipsets and moth- sion a complete platform integrat- erboards for consumer and com- ed on a single chip featuring hun- mercial OEM customers as well as dreds of cores, special-purpose Intel's desktop technology initia- hardware, and memory. Such tives and the Intel Developer processors will need to include Forum. From 1992 to 1996, new architectural, micro-architec- Gelsinger was instrumental in tural, and circuit techniques that defining and delivering the Intel® will provide for built-in resiliency. ProShare® video conferencing and Gordon Moore’s simple predic- Internet communications product tion has been a guiding principle line. Prior to 1992, he was general for an electronics industry that has manager of the division responsi- far surpassed anything anyone ble for the Pentium® Pro, could have dreamed of in 1965. In IntelDX2™ and Intel486™ micro- each decade since, there have processor families. Other positions been challenges, creative solu- Gelsinger has held during his Intel tions, and more challenges. Today, career include director of the Plat- those challenges include reliability, form Architecture Group, design variability, and power, and they manager and chief architect of the appear daunting. However, history original i48619™ microprocessor, has proven time and again that the Pat Gelsinger is senior vice presi- manager of CAD methodologies, realization of Moore’s Law drives dent and general manager of Intel and key contributor on the original us to new levels of innovation. Corporation's Digital Enterprise i386™ and i286 chip design teams. Will it ever come to end? No one Group. Gelsinger holds six patents and can know, but for the foreseeable Gelsinger joined Intel in 1979, six applications in the areas of future, Moore’s Law appears both and has more than 26 years of VLSI design, computer architecture intact and as prophetic as the day experience in general management and communications. He has more it was first penned. and product development posi- than 20 publications in these tech- tions. Gelsinger led Intel's Corpo- nical fields, including "Program- References rate Technology Group, which ming the 80386," published in 1987 1. Dennard, R.H.; Gaensslen, encompasses many Intel research by Sybex Inc. He has received F.H.; Yu, Hua-Nien; Rideout, activities, including leading Intel numerous Intel and industry V.L.; Bassous, E.; LeBlanc, Labs and Intel Research, and driv- recognition awards, and his pro- A.R.; IBM T.J. Watson ing industry alignment with these motion to group vice president at Research Center, Yorktown technologies and initiatives. As age 32 made him the youngest Heights, NY, USA, "Design of CTO, he coordinated with Intel's vice president in the history of the ion-implanted MOSFETs with longer-term research efforts and company. very small physical dimen- helped ensure consistency from Gelsinger received an associ- sions," Vol.SC-9, No.5, pp. Intel's emerging computing, net- ate's degree from Lincoln Techni- 256-68, Oct. 1974. working and communications cal Institute in 1979, a bachelor's 2. S. Borkar, “Designing Reliable products and technologies. degree from Santa Clara Universi- Systems from Unreliable Before his appointment as the ty in 1983, Magna Cum Laude, Components: The Challenges company's first CTO, Gelsinger and a master's degree from Stan- of Transistor Variability and was the chief technology officer of ford University in 1985. All Degradation,” IEEE Micro, vol the Intel Architecture Group. In degrees are in electrical engineer- 25, no 6, Nov-Dec 2005, this position, he led the organiza- ing. Gelsinger is married and the pp.10-16. tion that researches, develops and father of four children.

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TECHNICAL LITERATURE The Mythology of Moore’s Law

Why Such a Widely Misunderstood ‘Law’ Is So Captivating to So Many

Tom R. Halfhill, Senior Analyst, Microprocessor Report, [email protected]

oore’s law gets more Moore’s law is a narrow observa- computers,” which in 1965 were attention all the time. tion of a general manufacturing still in the realm of science fiction. MUsing Google to search trend, not a law of physics; it was- Reading the article will be a reve- for the term on the Internet finds n’t clearly defined in the first place; lation for those who enjoy 1.8 million hits—up from 223,000 its definition has been significantly offhandedly quoting Moore’s law, in 2004. That’s remarkable for changed over the years, both by its because nowhere in the text does something that describes the author and by trespassers, to make Moore explicitly state the law. In arcane art of semiconductor chip it better fit the actual data; and past fact, the word “law” never appears manufacturing. People who can’t performance is no guarantee of in the article. The term “Moore’s tell a silicon wafer from a compact future results. law” was coined years later by disc don’t hesitate to name-drop Understand that I’m not attack- Carver Mead, a professor at the Moore’s law at business lunches ing Moore’s law itself or its author, California Institute of Technology and parties, usually in the context Intel co-founder Dr. Gordon E. (Caltech). The closest Moore of whether Intel stock is a good Moore. My purpose is to counter comes to expounding the law in buy. Not since a falling apple led the growing misconceptions about his 1965 article is within a three- Sir Isaac Newton to discover uni- an interesting observation that, paragraph section under the sub- versal gravitation have so many since 1965, has acquired a strange heading “Costs and Curves.” people been so captivated by a sci- life of its own. Indeed, I believe In that section, Moore discusses entific law. there’s something romantic about the component counts of integrat- Yet Moore’s law isn’t really a law Moore’s law that has propelled it ed circuits manufactured at the in the formal sense, and it isn’t sci- into popular mythology. most economical point on the entific. Indeed, it barely works for semiconductor cost curve. In 1965, its intended purpose: describing The Origin of Moore’s Law he notes, the most economical the progress of component inte- One thing about Moore’s law chips integrate about 50 compo- gration on affordable silicon chips. everyone agrees on: it dates back to nents. By 1970, he speculates, the But that doesn’t stop news the April 19, 1965, issue of Elec- most economical chips will have reporters, commentators, analysts, tronics magazine, in which Gordon about 1,000 components. And by and almost anybody with a calcu- Moore wrote an article entitled 1975, he predicts, the most eco- lator from applying Moore’s law to “Cramming More Components nomical chips will contain about things as disparate as microproces- Onto Integrated Circuits.” At the 65,000 components. Moore comes sor clock frequency, microproces- time, Moore was director of closest to actually stating the law sor power consumption, general Fairchild Semiconductor’s Research when he writes, “The complexity computer-system performance, and Development Laboratories. for minimum component costs has disk storage capacity, network Only four years earlier, Fairchild increased at a rate of roughly a fac- bandwidth, digital camera resolu- and Texas Instruments had intro- tor of two per year.” His graph is tion, or—in the most egregious duced the first commercially avail- the now-classic log-base-two plot, example I’ve seen—the business able planar integrated circuits. And showing component counts dou- fortunes of Netscape, a software three years after publishing his bling every 12 months. company. Four years ago, the landmark article, Moore helped In retrospect, it’s possible to widespread and growing misappli- found Intel. Moore defined his law extrapolate Moore’s law from that cation of Moore’s law prompted at a crucial moment in the semi- single sentence and graph, but it's me to define Moron’s law: “The conductor industry. definitely not the succinct version number of ignorant references to Moore’s 1965 article is widely of the law popularly quoted today. Moore’s law doubles every 12 available on the Internet, such as After the article appeared, it months.” Intel’s website. It’s only three and remained for others to dissect Now that we have finished cele- a half pages long, with two hand- Moore’s careful engineering lan- brating the 40th anniversary of drawn graphs, a picture of Moore, guage and boil down his observa- Moore’s law, it’s time to set the and an artist’s cartoon of a future tion into a more concise statement: record straight. The facts are these: salesman hawking “handy home “The number of transistors on a sil-

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a law of physics, it cannot be held to strict accountability. It’s not like Newton’s law of gravitation, which identifies a universal constant. It’s more like Bode’s law, an observation by early astronomers that each planet in our solar system is roughly twice as far from the sun as the planet in the next inner orbit. Mod- ern astronomers don’t expect the distances between planets to add up exactly, and they don’t expect other solar systems to conform to the same rule.

The Evolution of Moore’s Law Since 1965, Moore’s law has been revised twice in its most common form—once by its author, and again by others who keep strug- Figure 1. Last year, on the 40th anniversary of Moore’s law, Intel used this chart gling to make it fit the data. In to illustrate the law’s progress. But the chart actually tracks the progress of transistor integration for Intel’s microprocessors—from the 4004 in 1971 to the 1975, at an IEEE meeting, Moore Itanium-2 in 2005—not the progress of integration predicted by the law. amended his law, which by that time had already become famous icon chip doubles every 12 the text. His second forecast over- within the semiconductor industry. months.” shot his mathematical projection Moore stretched the period for That rewrite is certainly more by 27%. doubling components from the concise, but it’s also less precise. Like the divorce between com- original 12 months to a more con- To begin with, it severs the rela- ponent counts and costs, these servative 24 months. This signifi- tionship between component inconsistencies also started a trend. cant modification reflected the counts and component costs. Since 1965, the relatively few peo- slower progress of integration as Moore was observing a trend in ple who have tried reconciling the engineers encountered new manu- component counts for the most forecasts of Moore’s law with actu- facturing challenges, which are economical integrated circuits, al data have found the task frus- most definitely governed by the which is quite different from trating—which is why the law has laws of physics. describing the maximum number been restated in at least three dif- When progress accelerated again of components it’s possible to ferent ways. There’s something so a few years later, Moore’s law cram on a chip at any given time. fascinating about Moore’s law that required additional tinkering to Early on, there began a trend of people want to make it work, maintain it as a reasonably accurate simplifying and generalizing whether it really works or not. description of reality. Moore didn’t Moore’s law. Soon, it began slip- Even Intel plays the game. An seem interested in continuing to ping out of Moore’s control and Intel PowerPoint presentation on bend the law, so other people entering the public domain. the 40th anniversary of Moore’s jumped in. They resorted to a Moore added to the confusion, law contained the chart in Figure sophisticated mathematical method because the numbers in his article 1, which actually shows the known as “splitting the difference.” don’t add up. Starting from a base- progress of Intel’s microproces- After looking at the original 12- line of 50 components in 1965, if sors, not the progress predicted by month period for doubling compo- the component count doubles the law. nent counts and comparing it with every 12 months, a chip manufac- Of course, Moore wasn’t defin- Moore’s revised 24-month period, tured in 1970 should have 1,600 ing a scientific “law” to be taken they settled on a compromise of 18 components, not 1,000 compo- literally. Other people saddled his months. Since then, the 18-month nents as Moore predicted in his casual observation with that bur- period has become a widely quoted text. His first forecast fell short of den. Moore was merely pointing version of Moore’s law, perhaps the his own mathematical projection out a four-year trend and speculat- most quoted version, even though by 38%. Likewise, by 1975, a chip ing where it might lead in the five- Moore had nothing to do with it. should have 51,200 components, to ten-year future. Because The unauthorized redefinition of not the 65,000 Moore predicted in Moore’s law is an observation, not Moore’s law provided more flexi-

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bility for those who enjoy using Number of Transistors the law to prove their points, (Baseline 1965, Predicted for 2006) (Actual in 2006) whatever those points may be. Moore's Law 109.9 trillion — With three time intervals to choose (2x in 12 Months) from—12, 18, and 24 months— Moore's Law 8.4 billion — people who knew a little more (2x in 18 Months) about arithmetic than about semi- Moore's Law 74.1 million — conductor manufacturing could (2x in 24 Months) pick the interval that best Intel Pentium D — 230 million described their actual data or (Dual Cores) desired forecast. Given the nearly Intel Itanium-2 — 1.72 billion ubiquitous use of this technique, (Montecito) it’s a wonder Microsoft hasn’t built the various permutations of Table 1. Three different versions of Moore’s law predict very different results over the past 41 years. Moore’s original 1965 law observed that component Moore’s law into Excel as prede- integration doubles every 12 months, but that curve was too aggressive to fined functions—along with remain valid for long. Moore’s revised 1975 law extended the doubling period macros to automatically generate to 24 months, which has turned out to be the most accurate curve. The widely hockey-stick graphs. quoted, but unofficial, 18-month version of the law is significantly off base, Another source of confusion is though it’s better than the original 12-month version. whether the “components” Moore chips, not the biggest chips it’s processor in 2006 should have 74.1 refers to in his 1965 article are syn- possible to build. Intel’s newest million transistors. And there cer- onymous with “transistors.” Today, Itanium-2 server processor, code- tainly are economical processors nearly everyone assumes Moore named Montecito, has only 1.7 bil- with approximately that many tran- was discussing the scale of transis- lion transistors, and it will proba- sistors, especially for embedded tor integration. Even Intel meas- bly cost $4,000. applications. Current-model desk- ures the progress of Moore’s law In addition to falling well short top PC processors are somewhat by this benchmark. However, of Moore’s original 1965 predic- larger—Intel’s dual-core Pentium Moore’s 1965 article refers to the tion, today’s microprocessors are D has 230 million transistors. In larger-scale integration of resistors cheating on Moore’s law, some contrast, the 18-month split-the- and diodes as well as transistors, critics argue. On average, 40% to difference curve predicts a vastly so he’s using “components” in a 60% of the transistors in PC proces- overoptimistic 8.4 billion transis- generic sense. This broader defini- sors are devoted to memory in the tors in 2006. (On a log-base-two tion makes it even more difficult to form of on-chip caches, not to curve, small differences add up track the accuracy of the law. workhorse logic. In fact, some of quickly.) Table 1 shows the differ- Transistor counts for chips are rel- today’s largest CPUs seem like ent predictions of the three ver- atively easy to come by, but counts memory chips with integrated sions of Moore’s law and the actu- of passive components are not. processors, not processors with al transistor counts of two micro- integrated memory. (Intel’s Mon- processors in 2006. Measuring the Accuracy of tecito has 24MB of on-chip Level-3 Still more confusion ensues Moore’s Law cache.) But remember, Moore’s when people try to link Moore’s If transistor counts are the accept- law doesn’t even distinguish law with Intel’s manufacturing ed benchmark, the original law is a between transistors and passive schedule. Intel’s aggressive goal is wildly inaccurate predictor. Start- components, much less between to introduce a new chip-fabrica- ing from a baseline of 50 transis- logic transistors and memory tran- tion process every two years. If it tors in 1965 and assuming Moore’s sistors. Besides, larger caches are a was 0.13 micron in 2001, then it original doubling period of 12 perfectly legitimate way to must be 90nm in 2003, 65nm in months, an economical micro- improve performance. 2005, 45nm in 2007, 32nm in 2009, processor in 2006 should have In fairness to Moore, he didn’t and so on. Surely, note some nearly 110 trillion transistors. expect his curve to remain accu- observers, it can’t be a coinci- That’s ridiculously more transistors rate beyond 1975 or so. That’s why dence that this two-year cycle than are found in a current Intel he later revised the doubling peri- exactly matches the interval of one Pentium D desktop-PC processor od to 24 months. His revision of the three versions of Moore’s (230 million). Indeed, the 1965 law pushes the curve back toward real- law—and that the company com- is unworkable even if we ignore— ity. Starting from a baseline of 50 mitted to the schedule is Intel, as Intel does in Figure 1—that transistors in 1965, the 24-month which was co-founded by the Moore was describing economical curve predicts that an economical author of the law!

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As a result, some people are tain is we’re 41 years closer to the useful to know. Dave Epstein, a reverting to Moore’s 1975 defini- end of Moore’s law than we were longtime member of the Micro- tion, which pegged the doubling when it was formulated. We still processor Report editorial board, interval at 24 months. But just don’t know the distance to what I has proposed a solution he mod- because Intel is rolling out a new call Moore’s wall (the reverse of estly calls Epstein’s amendment: fabrication process every two years Moore’s law). “Starting in 1970 with the predicted doesn’t mean the transistors on its Reading doom into the reluc- doubling every 12 months, the chips are doubling at the same tance of Intel and other companies interval will increase by six months pace. Moore’s law doesn’t address to make far-out predictions isn’t every ten years.” the ability of CPU architects to very useful, either. It’s perfectly In other words, assume that in effectively use the expanding tran- understandable that they can’t 1970, Moore’s law was still chug- sistor budgets that the law predicts. anticipate what their engineers are ging along at a rate of 2x every 12 capable of doing much beyond months. By 1980, it slowed to 2x The Greatly Exaggerated eight or ten years in the future. It’s every 18 months. By 1990, it was Death of Moore’s Law always been that way. We’ll have 2x every 24 months; by 2000, 2x The latest trend isn’t to modify to wait and see. every 30 months. Epstein’s amend- Moore’s law but to pronounce it The third reason for declaring ment adds a leveling factor that dead. This is a particularly popular the death of Moore’s law—the accounts for the law of diminishing theme in the mainstream press, slowing pace of clock-speed infla- returns. Although his factor doesn’t and even in the trade press. Refer- tion and the growing problem of quite fit the actual data, some jug- ences to the imminent demise of power consumption—forgets that gling with a spreadsheet should the law have been doubling the law describes component inte- whip it into shape. Maybe the roughly every 12 months. gration, not clock frequency, interval is increasing by six months There are at least three reasons dynamic power, or static current every eight years or eight months for these ominous predictions of leakage. There’s every reason to every six years. I’ll leave this prob- impending doom. First, the indus- believe that future processors will lem as an exercise for the obses- try has been coasting on the coat- continue integrating more transis- sive reader. tails of Moore’s law for more than tors than today’s processors do, 40 years, and there’s growing even if their clock speeds don’t The Popularity of Moore’s Law uneasiness that the carnival ride is climb at the heretofore feverish As we passed the 40th anniversary about to end. Second, companies pace. And there’s every reason to of Moore’s law in 2005, it was like Intel decline to predict what believe we’ll continue finding better amazing to see how a cost-compo- their engineers will be able to ways to control power consump- nent curve plotted in 1965 to achieve more than eight or ten tion, which doesn’t necessarily describe semiconductor manufac- years in the future, which some scale at the same rate as the poten- turing has so thoroughly penetrat- people misinterpret as an expira- tial for component integration. ed popular culture. Moore’s law tion date for the law. Third, Intel’s In microprocessor design, what isn’t just for engineers any more. recent retreat from higher clock matters is throughput, not clock References keep appearing in frequencies for its x86 processors speed. Multicore processors have more and more places, with and the worsening problem of proved that chip multiprocessing is increasing ambiguity, sort of like power consumption have led as valid for improving perform- crop circles in wheat fields. And, some people to mistakenly con- ance as caffeinating the clock fre- as with those wacky crop circles, clude that Moore’s law is almost quency is. Multicore designs are everyone is eager to offer a per- ready to take its place in history just another way of leveraging sonal interpretation. Today, alongside the Code of Hammurabi. higher-scale integration—and Moore’s law, in all its bastardized Fear mongering isn’t wholly to remember, higher integration is the forms, belongs to everyone. blame for this rising dread of point of Moore’s law. I believe Moore’s law has chipocalypse. Indeed, the first rea- The greatest shortcoming of entered popular mythology son for anticipating the end of Moore’s law is that it doesn’t because it’s so compelling. Who Moore’s law is the least hyperven- acknowledge another informal can resist a 41-year-old prediction tilated: the law can’t last forever. edict: the law of diminishing that practically promises chips will Duh! Otherwise, silicon chips returns. Moore’s law is an infinite get better on a regular schedule, as would eventually have more tran- log-base-two curve without a if by clockwork? To a great extent, sistors than there are grains of shoulder, so it never reaches the the law is self-fulfilling, because it sand with which to make them. inevitable plateau. More important, gives manufacturing engineers (or But heck, we’ve known that since it doesn’t suggest how close we at least their whip-cracking man- 1965. Today, all we know for cer- are to the plateau, which would be agers) a target to aim at. We land-

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ed a man on the moon before 1970 Perhaps the most attractive because we said we would. We attribute of Moore’s law, then, is its double the transistors on a chip time-tested optimism. At least every 24 months because we say something in the world is getting we will. Nothing motivates like a twice as good at regular intervals deadline. brief enough to perceive within our No other mathematical curve lifetimes. The hope inherent in captures the popular imagination Moore’s law could be the best the way Moore’s law does. It explanation for all the clumsy shoots skyward like a rocket, year attempts to apply the law to things after year. Population-growth having nothing to do with compo- curves are impressively steep, too, nent integration on chips of silicon. but their endpoints are frightening to contemplate. The zigzag charts For More Information of economists and accountants are Dr. Gordon E. Moore’s original unreliable predictors of the future 1965 article in Electronics maga- and have too many sharp spikes to zine is available on Intel’s website: be user friendly. The gentle bell download.intel.com/research/sili- About the Author curves of psychologists and social con/moorespaper.pdf Tom R. Halfhill is a senior analyst scientists are as reliable as Moore’s Intel offers a great deal of addi- at In-Stat’s Microprocessor Report. law, but they’re often depressing, tional information about Moore’s He has been covering the com- because they usually describe law: puter industry since 1982 and has unfair distributions of the human www.intel.com/technology/mo worked for BYTE Magazine and condition. oreslaw/index.htm several other publications.

The Impact of Moore’s Law Robert W. Keyes, IBM Thomas J. Watson Research Center, Yorktown NY [email protected]

he silicon integrated circuit Moore went beyond simply defined the number of compo- was invented in 1960. The observing the steady growth in nents on a chip as the number that Tintegrated circuit offered component count to attribute minimized the manufacturing cost manufacturers an opportunity to increases in chip content to specif- per component; reducing the cost drastically reduce costs by handling ic characteristics of manufacturing of devices continues to motivate and interconnecting many compo- technology.2 Larger chips appar- the pursuit of increased integra- nents simultaneously rather than ently permit more components on tion. The manufacture of integrat- one by one. The new technology a chip, as does making the com- ed circuits today processes large was quickly adopted and only five ponents on a chip of given size wafers that contain hundreds of years later Gordon Moore of Intel smaller. Components are made chips, each of which contains mil- announced that the number of smaller both by miniaturization, lions of devices. The cost of pro- components placed on a silicon ship decreasing the size of everything, cessing a wafer is divided among had approximately doubled each and by a factor that Moore dubbed billions of the devices. The chip year1. Moore's observation became a "cleverness," essentially more com- size is limited by the fact that the well-known description of progress pact device designs. Cleverness larger the chip, the greater the in integrated electronics, and four can be quantified as the number of probability that it contains a decades later the advance of inte- pixels or smallest resolvable spots defect. Increases in the size of the gration persists, although at a slow- that are used to make a compo- wafers that are processed to create er pace. The long-continued growth nent on a silicon surface. Clever- chips and transistors have been of the number of transistors on sili- ness has reduced the number of another contributor to the long- con chips, by a factor of one million pixels per bit of memory to only term decrease in the cost of com- since Moore's brief note, is unparal- six and it is hard to picture a more ponents. Besides low cost, integra- leled in the history of industrial tech- compact memory cell. tion also provides the very high nology and has earned fame as Cost was at the heart of Moore’s reliability that is needed in systems “Moore's Law.” original observation in 1965, which of many millions of devices.

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The invention of the micro- ogy into contemporary culture by tronics has led to an enormous processor and the demonstration making a host of new applications expansion of the role of computa- of a thousand-bit memory that affordable. tion in science and engineering. could replace magnetic core mem- Everyday encounters illustrate Simulations of all sorts of physical ory in 1970 were convincing evi- the broad impact of integrated structures and of interactions dence that the future of electronic electronics. The electronic wrist between myriads of entities have information handling lay in putting watch followed the development spawned whole new fields of sci- the largest possible number of of compact circuitry that could ence, witness journals Computa- components on a chip. The count down from megacycle elec- tional Physics and IEEE Computa- development of CMOS circuitry, by tronic oscillators to the time scales tional Biology and Bioinformatics. greatly reducing the power used of liquid crystal displays and Fourteen IEEE publications contain by digital circuits, eased the way to mechanical components, substan- the letter sequence “Compute” in increased integration. In spite of tially improving the accuracy and their titles. Daily newspapers have the escalating cost of facilities that convenience of timekeeping. made numerical modeling of could manufacture chips with Replacement of cash by credit earth’s climate known to everyone. smaller features on larger wafers, cards is feasible because of the Electronic tools that can simulate newer facilities continue to yield existence of electronics that rapid- structures in great detail and pro- ample reward in the form of value ly authorizes transactions. The vide fast access to large reposito- of product produced. personal computer and the inter- ries of information have given new Increased integration and net have enabled widespread and powers to engineering design. reduced cost made larger and quick access to vast quantities of Computers design the next genera- faster machines that could handle information and a new mode of tion of computers themselves and larger and more complex problems person to person communication, play a role in their manufacture, as available. Larger problems and made even more convenient in the design of lenses for photoli- larger machines needed more and through the development of the thography. Large databases that more memory to hold information. notebook computer. Lightweight can be rapidly accessed by elec- Increasing integration as dictated portable music permits simultane- tronic means have led to wide- by Moore's Law has also been the ous enjoyment of exercise and spread replacement of blueprints key to decreasing the cost of elec- entertainment. Immense fantasy by digital displays as the human- tronically accessible information worlds created for video games machine link, illustrated by the storage. The amount of informa- have invaded leisure time. Cell “paperless airplane,” the Boeing tion that can be stored on a single phones have become an essential 777. chip has increased from the one part of the lives of many people The technologies of warfare and kilobit of 1970 to several gigabits and brought voice communication national defense may be the great- today, while access times have to areas where physical wires are est beneficiaries of increasing inte- decreased. Part of the larger num- absent. "Electronic slide rules" in gration as well as a powerful force ber of transistors available on the form of numerical calculators driving innovation in electronics. microprocessor chips are now that fit into a pocket replaced addi- The portability conferred by small used as a rapidly accessible part of tion and multiplication with paper size and light weight often far out- a memory hierarchy. and pencil. Human lives are weighs cost in military applica- The market for computing enhanced by the hearing aids, car- tions. Deploying compact sophisti- power values MIPS (millions of diac pacemakers, and implantable cated communication and naviga- instructions per second), along defibrillators that owe their exis- tion equipment throughout a com- with the ability to store and access tence to the miniaturization of bat force, from individuals and an abundance of information. The electronics. Equipment in an vehicles on a battlefield to aircraft rapid increase in the number of sil- automobile can direct us towards and ships at sea offers the ability to icon transistors integrated on a chip our destination, courtesy of elec- distribute command and tactical has reduced the cost per MIP by a tronics that can correlate informa- information to all that need it. factor of almost 100 per decade for tion received from space, from The Global Positioning System forty years, while the cost of mem- satellites of the Global Positioning began as a military project for just ory decreased by a factor of 2/3 System, with maps stored in inte- this purpose. One can only guess per year. The long decrease in the grated circuits. Attempts to find what may be happening in many cost of these computing essentials, such large new markets for “con- defense-related technologies, e. g., aided by the small size, light sumer” applications of electronic automatic target recognition, cryp- weight, and power demand of sili- technology continue. tography, and intelligence gather- con electronics has encouraged the In addition to such impacts on ing. Freedom from a profit incen- penetration of computing technol- daily life, low-cost integrated elec- tive allows military support of

26 IEEE SSCS NEWSLETTER September 2006 sscs_NL0906r1 8/16/06 9:55 AM Page 27

TECHNICAL LITERATURE

early and speculative development world. The macroscopic view of efforts that can stimulate invention semiconductor components begins that often migrates to commercial to fail as sizes approach atomic applications. dimensions. Layers only a few Electronic processing is vital to a atoms thick are appearing in tran- vast field of imaging applications sistors, and tunneling renders that extend from digital display increasingly thin barrier layers screens to PowerPoint to monitor- more transparent to electrons. ing planet earth from space. Elec- However, the industry's long histo- tronically-enabled MRI and CAT ry of surmounting barriers that images and telemedicine aid health once appeared equally formidable care. Electronically stored digital encourages confidence in the snapshots made possible by cam- future. eras containing chips with millions Moore's Law is basically a of light-sensitive devices replace description and a consequence of silver-halide film. Electronic pro- the synergism between the increas- cessing of an artificial guide star ing computing power per dollar compensates for the fluctuating provided by the electronics indus- About the Author atmospheric distortion of telescop- try and the new and increasingly Robert W. Keyes received a Ph. ic images. The planned Large powerful applications that its cus- D. in physics from the University Synoptic Survey Telescope will tomers want. It also hints at what of Chicago. After several years at generate petabytes of imaging may be expected from the elec- the Westinghouse Research Labo- information for electronic analysis tronic industry. The international ratory in Pittsburgh, he joined and storage annually. Roadmaps are in large measure a IBM Research in Yorktown The growing dependence of guide to how projections of Heights, NY. During his tenure national economies on integrated Moore's Law to coming years there, he engaged in research and electronics led a consortium of might actually be achieved with development activity in physics governments along with industries real materials and tools. and materials science related to and universities to create an organ- However, the economic motiva- modern optical and electronic ization whose purpose is to antici- tion for the development of faster, technologies and their applica- pate the form of future products cheaper computing with silicon tions in electronics. for the guidance of research and integrated circuits exists regardless Keyes has received an IBM development activities and of sup- of what it is called; magnetic disk Invention Achievement Award for pliers to the electronics industries. files have experienced a rather eight issued patents and an IBM Forecasts are published periodical- parallel growth in density without Outstanding Contribution Award ly as “Roadmaps” that project the the decades-long progress being in 1963 for participation in the form of future chips and describe enshrined in a law. At least, development of the injection technological advances that are Moore's law has made integrated laser. He was elected to the needed to make them possible in electronics more newsworthy by National Academy of Engineering quantitative detail through another supplying journalists with an atten- in 1976 and is a Life Fellow of the fifteen or so years.3 Although the tion-getting phrase that is applied Institute of Electrical and Electron- Roadmaps identify difficulties for or misapplied to writings about ic Engineers and a Fellow of the which there is “no known solu- anything related to solid state elec- American Physical Society. He tion,” the act of predicting product tronics. received the IEEE W. R. G. Baker details through more than a Prize in 1976. decade into the future requires References Keyes served the American some optimism. 1. G. E. Moore, “Cramming Physical Society as chair of the Challenging scientific and engi- more components onto inte- committee on applications of neering problems that are well grated circuits,” 1965 Elec- physics for three years and as asso- beyond the abilities of today's inte- tronics 38 pp. 114-117 (1965). ciate editor of the Reviews of Mod- grated electronics exist, and the 2. G. E. Moore, “Progress in dig- ern Physics for applications of search for new product opportuni- ital electronics,” 1975 IEDM, physics from 1976 to 1995. He ties to exploit continues, but the pp. 11-13. spent the fall of 1996 as Girling miniaturization of devices in pur- 3. International Technology Watson Visiting Professor in the suit of Moore’s Law is colliding Roadmap for Semiconductors, electrical engineering department with basic aspects of the physical http://public.itrs.net/ of the University of Sydney.

September 2006 IEEE SSCS NEWSLETTER 27 sscs_NL0906r1 8/16/06 9:55 AM Page 28

TECHNICAL LITERATURE The Wider Impact of Moore’s Law David E. Liddle, Ph.D., U.S. Venture Partners, [email protected]

s everyone interested in improvement which transfers the niques and I/O controllers were such topics knows, Moore’s maximum profit from the comput- different in every product genera- ALaw began as an empirical er industry to the semiconductor tion and from every vendor. Before observation, a post-hoc curve-fitting industry.” It is NOT the maximum System 360, introduced in 1964 by exercise that highlighted the process improvement/feature size IBM, there had hardly been two remarkable and accelerating reduction rate possible technically, consecutive models that were progress of semiconductor technol- nor is it limited by capital spending compatible. These dramatic ogy. It quickly became a leitmotif in on new equipment. It is the rate at changes in direction meant that no every discussion of technology. And which each product generation particular design ever had enough despite the widely diverse tech- lasts long enough to be (marginal- customers to become low in cost, niques through which it has been ly) profitable for the systems ven- or to allow a meaningful inde- sustained, it has gained and held the dors, and yet provides new prod- pendent software industry to arise unquestioned character of a physi- uct introductions to customers at a (virtually all software was vendor cal law, deeply believed and con- pace at which they will consider dependent, either provided by the sidered to be immutable by con- them seriously. This economic vendor or by the customer). Each sumers, engineers, executives and influence has become the means small step produced improved financiers, world-wide. by which Moore’s Law has not cost/performance, but at great Although Moore’s original 1965 only driven the semiconductor sec- expense to vendor and customer. article described doubling the tor, but has restructured, marginal- Moore’s Law raised the velocity number of transistors every 12 ized, or greatly invigorated other of cost/performance improvement months, rather than today’s popu- sectors as well, as we will discuss far above maneuvering speed for lar form, which has microproces- further. the computer industry. That is, the sor performance doubling every 18 One might well ask “How does tremendous rate of improvement months (as our folklore maintains), all this economic influence create a in cost/performance via feature these considerations are secondary technical cross-impact?” Consider size reduction made it unwise for to a much larger truth, which an analogy with the flight of an air- computer vendors to attempt Moore clearly emphasized in his craft. Every aircraft has a speed architectural changes, which article: namely the overwhelming called maximum operating speed meant in turn that the semiconduc- role of increasing integration in (or “never exceed” speed), above tor suppliers took control of the reducing cost per function or per which the aircraft is unsafe to fly. architecture of their customers’ operation. Twenty years ago, Gor- Another lower speed is called Va designs by integrating more func- don Moore understood that he was (maneuvering speed). It is safe to tion in their chips, running them describing an economic, rather fly above this speed, but only in faster, and reducing electronic than technological phenomenon, straight and level flight, without costs steadily. with the potential to restructure any changes of direction. In other This, in turn, meant that these whole industries, indeed whole words, motion is confined to only high performance and low cost economies. one dimension, which allows processors and memories were A few times a year, we hear an greater speed but no significant available to all incumbent comput- envious voice from the belea- changes in other dimensions. In er vendors and to industry new- guered optical components sector order to allow for arbitrary comers as well. Over a fifteen year (or the even more-oppressed disk changes in heading or altitude, the period, the existing computer drive sector) say something like, aircraft must slow down below Va. industry was commoditized, and “Big Deal. We can improve our An enormous impact of Moore’s slowly destroyed. Even IBM was technology even faster than Law was to dramatically constrain forced to transform itself further in Moore’s Law!” This illustrates a and focus the computer industry. the direction of providing services basic misunderstanding of what For decades, before the advent of and to concentrate its own archi- Moore’s Law has become, namely significant levels of integration in tectural efforts in the very top of an economic law. semiconductors, innovations in the market. But this brave new In order to make this point computer architecture formed the world proved very hospitable to clearly, I give my interpretation of basis of competition among ven- low cost manufacturers, who con- Moore’s Law as applied today: dors. These innovations meant that centrated their efforts on power “Moore’s Law expresses that rate system organization, instruction and packaging and distribution, of semiconductor process sets, memory management tech- taking out costs and improving

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TECHNICAL LITERATURE

reliability and relying on Intel, the approaches delayed or aban- were just beginning to make real AMD or Motorola for the major doned by the course we’ve taken progress on the problem of pro- value creation. as an industry. gramming parallel machines, since A huge collateral effect of Programming in the 60’s and they seemed the most promising Moore’s Law was the creation of 70’s was a high form of technolog- architectural step toward a new the commercial software industry ical art, and computer science was level of performance. as a meaningful force in the econ- its guiding scripture. A rich body Parallel computing, too, was omy. This took place in two ways. of theory developed, as well as a frozen by the chill winds of First, the falling cost and wide software engineering discipline, Moore’s Law. In effect, every availability of powerful processors largely driven by the notions (true designer asked himself “Should I greatly increased the number of at the time) that computers were really build a dual processor computers in use, and thus suc- expensive, their resources limited, machine and the get software mod- cessful software products could be and programmers scarce. Thus ifications that are required, or just sold in enormous numbers at mod- great emphasis was placed on wait 18 months to have a single est prices. Secondly, the end of clever algorithms to require the CPU that’s twice as fast with no proliferation of architectural varia- least number of instructions or the additional effort?” Only now, that tions meant that a successful soft- smallest amount of memory or the limits of growth in CPU clock ware product need run on only both. Elegant, parsimonious pro- frequency are in sight, has really one or at most two different CPU gram design was celebrated. serious focus on significant multi- types, secure in the knowledge Improvements to compilers for processing entered the mainstream. that (a) this would cover virtually denser code and new languages Moore’s Law IS the story of the entire market of all vendors for programmer productivity were information technology in the past and customers, and (b) that there high priorities in academia and 40 years. Of course it has made the would be inexorable steady industry alike. It was a small and semiconductor industry an unbe- improvements in cost/performance much envied priesthood of those lievable success. But its cross- which would seldom require any that had access to a computer. impacts to the computer, commu- significant changes to the pro- This entire culture disappeared nications, consumer electronics grams, thus allowing larger soft- under the crashing wave of and software industries have ware investments to be made, in Moore’s Law. Clever, parsimonious changed our world, even beyond products which would surely per- designs were unnecessary in an what Gordon Moore foresaw in form better and better over time, era of ever faster and cheaper that short and brilliant article in courtesy of Moore’s Law. CPUs and memory, as were com- 1965. These three very large phenom- plex compilers that generated ena, i.e. the enormous growth of smaller code. Programmer produc- About the Author the semiconductor industry, the tivity was suddenly a different mat- David Liddle joined U.S. Venture commoditization of the computer ter when everyone had access to Partners in January 2000, after industry and the emergence of a their own machine, night and day. retiring as president and CEO of huge software industry are of Computer science has reinvented Interval Research Corporation, a course mutually dependent, and itself very successfully around top- Silicon Valley-based laboratory and have created the economic frame- ics like networking, databases, and incubator for new businesses work that has held Moore’s Law in search. Programming, however, focused on broadband applica- place for so long. That the rewards will never be the same. It’s tions and advanced technologies, have fallen disproportionately to become a pick-and-shovel techni- founded in 1992. David is also a Intel, Microsoft, Oracle and Cisco cal activity, where knowing the consulting professor of Computer is incidental; the global wealth and peculiarities of J2EE is vastly more Science at Stanford University and productivity created by the sim- useful than knowing complexity has spent his career in Silicon Val- plicity and constancy of Moore’s theory. ley, in activities spanning research, Law (or rather, our belief in it) has Another area of technology development, management and deeply changed civilization, our completely knocked off the track entrepreneurship. Prior to co- very concepts of information and by Moore’s Law is parallel comput- founding Interval with Paul Allen, our access to it. ing. In the 70’s, very large scientif- he founded Metaphor Computer However, staying strictly on any ic computers with parallelism Systems in 1982 and served as its technical path involves bypassing among several arithmetic units president and CEO. The company others; sacrificing progress in some were just beginning to work well, was acquired by IBM in 1991 and areas to sustain it in another. It is after a few failures. And equally David was named vice president, certainly worth examining some of important, software researchers Business Development, IBM Per-

September 2006 IEEE SSCS NEWSLETTER 29 sscs_NL0906r1 8/16/06 9:55 AM Page 30

TECHNICAL LITERATURE

sonal Systems. Before that, from M.S.E.E. and Ph.D. at the Universi- 1972 to 1982, he held various R&D ty of Toledo. For his contributions and management positions at to human-computer interaction Xerox Corporation and at its Palo design, he has been named a Alto Research Center. While there, Senior Fellow of the Royal College he was vice president and general of Art. He also serves as a director manager, Office Systems Division. of the New York Times Company. David has served as a director at David currently represents USVP Sybase, Broderbund Software, Bor- as a director at Caspian Networks, land International and Ticketmas- MaXXan, T-RAM, Inc., Axiom ter Group, as well as numerous Microdevices, Optichron Corp., private companies, and as Chair of MaxLinear, Gear6, Klocwork, the Board of Trustees of the Santa Instantis and PacketHop Inc. Fe Institute. He has served on the His primary investment areas DARPA Information Science and are in RF and analog semiconduc- Technology Committee, and the Research Council. He earned a B.S. tors, cellular and wireless network- Computer Science and Telecom- in Electrical Engineering at the ing, signal processing, and data- munications Board of the National University of Michigan, and an center networks. Back to the Future, Part IV: Moore’s Law, the Legend, and the Man Eugene S. Meieran

or 43 years, I have worked for the computational power of an Gordon Moore in one compa- Apollo space mission. Your car has Fny or another - Fairchild Semi- computers that protect you from conductor and Intel. During these skids and accidents and speed 43 years, I have witnessed an almost traps and tell you where you are unprecedented event: the evolution and where you are going and how of a simple observation made 41 to get there. You can interact with years ago into what is now known the movie or game you watch or as a “law.” Moore's Law, a name participate in, etc. Expanding com- only recently accepted and used by plexity surrounds us. Gordon himself, is not a “law” in the conventional sense, such as a law of Complexity Begets nature (gravity, motion, relativity, Complexity etc.) or a social necessity (traffic Second, we recognize that the law, criminal law, corporate law, ONLY way to manage this com- etc.), or a law of economics ("buy plexity is to introduce more com- low, sell high"), but a law of tech- Gordon Moore named Honorary Intel plexity! We need computers and nology....that human beings will Fellow, 2005. GPS systems and cell phones and continue to create more complex virtual reality and traffic control objects and devices at an expo- I believe there are three ingredients systems and electronic transactions nential rate, which for semicon- that have led to this phenomenon. simply to deal with more traffic, ductor devices equates to a dou- more people with whom we inter- bling of complexity about every 18 Complexity is Ubiquitous act, with global economies, etc. months. First, the Law is easy for anybody The complexity of everyday life What has caused a simple to understand: People who are feeds upon itself. I am sure the observation made 41 years ago to confronted every day with ever same issue faced ants and bees and actually become a driving force for increasing complexity relate to it termites, which evolved over mil- the world's economy? What is so instantly without direct knowledge lions of years into sophisticated magical, so riveting, about Moore's of how it works. Get on the phone and highly complex societies sim- Law that has caused it to capture or drive your car or be entertained ply to deal with a more complex global attention and become a on an iPod and you are confront- world consisting of ever more com- commonly used term by a huge ed with complexity. Your phone plex predators and environmental segment of the world's population? now has capabilities that exceed conditions. Now we must evolve to

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meet challenges in months and lating! But only later did the signif- the physicist who co-invented the years, rather than millennia. icance of Moore's Law and the rap- integrated circuit (with Jack Kilby), idly expanding universe of semi- and the physical chemist Gordon Moore’s Law Is Recursive conductor device technology Moore, the visionary of the technolo- And finally, Moore's Law has become obvious, after the micro- gy era and articulator of Moore's Law. become a self fulfilling prophecy. processor and personal computer Since we all regard Moore's Law as a started to become readily avail- Approachable and Gracious, scientific law rather than an extrapo- able. Fortunately, Gordon is still Moore Impacts People lated observation, and since the around to see the impact he has Simply stated, Gordon is a man development of new technology to made, unlike many visionaries. who, for more than four decades stay on Moore's Law presents ever As I look back to those early days, now, is liked, respected, honored greater challenges, there is a global I remember the environment, where and revered by virtually everyone feeding frenzy as companies strive to engineers and scientists had who comes in contact with him. be first, competing to develop new OFFICES (you know, those things The honors, the respect, even the technology and products. And since with walls and doors), and where reverence has not affected him in this is so difficult, so complex, one smart people of many different disci- any way that one can see; although has to invent new complexity! In plines were co-located and were people might be disinclined to sim- the semiconductor industry this within shouting distance of one ply go up to him and talk, that is implies smaller feature sizes, which another....I think this personal inter- not because of Gordon himself but imply better tools and better analysis action -- before the advent of email because of the legend of Gordon procedures and better process con- and conference phones and cell Moore. Gordon is still not only trol and better clean room facilities, phones and meetings with dozens of approachable, but is gracious and each of which requires more com- people located all over the globe all affable at the same time. I believe plexity. So we have a vicious circle trying to talk simultaneously --gener- this personality has also con- which shows no sign of abating: ated enthusiasm. Of course this tributed to the strength of Moore's People are surrounded by increasing could be simple nostalgia. None-the- Law; the Law is for technology but complexity and resort to more com- less, the fact that one could sit down Gordon is for technologists. plex tools to manage it. So the tool with Andy or Bob or Gordon and makers make ever more complex discuss ideas, and have technical ses- tools, which require even more com- sions with huge intellect sitting next plex tools to satisfy the demand for to you was different from doing the tools to manage more complexity. same with disembodied voices over the phone. Those were the days! A Straight Line in a Semi-log Graph Collaboration on Some- Moore's Law and Moore's Legend thing IMPORTANT emerged from Gordon’s observations This brings us to the personal side of on the newly invented integrated cir- Moore's Law which can only have Gordon, S. H. Wong (Head of Intel Assembly Test Facilities in the Far cuit, which translate into a simple been experienced by people work- East) and the author at an Intel Man- straight line when plotted in an easi- ing in the field, most particularly ufacturing Excellence Conference, ly understood semi-log graph. working directly with Gordon. I am about ten years ago. sure that the excitement, the belief People in Co-located Offices that one was doing something As I sit and think about what to Within Shouting Distance IMPORTANT, has been felt by only a say in this message, I wonder if I Of course, while all this was hap- fortunate few over technology histo- am too flowery, too praiseful of pening, one did not know that ry: for example, working with Gordon Moore, simply because I earth-shattering events were taking Thomas Edison as he invented the have been directly associated with place. Certainly it was exciting to light bulb or phonograph; with the him and know what his law has work at Fairchild in those days, Wright Brothers as they created the done for the world economy. And with Wednesday technology semi- first airplanes; with Alexander Gra- then I say to myself, "No, you are nars with Gordon, Bob Noyce, ham Bell at the invention of the tele- not being excessive; if you err, it is Andy Grove, Herb Kroemer (who phone, and with a few others, includ- in not being able to truly convey received the Nobel Prize in Physics ing Gordon Moore and Bob Noyce. what this man has done for socie- a few years ago), Carver Mead and Personally, I can imagine no other ty, through Moore's Law and Jim Gibbons often participating. environment that would be as satisfy- through his strong concerns for the The environment was truly stimu- ing as to work for Noyce and Moore, global environment, and through

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his ability to positively influence predicted by science and science fic- mentation of Statistical Process everyone with whom he comes tion writer Arthur C. Clarke more Control (SPC) in many manufactur- into contact." What I say here may than 50 years ago! But now, science ing sites. Since 1987, he has been a be biased, but I believe justifiably fiction writers are using Moore's Law member of Intel's Technology Man- biased and probably uncontested to write stories using devices operat- ufacturing Engineering group for by anyone, regardless of profes- ing at the neutron, proton, electron, introducing advanced technology sion, position or accomplishments. photon level; Gordon not only influ- into manufacturing facilities. He is enced real technology, but science currently working on knowledge fiction as well! So his straight line management, collaboration and curve will live on and people will innovation issues to leverage Intel's continue to strive to invent technolo- vast corporate knowledge base to gy to meet the needs of this obser- help individuals and teams become vation-turned into Law, this great more productive. influence on all aspects of our world. Gene has published about 50 And it could not have been technical papers, and has received done by a nicer person than Gor- three international awards for his don E. Moore. I am truly honored work in semiconductor device tech- just to have the pleasure of writing nology. He has given seminars and A tongue-in-cheek, never-published photo of a wafer-size prediction my thoughts about this most invited talks at numerous American according to Moore's Law, made by extraordinary individual and his and international universities, and Gordon for the author at an Electron- extraordinary Law. served as Director of Research for ic Materials Conference in Santa Clara MIT's Leaders for Manufacturing about ten years ago, just to prove program from 1993 to 2000. Moore's Law cannot be applied simul- Gene has been the Intel judge for taneously, or accurately, to all aspects the Intel International Science and of semiconductor technology. Engineering Fair for 12 years. He is a Moore’s Law in the Future member of the Board of Advisors for As Gordon often says, no expo- the Materials Engineering Depart- nential extrapolation can go on ment at Purdue and the Dean's Board forever. We cannot expect Moore's of Advisors at the University of New Law for the semiconductor-based Mexico, and served in equivalent industry to go beyond a few more capacities at UC Berkeley and generations in the conventional Lawrence Berkeley Labs. In 1987, sense (silicon based integrated cir- Purdue University elected him Distin- cuits), due to the push-back of guished Engineering Alumnus. He physical laws, although it must be was elected to the National Academy understood that this battle has of Engineering in 1988 and received already gone on for decades, and About The Author an honorary Doctorate from Purdue Moore's Law has prevailed in spite Eugene S.Meieran received his B.S. University in 2004. He was also of predictions that the physical Degree in Metallurgy from Purdue awarded the prestigious Carnegie limits are now not able to be University in 1959 and his Doctor's Medal by the Carnegie Museum, pushed further! But the end will degree in Material Science from Pittsburgh. He was named Senior come, in the conventional sense. MIT in 1963. He joined Fairchild Intel Fellow in 2004 and has also On the other hand, there are new Semiconductor R&D in 1963, spe- been a member of numerous Nation- and emerging technologies that cializing in analysis and characteri- al Research Council committees. might extend Moore's Law for sever- zation of semiconductor materials, Gene plays the flute and is an al more orders-of-magnitude increas- and became Manager of the new avid collector of fine mineral and es in chip complexity over another Package Development group now crystal specimens. He currently 20 or 30 years. And after that, as sci- known as ATD at Intel in 1973. resides in Phoenix, AZ, with his entists delve into the mysteries of In 1977, he transferred to Intel’s wife, Rosalind, a ceramic sculp- quantum and nuclear physics, who Quality and Reliability Department tress. His daughter Sharon is an knows what kinds of devices might for Intel materials technology, Mate- Emergency Room resident in emerge? Strange as it seems, few if rials Analysis Laboratories and man- Cincinnati, and his son Andrew is any predicted the PC and hand-held ufacturing process reliability, and in doing building redevelopment in devices enabled by following 1985, he was recognized as Intel's Los Angeles. He has two young Moore's Law, while geosynchronous 2nd Fellow for his work on soft granddaughters and by the time satellites for communications were error analysis and for his imple- you read this, a new grandson.

32 IEEE SSCS NEWSLETTER September 2006 sscs_NL0906r1 8/16/06 9:55 AM Page 33

TECHNICAL LITERATURE Cramming more components onto integrated circuits

Reprinted from Electronics, Volume 38, Number 8, April 19, 1965, pp.114 ff.

Gordon E. Moore, Co-founder Intel Corporation

ith unit cost falling as the plied to the user as irreducible employing integrated electronics. number of components units. These technologies were first These machines cost less and per- Wper circuit rises, by 1975 investigated in the late 1950’s. The form better than those which use economics may dictate squeezing as object was to miniaturize electron- conventional. electronics. many as 65,000 components on a ics equipment to include increas- Instruments of various sorts, single silicon chip ingly complex electronic func- especially the rapidly increasing The future of integrated elec- tions in limited space with mini- numbers employing digital tech- tronics is the future of electronics mum weight. Several approaches niques, are starting to use integra- itself. The advantages of integra- evolved, including microassembly tion because it cuts costs of both tion will bring about a proliferation techniques for individual compo- manufacture and design. of electronics, pushing this science nents, thin-film structures and The use of linear integrated cir- into many new areas. semiconductor integrated circuits. cuitry is still restricted primarily to Integrated circuits will lead to Each approach evolved rapidly the military. Such integrated func- such wonders as home computers - and converged so that each bor- tions are expensive and not avail- or at least terminals connected to a rowed techniques from another. able in the variety required to sat- central computer - automatic con- Many researchers believe the way isfy a major fraction of linear elec- trols for automobiles, and personal of the future to be a combination tronics. But the first applications portable communications equip- of the various approaches. are beginning to appear in com- ment. The electronic wristwatch The advocates of semiconductor mercial electronics, particularly in needs only a display to be feasible integrated circuitry are already equipment which needs low-fre- today. using the improved haracteristics quency amplifiers of small size. But the biggest potential lies in of thin-film resistors by applying the production of large systems. In such films directly to an active Reliability counts telephone communications, inte- semiconductor substrate. Those In almost every case, integrated grated circuits in digital filters will advocating a technology based electronics has demonstrated high separate channels on multiplex upon films are developing sophis- reliability. Even at the present level equipment. Integrated circuits will ticated techniques for the attach- of production, low compared to also switch telephone circuits and ment of active semiconductor that of discrete components, it perform data processing. devices to the passive film arrays. offers reduced systems cost, and in Computers will be more power- Both approaches have worked many systems improved perform- ful, and will be organized in com- well and are being used in equip- ance has been realized. pletely different ways. For exam- ment today. Integrated electronics will make ple, memories built of integrated electronic techniques more gener- electronics may be distributed The establishment ally available throughout all of throughout the machine instead of Integrated electronics is estab- society, performing many func- being concentrated in a central lished today. Its techniques are tions that presently are done inad- unit. In addition, the improved almost mandatory for new military equately by other techniques or reliability made possible by inte- systems, since the reliability, size not done at all. The principal grated circuits will allow the con- and weight required by some of advantages will be lower costs and struction of larger processing units. them is achievable only with inte- greatly simplified design-payoffs Machines similar to those in exis- gration. Such programs as Apollo, from a ready supply of low-cost tence today will be built at lower for manned moon flight, have functional packages. costs and with faster turn-around. demonstrated the reliability of inte- For most applications, semicon- grated electronics by showing that ductor integrated circuits will pre- Present and future complete circuit functions are as dominate. Semiconductor devices By integrated electronics, I mean all free from failure as the best indi- are the only reasonable candidates the various technologies which are vidual transistors. presently in existence for the referred to as microelectronics today Most companies in the commer- active elements of integrated cir- as well as any additional ones that cial computer field have machines cuits. Passive semiconductor ele- result in electronics functions sup- in design or in early production ments look attractive too, because

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of their potential for low cost and a rate of roughly a factor of two underway using multilayer metal- high reliability, but they can be per year (see graph on next page). ization patterns separated by dielec- used only if precision is not a Certainly over the short term this tric films. Such a density of compo- prime requisite. rate can be expected to continue, nents can be achieved by present Silicon is likely to remain the if not to increase. Over the longer optical techniques and does not basic material, although others will term, the rate of increase is a bit require the more exotic techniques, be of use in specific applications. more uncertain, although there is such as electron beam operations, For example, gallium arsenide will no reason to believe it will not which are being studied to make be important in integrated remain nearly constant for at least even smaller structures. microwave functions. But silicon 10 years. That means by 1975, the will predominate at lower frequen- number of components per inte- Increasing the yield cies because of the technology grated circuit for minimum cost There is no fundamental obstacle which has already evolved around will be 65,000. to achieving device yields of 100%. it and its oxide, and because it is I believe that such a large circuit At present, packaging costs so far an abundant and relatively inex- can be built on a single wafer. exceed the cost of the semicon- pensive starting material. ductor structure itself that there is Two-mil squares no incentive to improve yields, but Costs and curves With the dimensional tolerances they can be raised as high as is Reduced cost is one of the big already being employed in inte- economically justified. No barrier attractions of integrated electron- grated circuits, isolated high-per- exists comparable to the thermo- ics, and the cost advantage con- formance transistors can be built dynamic equilibrium considera- tinues to increase as the technolo- on centers two thousandths of an tions that often limit yields in gy evolves toward the production inch apart. Such a two-mil square chemical reactions; it is not even of larger and larger circuit func- can also contain several kilohms of necessary to do any fundamental tions on a single semiconductor resistance or a few diodes. This research or to replace present substrate. For simple circuits, the allows at least 500 components per processes. Only the engineering cost per component is nearly linear inch or a quarter million per effort is needed. inversely proportional to the num- square inch. Thus, 65,000 compo- £È ber of components, the result of nents need occupy only about £x £{ the equivalent piece of semicon- one-fourth a square inch. £Î ductor in the equivalent package £Ó £äx ££ containing more components. But £ä £ÈÓ as components are added, n { £ä Ç decreased yields more than com- È

*iÀÊÌi}À>Ìi`ÊÕVÌ x pensate for the increased com- £Èx vÊÌ iÊ ÕLiÀÊvÊ «iÌÃÊ £äÎ ÓÊ {

plexity, tending to raise the cost } Î Ó per component. Thus there is a £ £äÓ £Çä

minimum cost at any given time £x £Èä £È£ £ÈÓ £ÈÎ £È{ £Èx £ÈÈ £ÈÇ £Èn £È £Çä £Ç£ £ÇÓ £ÇÎ £Ç{ £Çx

9i>À in the evolution of the technolo- £ä ,i>ÌÛiÊ >Õv>VÌÕÀ}Ê ÃÌÉ «iÌ gy. At present, it is reached when Figure 2 (label added for this reprint) 50 components are used per cir- £ Log2 of the number of components cuit. But the minimum is rising £Ê £äÊ £äÓÊ £äÎÊ £ä{Ê £äx per integrated function versus year. rapidly while the entire cost curve ÕLiÀÊvÊ «iÌÃÊ*iÀÊÌi}À>Ìi`Ê ÀVÕÌ is falling (see graph below). If we Figure 1 (label added for this reprint) In the early days of integrated cir- look ahead five years, a plot of relative manufacturing cost/compo- cuitry, when yields were extremely nent versus number of components costs suggests that the minimum per integrated circuit. low, there was such incentive. cost per component might be Today ordinary integrated circuits expected in circuits with about On the silicon wafer currently are made with yields comparable 1,000 components per circuit used, usually an inch or more in with those obtained for individual (providing such circuit functions diameter, there is ample room for semiconductor devices. The same can be produced in moderate such a structure if the components pattern will make larger arrays eco- quantities.) In 1970, the manufac- can be closely packed with no nomical, if other considerations turing cost per component can be space wasted for interconnection make such arrays desirable. expected to be only a tenth of the patterns. This is realistic, since present cost. efforts to achieve a level of com- Heat problem The complexity for minimum plexity above the presently avail- Will it be possible to remove the component costs has increased at able integrated circuits are already heat generated by tens of thou-

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Figure 3 (label added for this reprint)

sands of components in a single by a particular array. Perhaps tions for tuning functions, but silicon chip? newly devised design automation inductors and capacitors will be If we could shrink the volume procedures could translate from with us for some time. of a standard high-speed digital logic diagram to technological The integrated r-f amplifier of computer to that required for the realization without any special the future might well consist of components themselves, we engineering. integrated stages of gain, giving would expect it to glow brightly It may prove to be more eco- high performance at minimum with present power dissipation. nomical to build large systems cost, interspersed with relatively But it won.t happen with integrat- out of smaller functions, which large tuning elements. ed circuits. Since integrated elec- are separately packaged and Other linear functions will be tronic structures are two-dimen- interconnected. The availability of changed considerably. The match- sional, they have a surface avail- large functions, combined with ing and tracking of similar com- able for cooling close to each cen- functional design and construc- ponents in integrated structures ter of heat generation. In addition, tion, should allow the manufac- will allow the design of differen- power is needed primarily to turer of large systems to design tial amplifiers of greatly improved drive the various lines and capac- and construct a considerable vari- performance. The use of thermal itances associated with the sys- ety of equipment both rapidly feedback effects to stabilize inte- tem. As long as a function is con- and economically. grated structures to a small frac- fined to a small area on a wafer, tion of a degree will allow the the amount of capacitance which Linear circuitry construction of oscillators with must be driven is distinctly limit- Integration will not change linear crystal stability. ed. In fact, shrinking dimensions systems as radically as digital sys- Even in the microwave area, on an integrated structure makes tems. Still, a considerable degree structures included in the defini- it possible to operate the structure of integration will be achieved tion of integrated electronics will at higher speed for the same with linear circuits. The lack of become increasingly important. power per unit area. large-value capacitors and induc- The ability to make and assemble tors is the greatest fundamental components small compared with Day of reckoning limitations to integrated electronics the wavelengths involved will Clearly, we will be able to build in the linear area. allow the use of lumped parame- such component-crammed equip- By their very nature, such ele- ter design, at least at the lower fre- ment. Next, we ask under what cir- ments require the storage of quencies. It is difficult to predict at cumstances we should do it. The energy in a volume. For high Q it the present time just how exten- total cost of making a particular is necessary that the volume be sive the invasion of the microwave system function must be mini- large. The incompatibility of area by integrated electronics will mized. To do so, we could amor- large volume and integrated elec- be. The successful realization of tize the engineering over several tronics is obvious from the terms such items as phased-array anten- identical items, or evolve flexible themselves. Certain resonance nas, for example, using a multi- techniques for the engineering of phenomena, such as those in plicity of integrated microwave large functions so that no dispro- piezoelectric crystals, can be power sources, could completely portionate expense need be borne expected to have some applica- revolutionize radar.

September 2006 IEEE SSCS NEWSLETTER 35 sscs_NL0906r1 8/16/06 9:55 AM Page 36

Gordon E. Moore, Co-founder Intel Corporation

omplexity of integrated cir- plexity curve. Chip area tor maxi- cuits has approximately dou- mum complexity has increased by Cbled every year since their a factor of approximately 20 from introduc?tion. Cost per function has the first planar transistor in 1959 to decreased several thousand-fold, the 16,384-bit charge-coupled while system performance and reli- device memory chip that corre- ability have been improved dramat- sponds to the point plotted for ically. Many aspects of processing 1975, while complexity, according and design technology have con- to the annual doubling law, Figure 3 Device density contribution tributed to make the manufacture of should have increased about from the decrease in line widths and such functions as complex single 65,000-fold. Clearly much of the spacings. chip microprocessors or memory increased complexity had to result circuits economically feasible. It is from higher density of compo- exponential growth. From the possible to analyze the increase in nents on the chip, rather than exponential approximation repre- complexity plotted in Figure 1 into from the increased area available sented by the straight line in Figure different factors that can, in turn, be through the use of larger chips. 3, the increase in density from this examined to see what contributions source over the 1959-1975 period have been important in this devel- is a factor of approximately 32. opment and how they might be Combining the contribution of expected to continue to evolve. The larger chip area and higher density expected trends can be recombined resulting from geometry accounts to see how long exponential growth for a 640-fold increase in complex- in complexity can be expected to ity, leaving a factor of about 100 to Figure 2 Increase in die area for continue. account for through 1975, as is most complex integrated devices commercially available. shown graphically in Figure 4. This factor is the contribution of circuit Density was increased partially and device advances to higher by using finer scale microstruc- density. It is noteworthy that this tures. The first integrated circuits contribution to complexity has of 1961 used line widths of 1 mil been more important than either (~25 micrometers) while the 1975 increased chip area or finer lines. device uses 5 micrometer lines. Increasingly the surface areas of Both line width and spacing the integrated devices have been between lines are equally impor- committed to components rather tant in improving density. Since than to such inactive structures as they have not always been equal, Figure 1 Approximate component the average of the two is a good count for complex integrated circuits parameter to relate to the area that vs. year of Introduction. a structure might occupy. Density can be expected to be proportion- A first factor is the area of the al to the reciprocal of area, so the integrated structures. Chip areas contribution to improve density vs. for some of the largest of the cir- time from the use of smaller cuits used in constructing Figure 1 dimensions is plotted in Figure 3. are plotted in Figure 2. Here Neglecting the first planar tran- again, the trend follows an expo- sistor, where very conservative line nential quite well, but with signif- width and spacing was employed, Figure 4 Decomposition of the com- icantly lower slope than the com- there is again a reasonable fit to an plexity curve into various components.

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device isolation and interconnec- micrometer dimensions show that tions, and the components them- no basic problems should be selves have trended toward mini- expected at least until the average mum size, consistent with the line width andspaces are a dimensional tolerances employed. micrometer or less. This allows for an additional factor of improve- Can these trends continue? ment at least equal to the contri- Extrapolating the curve for die size bution from the finer geometries of to 1980 suggests that chip area the last fifteen years. Work in non- might be about 90,000 sq. mils, or optical masking techniques, both the equivalent of 0.3 inches electron beam and X-ray, suggests Figure 5 Projection of the complexity square. Such a die size is clearly that the required resolution capa- curve reflecting the limit on increased consistent with the 3 inch wafer bilities will be available. Much density through invention. presently widely used by the work is required to be sure that industry. In fact, the size of the defect densities continue to in Figure 1, but it is unlikely that wafers themselves have grown improve as devices are scaled to the packing efficiency alone can about as fast as has die size during take advantage of the improved contribute as much as a factor of the time period under considera- resolution. However, I see no rea- four, and this only in serial data tion and can be expected to con- son to expect the rate of progress paths. Accordingly, I am inclined tinue to grow. Extension to larger in the use of smaller minimum to suggest a limit to the contribu- die size depends principally upon dimensions in complex circuits to tion of circuit and device clever- the continued reduction in the decrease in the near future. This ness of another factor of four in density of defects. Since the exis- contribution should continue component density. tence of the type of defects that along the curve of Figure 3. With this factor disappearing as harm integrated circuits is not fun- With respect to the factor con- an important contributor, the rate damental, their density can be tributed by device and circuit clev- of increase of complexity can be reduced as long as such reduction erness, however, the situation is expected to change slope in the has sufficient economic merit to different. Here we are approaching next few years as shown in Figure justify the effort. I see sufficient a limit that must slow the rate of 5. The new slope might approxi- continued merit to expect progress progress. The CCD structure can mate a doubling every two years, to continue for the next several approach closely the maximum rather than every year, by the end years. Accordingly, there is no density practical. This structure of the decade. present reason to expect a change requires no contacts to the Even at this reduced slope, inte- in the trend shown in Figure 2. compo?nents within the array, but grated structures containing sever- With respect to dimensions, in uses gate electrodes that can be at al million components can be these complex devices we are still minimum spacing to transfer expected within ten years. These far from the minimum device sizes charge and information from one new devices will continue to limited by such fundamental con- location to the next. Some reduce the cost of electronic func- siderations as the charge on the improvement in overall packing tions and extend the utility of dig- electron or the atomic structure of efficiency is possible beyond the ital electronics more broadly matter. Discrete devices with sub- structure plotted as the 1975 point throughout society. Lithography and the Future of Moore’s Law Copyright 1995 IEEE. Reprinted with permission. Proc. SPIE Vol. 2437, pp. 2-17.

Gordon E. Moore, Co-founder Intel Corporation

he definition of “Moore’s restrict it's definition. tinuing on the same slope doesn’t Law” has come to refer to However, today I will review the get any easier. It presents a difficult Talmost anything related to the history and past performance rela- challenge to the industry. semiconductor industry that when tive to predictions and show The original paper that postulat- plotted on semi-log paper approxi- where the advances have come ed the first version of the “law” mates a straight line. I hesitate to from. I will leave the future per- was an article I wrote for the 35th review its origins and by doing so formance up to you. Certainly con- anniversary issue of Electronics

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Magazine in 1965. My assignment down as we improved out pro- was to predict what was going to cessing capability. happen in the semi-conductor Next I looked at how complex components industry over the next integrated circuits should minimize ten years — to 1975. In 1965 the cost per component and reasoned integrated circuit was only a few that the most complex circuit at years old and in many cases was any time would not be much more not very well accepted. There was complex than this minimum, still a large contingent in the user because of the steepness of the community who wanted to design curve beyond the minimum. The their own circuits and who consid- available data I chose started with ered the job of the semiconductor the first planar transistor, which industry to be to supply them with had been introduced in 1959. It Figure 3 Photomicrograph of the first transistors and diodes so they was really the first transistor repre- commercial planar transistor. could get on with their jobs. I was sentative of the technology used trying to emphasize the fact that for practical integrated circuits. It is integrated circuits really did have represented by the first point, two an important role to play. raised to the zero power, or one Let’s start with two figures from component. that original paper. Figure 1 shows my estimate of the cost of integrated circuits divided by the number of components, a component Figure 4 Photomicrograph of one of being a transistor, resistor, diode or the first planar integrated circuits pro- capacitor, in an integrated structure duced by Fairchild Semiconductor in at various times. the early 1960’s. Many of you were not in the industry when the devices represented by the first few points in this plot were introduced. I have Figure 2 The original “Moore’s Law” reproduced photomicrographs of plot from Electronics April 1965. the first planar transistor and the first commercially-available inte- Adding points for integrated cir- grated circuit in Figures 3 and 4. I cuits starting with the early “Micro- am particularly fond of the transis- logic” chips introduced by tor, since it is one of the very few Fairchild, I had points up to the 50- products that I designed myself 60 component circuit plotted for that actually went into production. 1965 as shown in Figure 2. On a The unusual diameter of 764 semi-log plot these points fell close microns was chosen because we Figure 1 Relative manufacturing cost per component vs. components in the to a straight line that doubled the were working in English units and circuit estimated for various times. complexity every year up until that is thirty thousandths of an 1965. To make my prediction, I just inch, or 30 mils. The minimum fea- In 1962 the minimum cost per extrapolated this line another ture size is the three mil metal line component occurred for circuits decade in time and predicted a making the circular base contact. containing about ten components. thousand-fold increase in the num- Metal-to-metal spacing is five mils For more complex circuitry costs ber of components in at the most to allow the 2.5 mil alignment tol- skyrocketed because yields col- complex circuits available commer- erance we needed. lapsed. With time, as processing cially. The cheapest component in Interestingly enough at the time improved, the minimum moved 1975 should be one of some 64,000 the idea for the planar transistor down and to higher complexity. in a complex integrated circuit. I was conceived by Jean Hoerni in When I wrote this article in 1965 did not expect much precision in the early days of Fairchild Semi- my estimate was that the minimum this estimate. I was just trying to get conductor, it had to sit untried for cost per component was achieved across the idea this was a technol- a couple of years, because we did with several tens of components in ogy that had a future and that it not have the technology to do four a circuit, and I predicted that the could be expected to contribute aligned mask layers. In fact, we minimum would continue to go quite a bit in the long run. were developing the technol?ogy

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to do two aligned oxide-masked }««}® dimensions. This increases the diffusions plus a mesa etching step density on the chip as the recipro- for transistors. The original step cal of the square of the minimum and repeat camera that Bob Noyce dimension, or the average of the designed using matched 16 mm minimum line width and spacing movie camera lenses had only in cases where they were not three lenses, so it could only step equal. Figure 7 shows that this also a three-mask set. We had to wait approximates an exponential until the first mesa transistors were growth of component density if in production before we could go one neglects the first point, which back and figure out how to make is reasonable, since the planar a four mask set to actually try the Figure 5 Approximate component transistor was not pushed to use planar idea. count for integrated circuits intro- the finest features that could be The first integrated circuit on the duced up to 1975 compared with the etched. We had enough other graph is one of the first planar inte- prediction of the most complex cir- problems to deal with on that grated circuits produced. It includ- cuits from the original Electronics device. paper (Figure 2). ed four transistors and six resistors. In Figure 8 the contributions to It has always bothered me that the This time I tried to resolve the increased complexity from larger picture of this important device curve into various contributions dice and finer dimensions are that got preserved was of the ugly from the technology to see where show along with the increase in chip shown in Figure 4. The circuit the progress was coming from. complexity achieved. They are had six bonding pads around the First, the dice were getting bigger. show individually and the product circumference of a circle for As defect densities decreased we of the two is also shown. Clearly mounting in an 8-leaded version of could work with larger areas while there is another contribution the old TO-5 outline transistor can. still maintaining acceptable yields. beyond these two. I attributed this In this case only six of the eight Many changes contributed to this, additional contribution to “circuit possible connections were not the least of which was moving and device cleverness.” Several required. We did not think we to optical projection rather than features had been added. Newer could make eight wire bonds with- contact printing of the patterns on approaches for device isolation, reasonable yield, so for these first the wafers. This increase in die for example, had squeezed out integrated circuits we etched a area followed a good approxima- much of the unused area. The round die that let us utilize blobs tion to exponential growth with advent of MOS integrated circuits of conducting epoxy to make con- time as can be seen from Figure 6. had allowed even tighter packing tact to the package pins. For the of components on the chips. die in the picture, the etching clearly got away from the etcher.

How good were my predictions? What really happened? Figure 5 adds the points for sever- Figure 6 Contribution to increasing al of the most complex integrated complexity resulting from increased circuits available commercially die area. Proceedings IEEE IEDM 1975. from 1965 to 1975. It was taken from an update of the industry’s progress that I presented at the 1975 IEEE International Electron Figure 8 Resolution of the increase in Devices Meeting. Generally they complexity into die size, dimension scatter pretty well along the line reduction and “cleverness” factors. that corresponds to doubling every Proceedings IEEE IEDM 1975. year. For a prediction of a thou- Figure 7 Contribution to increasing sand-fold increase in complexity, complexity from finer structures. Pro- Looking at this plot, I said that this fits pretty well. The last point ceedings IEEE IEDM 1975. approximately half the progress shown, for the most complex had come from die size and finer device, represents a 16k charge- Second, not only did we move structures, the remaining half from coupled-device (CCD) memory. I to larger dice, but we simultane- “cleverness.” If one looks closely, will come back to this in a minute. ously evolved to finer and finer however, more than half comes

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from the first two factors, more DRAMs was discovered, where size and density from smaller like 60 percent. I didn’t think that there would be occasional random dimensions, rather than the dou- the data was good enough to push losses of bits of information. The bling every two years that I used this much, however, so I stuck cause was traced to alpha particles before If I believed what the data with half. coming from the packaging materi- said, I would have drawn that line Remember that my most com- als generating enough hole-elec- and then, I guess, I would have plex device was a CCD memory. tron pairs in the silicon to destroy had much more reason to be The CCD structure is essentially the charge representing a bit. proud of my predictions of what active device area side by side. CCD’s are especially sensitive to has happened in the last 20 years. There is no room left to squeeze this phenomenon, in fact that is anything out by being clever. why they make such good imaging Going forward from here we devices. Our CCD’s proved to be have to depend on the two size the best vehicle to study the DRAM factors — bigger dice and finer problem and to test solutions. As dimensions. memories, they become just that...memories. The points that I thought I knew were coming never became commercial products. ««

Figure 11 What I calculated and should have said in 1975 vs. what has actually occurred.

Figure 9 My prediction of the maximum complexity limit in 1975. Pro- ceedings IEEE IEDM 1975. So I changed my projection looking forward. The complexity curve is going to change slope. Figure 10 Transistor count for various Instead of doubling every year, it DRAMs and microprocessors since 1975 will be closer to doubling every compared with the 1975 prediction. two years. But as can be seen in Figure 12 Contribution from increas- Figure 9, however, I did not pre- Figure 10 shows the actual ing die size over the most recent 25 dict that the slope would change progress in device complexity years. immediately, but left five years for since 1975 compared with my 1975 Let’s look at how this increase in it to rollover. This delay was prediction. Instead of continuing at complexity over the last period can because I had too much visibility the annual doubling rate for the be factored. Amazingly we have into what I believed to be the near next five years, the slope changes stayed very closely on the expo- future. immediately, which is what my nentials that were established dur- My problem was the CCD memo- calculation said should happen. ing the first fifteen year period. Fig- ries. Beyond the 16k that was This figure suggests that the 64meg ure 12 shows both microprocessor already on the market, I knew that DRAM will be commercially avail- and DRAM die size history. The Intel had a 64k product (>128k com- able this year. If it is delayed to microprocessor die tend to be a lit- ponents the way I counted CCD’s) next year, it will fit my plot better. tle larger, but the greater number of about ready to announce and we Such a delay would certainly not components is on the DRAMs. The were working on a 256k product. surprise me. best line through the points has a This suggested that I should push Let’s look at what I should have slightly smaller slope than the one out the time at which we slipped said based on my reasoning, rather in Figure 6, but the same within from doubling every year, because than what I did say based on too experimental error. We haven’t these CCD’s would keep us on the much information. In Figure 11, done quite as well here as we were old curve for a while. the slope changes right away start- doing during the first ten years. The thing that I couldn’t know ing with the 32,000 components of On the other hand, looking at was that the CCD memories would the 16k CCD. The new slope is Figure 13, the density contribution not be introduced. This was just very close to the one predicted by from decreasing line widths has when soft error problems with extrapolating the product of die stayed almost exactly on the same

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exponential trend as over the first or less conventional optics, prob- In fact, I still have trouble fifteen year period. If anything, the lems with depth of field, surface believing we are going to be com- bias is up, but well within the pre- planarity and resist technology are fortable at 0.18 microns using con- cision of the data. I think that this formidable, to say nothing of the ventional optical systems. Beyond is truly a spectacular accomplish- requirement that overlay accuracy this level, I do not see any way ment for the industry. Staying on must improve as fast as resolution that conventional optics carries us an exponential like this for 35 if we are really to take maximum any further. Of course, some of us years while the density has advantage of the finer lines. These said this about the one micron increased by several thousand is subjects will all be treated in sev- level. This time, however, I think really something that was hard to eral of the papers at this confer- there are fundamental materials predict with any confidence. ence. But what has come to worry issues that will force a different me most recently is the increasing direction. The people at this con- cost. This is another exponential, ference are going to have to come as shown in Figure 15. up with something new to keep us on the long term trend.

Figure 13 Contribution from increased density from finer line widths over the last 25 years. Figure 15 Increasing cost of lithography tools including extrapolation to Figure 16 Estimated cost of a wafer 0.18 micron minimum dimensions. processing plant and equipment for 5,000 wafer starts per week for vari- When Intel was founded in ous generations of technology. 1968, we set up our manufacturing If one takes the increasing cost facility. A piece of equipment cost of production tools combined with about $12,000. You could buy a the increasing number of layers in Figure 14 Density contribution histor- bank of diffusion furnaces, an advanced technologies, the cost ically and extrapolated based upon evaporator, a lithography exposure for a reasonably balanced produc- the SIA technology road map through machine or whatever for about tion facility (about 5,000 wafers year 2010. that amount. per week) grows as shown in Fig- In a couple of years it is going ure 16. The 0.25 micron plants are I have never been able to see to be $12 million for a produc?tion already being constructed as the beyond the next couple of genera- tool. The equipment tends not to process is being developed. We tions in any detail. Amazingly, process any more wafers per hour have passed the days of mere bil- though, the generations keep com- than they did in 1968 — the wafers lion dollar plants. Current facilities ing one after the other keeping us are bigger, they were two inch under construction will exceed about on the same slope. The cur- then and current eight wafers have two billion and the three billion rent prediction is that this is not sixteen times the area, but that has dollar plant starts construction no going to stop soon either. The cur- not gone up nearly as fast as the later than 1998. The rising cost of rent Semiconductor Industry Asso- cost of the equipment has. This is the newer technologies is of great ciation (SIA) technology road map a really difficult trend to stay on. concern. Capital costs are rising far lays out a path to keep it going My plot goes only to the 0.18 faster than revenue in the industry. well beyond my tenure in the micron generation, because I have We can no longer make up for the industry (Figure 14). While I have no faith that simple extrapolation increasing cost by improving learned not to predict an insur- beyond that relates to reality. yields and equipment utilization. mountable roadblock, staying on These points are not quotes from Like the “cleverness” term in this line clearly gets increasingly equipment vendors, but the best device complexity disappeared difficult. As we go below 0.2 judgment of some of Intel’s lithog- when there was no more room to micron, the SIA road map says 0.18 raphy engineers. Beyond this is be clever, there is little room left in micron line widths is the right really terra incognita, taking the manufacturing efficiency. number, we must use radiation of term from old maps. I have no Increasing the growth rate of the a wavelength that is absorbed by idea what will happen beyond industry looks increasingly unlike- almost everything. Assuming more 0.18 microns. ly. We are becoming a large player

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progress is going to be controlled probably cost quite a bit, maybe from financial realities. We just the equivalent of a few dollars will not be able to go as fast as we today based on the time it proba- would like because we cannot bly took. Today people printing afford it, in spite of your best newspapers sell them for a price technical contributions. When you that makes the individual charac- are looking at new technology, ters about as expensive as are indi- Figure 17 World output of goods and please look at how to make that vidual transistors in a DRAM. Sur- services compared with historic semi- technology affordable as well as prisingly, they sell about as many conductor industry extrapolated into functional. characters as we sell transistors, as the future. Our industry has come a phe- near as I can estimate. Trying to in the world economy. Figure 17 nomenal distance in what histori- estimate the number of characters shows the semiconductor industry cally is a very short time. I think printed is far more challenging compared with the sum of the our progress to a considerable than estimating the number of gross domestic products of the extent is the result of two things: a transistors produced. Taking into countries of the world, the Gross fantastically elastic market with account newspapers, books, the World Product would be an appro- new applications that can consume Xerox copies that clutter up your pri?ate name for it. Obviously this huge amount of electronics, and a desks, all such printed matter I extrapolation has some problems technology that exploits what I estimate that it is no more than an associated with it. have often described as an excep- order of magnitude greater than As you can see, in 1986 the tion to Murphy’s Law. the number of transistors being semiconductor industry represent- By making things smaller, every- produced. ed about 0.1 percent of the GWP. thing gets better simultaneously. Printing in advancing it's tech- Only ten years from now, by about There is little need for trade-offs. nology over the centuries has had 2005, if we stay on the same The speed of our products goes a revolutionary impact on society. growth trend, we will be 1%; and up, the power consumption goes We can now archive our knowl- by about 2025, 10%. We will be down, system reliability, as we put edge and learn from the collected everything by the middle of the more of the system on a chip, wisdom of the past increasing the century. Clearly industry growth improves by leaps and bounds, but rate of progress of mankind. has to roll off. especially the cost of doing thing I think information technology I do not know how much of the electronically drops as a result of will create its own revolution in GWP we can be, but much over the technology. Today one can society over a much shorter time one percent would certainly sur- buy a four megabit DRAM with scale, primarily because of the prise me. I think that the informa- well over four million transistors semiconductor technology you are tion industry is clearly going to be on the chip for less than the planar driving. Semiconductor technology the biggest industry in the world transistor pictured in Figure 3 sold has made its great strides as a over this time period, but the large for in 1960, even neglecting the result of ever increasing complexi- industries of the past, such as auto- change in the value of the dollar. ty of the products produced mobiles, did not approach any- We have made of the order of a exploiting higher and higher densi- thing like a percent of the GWP. ten million fold decrease in the ty to a considerable extent the Our industry growth has to moder- cost of a transistor and thrown in result of progress in lithography. ate relatively soon. We have an all the interconnections free, using As you leave this meeting I inherent conflict here. Costs are the DRAM as an example. It is hard want to encourage each of you to rising exponentially and revenues to find an industry where the cost think smaller. The barriers to stay- cannot grow at a commensurate of their basic product has dropped ing on our exponential are really rate for long. I think that this is at ten million fold even over much formidable, but I continue to be least as big a problem as the tech- longer time periods. amazed that we can either design nological challenge of getting to The only one I can find that is or build the products we are pro- tenth micron. remotely comparable is the print- ducing today. I expect you to con- I am increasingly of the opinion ing industry. Carving a character tinue to amaze me for several that the rate of technological into a stone tablet with a chisel years to come.

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PEOPLE Mishra and Popplewell Receive Predoctoral Fellowships for 2006-2007

hinmaya Mishra of Texas A & M University in Col- responsible for the development of the frequency lege Station, Texas and Peter Popplewell of band plan and the design of frequency synthesizers CCarleton University, Ottawa, Canada have won for multiband OFDM based UWB radios. His pio- the Solid-State Circuits Society Predoctoral Fellowship neering theoretical work on UWB frequency synthe- for 2006 - 2007. They were selected "based upon their sis resulted in a Transactions on Microwave Theory considerable accomplishments to date and their great and Techniques publication which was listed as one promise for future contributions to the field of solid- of the top 100 documents accessed in the entire IEEE state circuits," said Prof. David Hodges of the University in December 2005. of California, Berkeley, Chair of the Award Committee. In the spring of 2005 he was a graduate assistant Inaugurated in 1983 but suspended between 2003 - lecturer in the department of electrical engineering at 2005, the predoctoral fellowship program provides a Texas A&M University and was the instructor for the stipend of $15,000, tuition and fees up to $8,000, and a course ELEN 326 Electronics Circuits. During the sum- grant of $2,000 to the department in which the recipient mer of 2005, he was a RF IC Design Engineer intern is registered. Applicants are required to have completed at WiQuest Communications Inc, Allen, Texas, where one year of graduate study, be in a Ph.D. program in the he worked on the design of a CMOS frequency syn- area of solid-state circuits, and belong to IEEE. thesizer for an ultra-wideband (UWB) radio which resulted in a U.S. patent application. In the fall of Chinmaya Mishra (S’03) received 2005, he was a teaching assistant in the department of the B.E. degree in Electrical and Elec- electrical engineering for two courses, ELEN 665, Inte- tronics Engineering with distinction grated CMOS RF Circuits and ELEN 325, Electronics. from Birla Institute of Technology Since February, 2006 he has been a technical co-op and Science, Pilani, India in 2002 and in the Communications Technology Department of was awarded the Merit Scholarship IBM T. J. Watson Research Center, Yorktown Heights, for being among the top ten of all New York, where he is working on the design of mil- students in the entire University for the class of 2002. limeter wave circuits. His research interests include In the spring of 2002 he was a technical intern in RF, microwave and millimeter wave circuit design on the DSP Design Group at Texas Instruments Inc., silicon and low voltage low power analog circuits. Bangalore, India where he worked on formal verifi- cation of hardware circuits. He received the M.S. Peter H. R. Popplewell (S’98) was degree in Electrical Engineering from Texas A&M Uni- born in Ottawa, Ontario, Canada in versity, College Station in 2004 with a GPR of 4.0. His 1979. He received the B.Eng. degree thesis focused on the design and implementation of in 2002 and the M.A.Sc. degree in 2004, low power multistage amplifiers and high frequency both in electrical engineering from Car- (>10GHz) broadband distributed amplifiers in CMOS. leton University in Ottawa. While an From the fall of 2002 to fall 2004, he was a Texas undergraduate, he was employed by Instruments Research Assistant in the Analog and Nortel Networks’ Long-Haul Optical Networks Group as Mixed Signal Center (AMSC). During this period he part of the team that tested and designed erbium-doped co-developed two novel, power and area efficient fre- and distributed-Raman optical amplifiers. As a Master’s quency compensation schemes for low-voltage multi- student he was a resident researcher at Conexant Systems stage amplifiers driving large capacitive loads. This Inc. and eventually Skyworks Solutions Inc., where he work resulted in a publication in the IEEE Journal of studied the behavior of integrated voltage controlled Solid-State Circuits (JSSC), which was listed as one of oscillators (VCOs) focusing on VCO injection locking. the most read JSSC articles in the first quarter of 2005 This research led him to design, manufacture and test an and one of the top 100 documents accessed in the IC for measuring coupling between on-chip inductors entire IEEE in April 2005. using injection-locked VCOs which doubled as short Since September 2004, he has been working range wireless communication devices. towards his Ph.D. degree at the AMSC under the With the help of fellow Ph.D. researcher Victor supervision of Dr. Edgar Sánchez-Sinencio. From Karam at Carleton University, he recently submitted a spring 2004 to fall 2005 he was part of a team that complete 5.2 GHz transceiver, which uses VCO injec- developed the first multiband UWB receiver system tion locking to achieve very low power consumption, in a package operating from 3-10GHz. He was for fabrication by IBM through MOSIS. The circuit is

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PEOPLE

revolutionary in that it is completely integrated, using Council (NSERC) PGS-D Ph.D. Scholarship and a 2005 on-chip antennas, and is self-powered by a thin film Canadian Wireless Telecommunications Association ultra-capacitor and solar cell which could be stacked (CWTA) Graduate Scholarship. He has published papers on top of the chip. Because the circuit is completely in the proceedings of the IEEE's BCTM, CICC and other integrated, including the antenna and power supply, conferences, and has also been published in the Journal it is ideally suited for applications where low cost is of Solid-State Circuits. A patent for a Lower Power, Inte- essential, such as RFID tags for merchandise. The grated Radio Transmitter and Receiver filed in May is solution is also well suited for use in dosimeters currently under review by The Canadian Patent Office. which measure radiation dosages received by cancer While completing his Ph.D. degree, he continues to patients during treatment. collaborate with Skyworks Solutions Inc. to research Mr. Popplewell has received numerous Canadian very low power and self powered RFIC designs for national awards and scholarships for his research, wireless applications focusing on RFID tags and med- including a Natural Sciences and Engineering Research ical sensors for treating cancer patients. Congratulations New Senior Members

16 Elected in June

Sandeep D'Souza Coastal Los Angeles Section Pamela Kwong Dallas Section Mark Hooper Santa Clara Valley Section Ravindar Lall Oregon Section Daquan Huang Coastal Los Angeles Section Felix Lustenberger Switzerland Section Ulrich Kaiser Germany Section Daniel McMahill Atlanta Section James Kannard Florida West Coast Section Wisik Min Seoul Section Gerhard Knoblinger Austria Section Radivoje Popovic Switzerland Section Elisabeth Koontz Dallas Section David Potter Providence Section Oleh Borys Krutko Fort Worth Section Rajah Vysyaraju Princeton/Central Jersey Section

Tools: How to Write Readable Reports and Winning Proposals

Part I: Grab Your Reader with a PAW

Peter Reimold and Cheryl Reimold

hether your opening is an abstract, an exec- work – the P of your opening PAW. By relating the utive summary, or an unnamed couple of purpose to the readers’ interests, you immediately Wparagraphs, its goal is the same: to give your show them why your report or proposal will be inter- readers the essence of what follows and show them esting to them. why it is important to them. If you do that, you will Let’s take an example of a report. Suppose you are catch their interest and entice them to continue reading. part of a task force to discover how the work people One good success formula is to grab them with a PAW. are doing matches their official job descriptions. Hav- PAW stands for Purpose, Action/Achievement, ing interviewed about one-third of the department What Next. It’s an easy acronym to remember for the employees, members of the task force force agree that beginning of a piece of writing, as it mirrors the open- the project is not working. People don’t want to ing handshake of a conversation. Let's see why it answer the questions. When they do speak, their works. statements match neither their job descriptions nor the work you know they do. The task force has decid- P Stands for Purpose ed to send the department head (who organized this Why did you do the work that is the subject of your report? somewhat inane exercise) a progress report. You What was the problem it intended to solve? The question it have been delegated to write it. hoped to answer? The complaint it set out to resolve? The Your opening should begin with the purpose (the idea it planned to test? The new product it sought to create? P of the PAW): Those questions lead you to the purpose of your The Departmental Task Force was created to deter-

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PEOPLE

mine how the work performed in this department sentences but they give the essence of the report or matches the official descriptions of each job. proposal to follow: If you are writing a proposal, the purpose is usual- The Department Task Force was created to deter- ly even simpler. It is the need of the customer that mine how the work performed in this department you are proposing to solve: matches the official descriptions of each job. Our inter- ABS Food Service requires affordable disposable trays views with one-third of the department members have that will not stick to hot substances place on them. produced inconclusive and conflicting responses. We believe this is because people are unwilling to answer A Stands for Achievement or Action the questions accurately for fear of putting their jobs at Now that your readers know the purpose behind your risk. The Task Force proposes holding a meeting to project or proposal, they are ready for an indication of examine other methods of gathering the information your findings or proposals in service of this purpose. before continuing with this project. For report writers, this means stating what you ABS Food Service requires affordable disposable have accomplished: trays that will not stick to hot substances placed on Our interviews with one-third of the department them. The Careful Chemists Corporation proposes to members have produced inconclusive and conflicting cost the disposal trays with XYZ in a patented two-step responses. We believe this is because people are unwill- method described in this proposal. We would welcome ing to answer the questions accurately for fear of put- the opportunity to present this solution to ABC with ting their jobs at risk. samples of similar products. For proposal writers: What action do you propose Begin by telling your readers what you’re doing, to solve the customer’s need? why it matters, and what should follow it. That pre- The Careful Chemists Corporation proposes to cost the pares both them and you for a report or proposal disposal trays with XYZ in a patented two-step method focused on their interests, not just yours. described in this proposal. Cheryl and Peter Reimold have been teaching W Stands for What’s Next communication skills to engineers, scientists, and In a few lines, you have shown your readers the past (the business people for 20 years. Their latest book, “the purpose of the work) and the present (the achievements Short Road to Great Present ations” (Wiley, 2003), is or results). If that covers the work you are reporting, stop available in bookstores and from Amazon.com. Their there. When it is meaningful and useful, however, com- consulting firm, PERC Communications (+1 914 72 5 plete your opening with a sketch of the future. What do 102 4, [email protected]), offers business consulting you plan to do next, or what do you recommend? and writing services as wellas customized in-house Here are two possible W’s for the report and pro- courses on writing, presentation skills, and on-the- posal openings: job communication skills. Visit their Web site at The Task Force proposes holding a meeting to exam- http://www.allaboutcommunication.com/.” ine other methods of gathering the information before This article is gratefully reprinted with permission continuing with this project. from the authors as well as from IEEE Professional We would welcome the opportunity to present this Communication Society Newsletter editor Rudy Joenk. solution to ABC with samples of similar products. The article is reprinted from the May/June 2002 issue, These two openings each contain only three to four vol. 46, Number 3, pages 10-11.

SSCS Membership Offers More for 2007

Three Great Improvements down from the 2006 price of are black out days at the IEEE SSCS membership will include $150. membership site. No additions to three great improvements for 2007: The $20 membership fee contin- your membership will be available • online access to all SSCS spon- ues to include Xplore access to all while the 2007 renewal informa- sored conference articles in 51 years of the JSSC. tion is in preparation. Xplore More information for student • an SSCS Quarterly News publica- Renew On-Line in October members, who must renew or add tion mailed to all members Wait for your email notice this fall new services (join IEEE societies or • the Solid-State Circuits Digital to renew on-line at the IEEE add publication subscriptions) Archive 2-DVD set, offered at a Renew Membership webpage. The online is available on the IEEE Stu- reduced member price of $40, end of August and early September dent Concourse.

September 2006 IEEE SSCS NEWSLETTER 45 sscs_NL0906r1 8/16/06 9:55 AM Page 46

CHAPTERS

Serbia and Montenegro ED/SSC Chapter Promotes EE as a Career Sponsors Miel 2006 Drawing Attendees from 32 Countries

Ninoslav Stojadinovic, Chapter Chair, [email protected]

he first activity of the Serbia great inventor Nikola Tesla in Bel- and Montenegro ED/SSC grade. In addition to university stu- TChapter in 2006 was the dents, the participants of this trip annual chapter meeting, held in were ten female students coming mid-January at the Faculty of Elec- from five different high schools. tronic Engineering, University of The chapter subsidized the trip of Nis. The Chapter Chair, Prof. the high school students and Stu- Ninoslav Stojadinovic, presented a dent Chapter members, while report on chapter activities in other interested students fully par- 2005 and a plan for 2006, both of ticipated in covering the expenses. which were supported and adopt- It should be noted that involve- ed. His report was followed by ment of young women in this and the traditional promotion of new some other chapter activities falls members and by the also tradi- under the IEEE STAR Program. The tion with Faculty of Electronic tional cocktail party. STAR Program is aimed at increas- Engineering (University of Nis), Ei- ing the number of women pursu- Holding Co., and national Society IEEE Campaign in Collabo- ing careers in electrical engineer- for ETRAN. But it is very important ration with University of Nis ing, and its development has been to say that the conference was ED/SSC Student Branch one of our chapter’s important organized under the co-sponsor- Chapter activities for several years. ship of the IEEE Electron Devices This chapter meeting was only an The IEEE campaign ended in Society, with cooperation of the introduction to several important April with a new presentation on IEEE Solid-State Circuits Society, chapter activities conducted in col- IEEE mission, goals, and benefits, and under the auspices of the Ser- laboration with the University of which also was given by Prof. Sto- bian Ministry of Science and Envi- Nis ED/SSC Student Branch Chap- jadinovic. His talk was followed by ronment Protection, Serbian Acad- ter in February and March, aimed the presentation of a videotape emy of Science and Arts, Academy at promoting the IEEE among the “Getting Ready: Careers for Electri- of Engineering Sciences of Serbia students and increasing the interest cal Engineering and Computer Sci- and Montenegro, and City Assem- of young scholars, especially entist,” from the EDS Video Tape bly of Nis. female ones, in electrical engineer- Lending Library. A number of high The Conference Workshop on ing studies. school students were among the Nanotechnologies on 14 May Several chapter members among attendees, which hopefully means included nine keynote invited talks the teaching staff at the Faculty of that our efforts on increasing the Electronic Engineering were interest of young scholars in pur- involved in the campaign promot- suing the careers in engineering ing the IEEE. A part of this cam- disciplines have been fruitful. paign was a presentation of IEEE benefits, given in the main lecture Nine Keynote Talks on Nan- hall by Prof. Ninoslav Stojadinovic otechnologies at MIEL 2006 and Mr. Danijel Dankovic, Univer- The most important activity of the sity of Nis ED/SSC Student Branch Serbia and Montenegro ED/SSC Chapter Chair. Chapter in 2006 was organizing the 25th International Conference on Some of Serbia and Montenegro IEEE STAR Program Promotes Microelectronics (MIEL 2006), ED/SSC Chapter members involved in organization of MIEL 2006 Confer- Women in Engineering which was held on 14-17 May in ence. From left: Tatjana Pesic, Biljana The two chapters organized a tra- Belgrade. The Chapter organized Pesic, Ivica Manic, Aneta Prijic, and ditional visit to the museum of the MIEL 2006 Conference in coopera- Danijel Dankovic.

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Professor N. Stojadinovic addressing Some of MIEL 2006 distinguished Serbia & Montenegro ED/SSC Chapter the audience at MIEL 2006 Opening attendees. From left: Prof. Cor Claeys, members Danijel Dankovic (left) and Session. his wife Mrs. Rita Rooyackers, Prof. Vojkan Davidovic preparing to run the Ninoslav Stojadinovic (Conference presentations at one of MIEL 2006 Chairman), Prof. Magali Estrada, and Conference sessions. Prof. Antonio Cerdeira.

given by leading experts in the 753 pages) were published vier Science gave an award to the field, which attracted a lot of inter- through the IEEE Book Broker paper “Long Range Statistical Life- ested attendees. The Workshop Program. time Prediction of Ultra-Thin SiO2 was an excellent introduction to Serbia & Montenegro ED/SSC Oxides: Influence of Accelerated the main technical program, which Chapter members Danijel Dankovic Ageing Methods and Extrapolation consisted of two plenary sessions, (left) and Vojkan Davidovic prepar- Models” presented by D. Pic (STMi- each with two keynote invited ing to run the presentations at one croelectronics, Rousset, France). talks, and nine regular sessions on of MIEL 2006 Conference sessions. This award was establsihed by Prof. specific topics: Power Devices and Stojadinovic, Editor-in-Chief of the ICs, Nanotechnologies, Microsys- Best Paper Awards journal. tem Technologies, Opto and Based on the quality of the papers Among the best traditions of Microwave Devices, Processes and and presentations, three Best MIEL, the social program of this Technologies, Physics and Model- Paper Awards were presented to year’s conference issue was par- ing, Modeling and Simulation, Reli- • K. Arshak (University of Lim- ticularly rich, with a conference ability Physics, and Circuit and Sys- erick, Ireland) for a confer- banquet and gala-dinner as tem Design. ence session paper “Investi- highlights. The conference attendees, 42 gation of Electrode Patterns Besides the high quality of pre- domestic and 88 foreign, came Suitable for Nano-Litre Drop sentations, MIEL is generally fla- from 32 countries all over the Coated Conducting Polymer vored by a friendly atmosphere world (Australia, Austria, Bahrain, Composite Sensors.” and great hospitality of our chapter Belgium, Bulgaria, Canada, Czech • Z. Jaksic (IHTM-CMTM, Bel- members involved in organization, Republic, Estonia, Finland, France, grade, Serbia) for a poster as well as other local people. This Germany, Greece, Hong Kong - paper “A Consideration of special charm adds to very positive China, India, Ireland, Italy, Japan, Transparent Metal Structures impressions the participants bring Korea, Macedonia, Mexico, for Subwavelength Diffraction from the conference, and is one of Poland, Romania, Russia, Serbia Management.” the reasons why one rarely attends and Montenegro, Slovakia, Spain, • U. Abelein (University of MIEL just once: one who comes Sweden, Taiwan, The Netherlands, Bundeswehr Munich, Neu- will almost certainly come again. Ukraine, United Kingdom, and biberg, Germany) for a stu- So, we are very much looking for- USA). A total of 23 keynote invited dent paper “A Novel Vertical ward to welcoming old and new papers and 118 regular contribu- Impact Ionisation MOSFET (I- friends at MIEL 2008. tions (70 in oral sessions and 48 MOS) Concept.” More information about MIEL is posters) were presented. The con- In addition, the Microelectronics available at: europa.elfak.ni.ac.yu ference proceedings (two volumes, Reliability journal published by Else- /miel. E-mail: [email protected].

September 2006 IEEE SSCS NEWSLETTER 47 sscs_NL0906r1 8/16/06 9:56 AM Page 48

CHAPTERS SSCS Taipei a Key Player in the Asian IC Community

Prof. Tsung-Hsien Lin, National Taiwan University, [email protected]

he SSCS Taipei Chapter has witnessed and contributed to Tthe extraordinary growth of the Asian IC design community over much of the last decade. The main mission of the Taipei Chapter, founded in 1998, is to serve the IC design community and promote solid-state circuit design excellence in Taiwan. To accomplish this goal, the Chapter frequently organizes and sponsors various activities such as short courses, tutorials, workshops, conferences, and student IC design ISSCC rehearsal meeting, January, 2006. contests. tional Symposium on VLSI-TSA- in Taiwan. In this contest, graduate Inaugural A-SSCC in Taiwan DAT, which is held in Taiwan and undergraduate students can In Nov. 2005, the SSCS-endorsed annually. On the domestic side, form a two-person team and com- Asian Solid-State Circuit Conference the Chapter is actively involved in pete in several design categories. (A-SSCC) was successfully held in the VLSI Design/CAD Symposium, Teams are required to complete a Hsinchu, Taiwan. Many Chapter which is held during the summer hardware implementation or cir- members were involved in organiz- each year and has become a major cuit design task within a 12-hour ing this event, which drew more than island-wide technical event. The period and satisfy certain design 340 attendees in its first appearance. number of symposium participants requirements. Students must be This year, the conference will take has grown to near 1000 in 2005. familiar with the design flow, EDA place in Hangzhou, China. To The large number of attendees tools, circuit design techniques, encourage students’ participation, the attests to the vibrant IC design and most important of all, how to Taipei Chapter plans to provide par- society in Taiwan. The annual work as a team to get the job tial travel compensation to reward SSCS Taipei Chapter member done. The number of teams students who will present their meeting is also held during the entered in the contest has grown accepted papers at the conference. symposium. to over 500 in 2005. A detailed description of this event can be ISSCC Rehearsals found in the Jan. 2006 issue of the In addition to providing support, Taiwan IC Student Design SSCS Newsletter. the Taipei Chapter is also committed Contest to promote technical presentation To promote students’ interests and Short Courses quality. Starting from 2005, a formal involvement in the IC design, the Among all our activities, short rehearsal meeting was arranged by Taipei Chapter co-sponsors the courses and tutorials are very the Chapter shortly before ISSCC. domestic student IC design contest popular among students and engi- For the papers accepted by ISSCC from Taiwan, the designated speakers were invited to the rehearsal meeting and polished their presentations in front of a selected audience. In 2006, 18 presentations were rehearsed at his meeting.

Annual VLSI-TSA-DAT The Taipei Chapter also co-sponsors and hosts the IEEE Interna- IEEE SSCS Taipei annual chapter meeting, August, 2005.

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National Taiwan University and met with students. One of the books co-authored by Prof. Smith was adopted as the textbook and used by many students in Taiwan. This rare opportunity to meet and interact with Prof. Smith has brought a great inspiration to the students. All these event announcements are posted in a concise yet informative Chapter webpage (http://www2.ee.ntu.edu.tw/~sscs /). In addition, an email broad- casting system is also established to inform the members and other interested parties about the upcoming activities. The webpage also includes membership applications and other useful links. Recognized for its efforts in pro- Short course by Dr. Hooman Darabi (center), August, 2005. moting solid-state circuit designs and services to the IC design community, the Taipei Chapter was awarded the Outstanding SSCS Chapter in 2002. Based on its past successful experience and operation, the Taipei Chapter will keep the good tradition to bring more value to our members and continue to make contributions to the society.

About the Author Prof. Tsung-Hsien Lin (S’97–M’01) received Prof. K. C. Smith meeting with students at National Taiwan University, Decem- the B.S. degree in ber, 2005. electronics engineer- neers. Each year, the Chapter technical knowledge within a lim- ing from National organizes and hosts several two- ited amount of time. In addition, Chiao Tung Universi- day short courses. The topics of by inviting these international ty in 1991, and M.S. these short courses are selected to guests to visit Taiwan, they have a and Ph.D. degrees in electrical engi- address both industrial and acade- better opportunity to connect with neering from UCLA in 1997 and mia interests. For instance, the the local IC design community. 2001, respectively. From March 2000 three short courses held over the Some forms of collaboration with to 2004, he was with Broadcom past 12 months were on the topic local companies or research insti- Corporation as a Senior Staff Scien- of wireless transceiver design, tutes may be established out of tist. While at Broadcom, he was high-speed link design, and these contacts. involved in analog/RF/mixed-signal power management IC design. In addition to the above events, IC designs for various wireless appli- The invited speakers are world the Taipei Chapter also frequently cations. He joined the Graduate renowned experts, and they organizes and cosponsors semi- Institute of Electronics Engineering brought with them years of nars, short talks, and forums. One and Department of Electrical Engi- advanced research/industrial event worth mentioning in particu- neering, National Taiwan University experiences and practical know- lar was Prof. K. C. Smith’s visit in in February, 2004. His research inter- how. These short courses were Dec. 2005. While on a trip to Tai- ests Include wireless communication well-received by the attendees, wan for the 2006 ISSCC press con- circuit and transducer interface cir- for they acquired well-structured ference, Prof. Smith also visited cuit designs.

September 2006 IEEE SSCS NEWSLETTER 49 sscs_NL0906r1 8/16/06 9:56 AM Page 50

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SSCS Subsidizes Short Course on Linear Regulator Design in Taipei

IEEE SSCS Taipei Chapter

SCS chapters are eligible for It was presented in Hsinchu and LDO circuit design in great detail. In extra subsidies to support Taipei on 8 and 9 June, 2006, the last part of his lecture, Prof. Sevents such as workshops respectively. There were approxi- Rincón-Mora shared his views and mini-conferences that are not mately 70 participants at the on future research directions of financed by the annual Chapter Hsinchu lecture, and 40 at the lec- power management system with Subsidy. ture at National Taiwan University, the audiences. With the help of an SSCS extra Taipei. The majority of attendees Prof. Rincón-Mora, who has subsidy, the Taipei Chapter organ- were IC design engineers. This years of practical IC development ized a two-day short course on the reflects the fact that many IC and research experiences in both subject of power management IC design companies in Taiwan are industry and academia, brought a design in light of the increasing pursuing the power management good mix of design knowledge to importance and diverse applica- IC market. the lectures. His short course was tion of power management sys- The course began with an well-received by the attendees, tems. The invited speaker was overview of power management and many considered the course Prof. Gabriel A. Rincón-Mora of systems and a brief introduction to content a great value to their the School of Electrical and Com- the design requirements. Prof. research and work. puter Engineering, Georgia Insti- Rincón Mora then went on to con- The Taipei Chapter greatly tute of Technology, whose course centrate on low dropout regulator appreciates the financial support was entitled “Linear Regulators: (LDO) design, describing the design from the IEEE Solid-State Circuits From the Ground Up ….” methodology and presenting the Society in organizing this event.

Photo taken after the lecture by Prof. Gabriel Rincón-Mora in National Taiwan University, Taipei on 8 June, 2006. From left to right (front row): Prof. Tsung-Hsien Lin, Prof. Shen-Iuan Liu (Taipei Chapter Chair), Prof. Gabriel Rincón-Mora, Prof. Yi-Jan Chen, and Prof. Chorng-Sii Hwang.

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Challenges for THE e-life at 2nd A-SSCC

13-15 November 2006, Hangzhou, China

Takayasu Sakurai, A-SSCC 2006 Steering Committee member, [email protected]

his year, the Asian Solid-State consumer applications. Design Circuits Conference will be challenges are reviewed and Theld from 13-15 November in explored from submicron to Hangzhou, China at the Hyatt nanometer eras in multiple levels Regency Hangzhou on the lakeside of technology developments. of the beautiful West Lake. This is Tutorials on 13 November cover the second A-SSCC fully sponsored advanced embedded SRAM design, by the IEEE SSCS. Chang, CEO of SMIC (China). advanced PLL design, advanced The uniqueness of A-SSCC Dr. Soo-Young Oh, VP of ETRI pipeline ADC design and among other first-class internation- (Korea) will also speak on 14 advanced sigma-delta ADC design. al conferences is that it is held November about "Component Two panel discussions on high- every year in rapidly-growing Asia, Technologies needed by the Ubiq- speed wireline communications providing opportunities for uitous IT Society." Korea devel- and software radio are also exchanging information and ideas oped infrastructures for mobile TV planned on 14 November. in the circuit design field. A- service and Wibro which can pro- Other than the ordinary confer- SSCC'06 is the first IEEE SSCS vide the 2 ~ 10 Mbps mobile inter- ence events such as plenary talks, sponsoring conference which is net service at the speed of 60 ~ 120 panel discussions, tutorials, normal held in mainland China. The con- Km/h and the cost of $20 ~ 30 per technical papers, the A-SSCC'06 ference theme this year is "Chal- month. This presentation covers will hold a very unique event lenges for THE e-life". the Korea IT development strategy, called an Industry Program where The A-SSCC'06 received 327 its results, and the components attendees can share an industry paper submissions from which technologies needed by the future trend and information on cutting- about 100 papers will be selected ubiquitous IT society. edge product chips through demos for presentation. Thus, the paper Dr. Tohru Furuyama, GM of and evaluation results. The Indus- quality is expected to be very high. Toshiba (Japan), will talk on "Deep try Program is held on Nov. 14. The detailed paper submission dis- Sub-100 nm Design Challenges" on Posters presentations are quitted tribution is: Belgium 3, Canada 4, 15 November. The deep sub-100 this year but instead, the student China 129, Finland 1, France 1, nm design challenges and several design contest program is planning India 6, Iran 9, Japan 38, Korea 32, approaches to counteract these new sessions with demos by stu- Philippines 2, Singapore 7, Spain 1, problems will be described in this dents lead by Prof. H.J.Yoo. Sweden 2, Switzerland 1, Taiwan presentation, such as various low As to the collaboration with the 68, U.S.A. 23. As you can see, sub- power technologies and high-level journal and the other conference, missions from China are dominant language and platform based some of the technical papers will this year. The TPC consists of a design flow. be printed in a special edition of balanced mix of both of industry Mr. Ming-Kai Tsai, CEO of Medi- JSSC after being reviewed, and the and academia, and as a result, the aTek (Taiwan), will give a talk best three Student Design Contest technical program will cover entitled "From PC Multimedia papers will be presented at the papers that interest people from Chipsets to Wireless and Digital forthcoming ISSCC and awarded both industry and academia. Consumer SoC: Evolution and with an ISSCC scholarship of US Representatives from four major Challenges" on 15 November. $500 each. semiconductor forces in Asia will Starting with the evolution of opti- For more detailed information, be delivering important messages cal-storage chipsets for PC multi- please visit the following website: as plenary talks. The plenary media, this presentation moves www.a-sscc.org/ speeches will start on 14 Novem- towards full-blown, next-genera- Hope to see you in the midst of ber with a talk by Dr. Richard tion SoCs for wireless and digital booming China.

September 2006 IEEE SSCS NEWSLETTER 51 sscs_NL0906r1 8/16/06 9:56 AM Page 52

CONFERENCES Van der Spiegel will Speak at IBERSENOR 2006

SSCS Uruguay Chapter Organizes 5th Ibero-American Congress, 26-29 September in Montevideo, Uruguay

an Van der Spiegel, Professor in 1998, in Buenos Aires, Argentina of Electrical Engineering at the in 2000, in Lima, Peru in 2002, and JUniversity of Pennsylvania in Puebla, Mexico in 2004. and SSCS Chapters Committee Research groups in Argentina, Chair, will present a DL talk at the Brazil, Chile, Colombia, Cuba, 5th Ibero-American Congress on Spain, Mexico, Peru, Portugal, Sensors and Biosensors (IBERSEN- Puerto Rico, USA and Uruguay are SOR 2006), 26-29 September in Mon- active participants in this initiative. tevideo, Uruguay. The event is being Its goal is the integration of further organized by the SSCS Uruguay research groups from all countries chapter chaired by Enrique D. Fer- of the region, as well as the spon- reira. Beforehand, Prof. Van der sorship of new research groups Spiegel will travel to Brazil to present and tuition assistance in the field. a lecture and promote the formation Steady progress and the growth of a SSCS Chapter in Sao Paulo. of IBERSENSOR meetings undoubt- edly has corroborated the potential Abstract: Biologically both detectors and local signal of our community countries in this Inspired Optical Vision Sensors processing elements. Examples of field, which nowadays constitute This presentation deals with optical CMOS-based vision sensors with one of the most significant and fast sensors that are architecturally on-chip contrast, edge, motion, developing branches of the scientif- inspired by biological systems. A orientation, and polarization detec- ic and technical tasks worldwide. brief overview of the underlying bio- tion capabilities will be discussed. This year’s program includes logical mechanisms found in senso- Held biannually, IBERSENSOR is short courses, keynote talks, oral ry systems will be discussed, as well a forum of the Spanish and Por- and poster sessions, and bi- and as signal processing strategies and tuguese speaking scientific com- multilateral cooperation meetings. sensory circuits, with special atten- munity, working in the fields of The Chair is Prof. Maria Simon, for- tion given to visual systems. development of sensors of every mer Dean of the Faculty of Engi- The talk will describe how these kind and their applications. The neering, University of the Republic, properties can be used to design IBERSENSOR conference has who is President of ANTel, a state- and build neuromorphic vision already been successfully held on owned telecommunications com- sensors with pixels that contain four occasions: in Havanna, Cuba pany, the biggest in the country. ICCAD 2006 will Focus on Current Applications and Challenges Faced by Future Technologies More than 750 Expected at Meeting on 5-9 November in San Jose Soha Hassoun, ICCAD 2006 General Chair , [email protected]; Georges Gielen, ICCAD 2006 Program Chair, [email protected]

rom November 5-9 in San ability, as well as the challenges of Jose, California the Interna- future technologies, both CMOS and Ftional Conference on Comput- beyond. er Aided Design (ICCAD) will again provide attendees the rich and high- Focus Expanded to quality technical content in design Emerging Technologies technology that they have come to ICCAD recently expanded its focus expect. The Conference will focus to include emerging technologies on the pressing problems of today's such as carbon nanotubes, molecu- IC designs such as power and vari- lar transistors, spin-based and sin-

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gle electron devices, DNA-based this year with the physical design computing, electro-chemical com- sessions on placement, routing and ponents, MEMS, and the integration interconnect, which are traditional- in sensor systems and biochips. ly strong in content. The latest At this year’s show, attendees results in other fields, such as test from around the globe will find of and analog CAD, will also be pre- particular interest the focus on sented. Also continued from last design problems in current applica- year is the full-day track focused Phil Hester Leon Stok tions, such as power and variability, on design and applications in and the topic of challenges in emerg- ded tutorials and two keynote emerging nano technologies. ing technologies, such as the impact addresses from Phil Hester, Chief The physical design program of new devices and materials. Both Technology Officer of AMD; and has two embedded tutorials pre- professionals and researchers active Leon Stok, Director of CAD at IBM. sented by renowned experts in in EDA, as well as practicing design- the field, and two regular paper ers, will benefit from this knowledge, 5-Day Track on Issues in sessions, and takes place on which is provided in regular paper System Design Wednesday. Other embedded tuto- sessions and in tutorials embedded Particularly noteworthy this year is rials will focus on the challenges within the conference program. the technical track on system design that designers face in the industry issues, which runs the entire length today or will encounter in the very Technical Program of the conference and covers issues near future. These include the The program begins on Sunday, 5 on power and performance opti- impact of new materials used in November, with a workshop on mization at the system-level, thermal CMOS technology, the mitigation the convergence between technol- and variability issues in architec- of DRC rule complexity, and the ogy and design, and concludes on tures, and energy minimization in challenges of mixed-signal design. Thursday, 9 November, with six real-time embedded systems, to Because of the rich technical high-caliber, half-day tutorials. name a few. The system theme is and practical content of ICCAD, The technical program from completed with two tutorials the conference is able to draw Monday – Wednesday includes 130 embedded within the system design attendees from around the globe. papers that were selected accord- track: Challenges in Designing and With more than 750 attendees ing to the rigorous standards of the Mapping Algorithms to Multi-Core expected to attend this year’s con- International Technical Program Systems, and the second on The ference, designers, design technol- Committee. Popular topics this year Use of UML Versus SystemC in the ogy professionals, and academics are low-power techniques, variabil- Design of Systems. should find ICCAD the world’s ity, and architectural design. leading forum for the discussion of In addition to these regular Traditional Sessions on new EDA technology. papers, the technical program also Physical Design The conference website is: contains two panels, seven embed- A classic at ICCAD will continue http://www.iccad.com/.

CSIC Symposium Meets in San Antonio, 12-15 November, 2006 Mohammad Madihian, Executive Committee Technical Program Chair, [email protected]

e cordially invite you to the preeminent international forum in the 2006 Compound Semi- which advances in semiconductor Wconductor IC Symposium circuit and device technology are pre- being held 12-15 November in beau- sented, debated, and discussed. The tiful, historic San Antonio, Texas. The scope of the Symposium encompass- high-performance wireless and high- es devices and circuits in GaAs, SiGe, speed digital communications mar- InP, GaN, and InSb, as well as ses- kets are thriving due to impressive sions targeting the fields of RF CMOS strides in new materials and devices, and high-speed digital CMOS, to pro- greater integration levels, novel cir- vide a truly comprehensive confer- cuit implementations, and ever- conductor IC Symposium (CSICS – ence. This is the ideal forum for pres- changing systems partitions. Over the formerly named the GaAs IC Sympo- entation of the latest results in high- last 28 years, the Compound Semi- sium) has been and continues to be speed digital, analog, microwave/mil-

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limeter wave, mixed mode, and plays with corporate representa- the “River Walk,” these cobblestone optoelectronic integrated circuits. tives on hand. The list of exhibitors and flagstone paths border both sides This year’s 2006 CSIC symposium can be found in the CSICS advance of the San Antonio River as it winds will be co-located with the Key Con- program which was published and its way through the middle of the ference. The co-location is referred to distributed in late June. business district. The River Walk is as Compound Semiconductor Week To complement the Symposium, quiet and park-like in some stretches, and is comprised of two short cours- there are several social events, while other areas are full of activity es and a primer course, a full three- including the Sunday Evening CSICS with European-style sidewalk cafes day technical program, and a joint Opening Reception, the Monday and specialty shops. The River Walk technology exhibition. The technical CS-Week Exhibition Opening stretches for approximately two-and- program consists of 58 high quality, Reception, the CS-Week Tuesday a-half miles from the Municipal Audi- state-of-the-art technical papers, four evening Theme Party to be held at torium and Conference Center on the panel sessions, two Short Courses on the Rio Cibolo Ranch providing an north end to the King William His- “GaN Circuits and Applications” and authentic and memorable Texas toric District on the south. Rio San “RF and High Speed CMOS”, and an experience, and the CS-Week Exhi- Antonio Cruises, the river's floating Industry Exhibit. The Symposium will bition Luncheon on Tuesday. Addi- transportation system, provides a also be offering the popular annual tionally, breakfast will be served on novel method of sightseeing and introductory level Primer Course on Monday, Tuesday and Wednesday. people-watching in downtown San “Basics of Compound Semiconductor The 2006 CSICS will be held in San Antonio. Groups can also dine ICs”. This year the Symposium will Antonio, Texas in the Marriott River- aboard open-air cruisers as they wind feature 16 invited papers on a wide walk Hotel located in downtown San their way along the scenic waterway. range of important topics encom- Antonio. Now the eighth largest city For registration, paper submis- passing device engineering to circuit in the United States, the city has sions, call for papers, advance pro- application using advanced com- retained its sense of history and tradi- gram, and further information please pound and other related semicon- tion, while carefully blending in cos- visit the CSICS website at ductor technologies. In addition, the mopolitan progress. Close to twenty http://www.csics.org/. Further ques- Symposium will continue the tradi- million visitors each year delight in tions on abstract submission may be tion of including important “late the discovery of San Antonio's addressed to the Symposium Tech- breaking news” papers. charms. Amidst the daily hubbub of nical Program Chair: Mohammad The joint technology exhibition the busy metropolitan downtown, Madihian, Ph: +1-609-951-2916, will be held on Monday and Tues- sequestered 20 feet below street Email: [email protected] day. The exhibition will feature level, lies one of San Antonio's jewels We hope you can attend, informative and interesting dis- - the Paseo del Rio. Better known as IEEE CSIC Organizing Committee.

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SSCS EVENTS CALENDAR Also posted on www.sscs.org/meetings SSCS SPONSORED MEETINGS Kyoto, Japan 2006 International Conference on 2006 (CICC) Custom Integrated Paper deadline: 5 January 2007 Computer Aided Design Circuits Conference Contact: Phyllis Mahoney, www.iccad.com/future.html www.ieee-cicc.org [email protected] 5–9 November, 2006 10–13 September, 2006 or Business Center for Academic Societies, San Jose, CA, USA San Jose, CA, USA Japan, [email protected] Paper deadline: passed Paper deadline: passed Contact: Melissa Widerkehr, [email protected] SSCS PROVIDES TECHNICAL 2006 Compound Semiconductor IC CO-SPONSORSHIP Conference 2006 (A-SSCC) Asia Solid-State 2006 European Solid-State Circuits www.csics.org/ Circuits Conference Conference 12 – 15 November, 2006 www.a-sscc.org www.esscirc2006.org/ San Antonio TX 13–15 November, 2006 18–22 September, 2006 Paper deadline: 15 May 2006 Hangzhou, Zhejiang Province, China Montreux, Switzerland Paper deadline: 5 June 2006 Paper deadline: passed 2007 International Conference on VLSI Contact: [email protected] Design 2006 International Symposium on www.vlsiconference.com/ 2007 (ISSCC) International Solid-State Low-Power Electronic Devices 3–7 January, 2007 Circuits Conference www.islped.org Bangalore, India www.isscc.org 4–6 October, 2006 Paper deadline: TBD 11– 15 February, 2006 Tegernsee, Germany San Francisco Marriott Hotel, Paper deadline: passed 2007 Design, Automation and San Francisco, CA, USA Test in Europe Paper deadline: 15 September 2006 2006 Bipolar/BiCMOS Circuits and www.date-conference.com/conference/next.htm Contact: Courtesy Associates, ISSCC@cour- Technology Meeting 16–20 April, 2007 tesyassoc.com www.ieee-bctm.org Acropolis, Nice, France 9–10 October, 2006 Paper deadline: TBD 2007 Symposium on VLSI Circuits Maastricht, Netherlands www.vlsisymposium.org Paper deadline: passed 14–16 June 2007

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