Electronic Properties of Monolayer Tungsten Disulfide Grown by Chemical Vapor Deposition

Supplementary Information

Electronic properties of monolayer tungsten disulfide grown by chemical vapor deposition

Abdullah Alharbi, Davood Shahrjerdi

Electrical and Computer Engineering, New York University, Brooklyn, NY 11201

Material synthesis: Figure S1 illustrates the schematic of our custom-made CVD setup.

During the growth, the SiO2/Si substrate was placed faced-down on the WO3 crucible, while the S powder was placed in a separate crucible in the upstream region of the quartz tube. The growth was performed at atmospheric pressure at 950°C for 3min. The WO3

(20mg) powder was placed in alumina boat at the center of the furnace inside a 1-inch diameter quartz tube and the temperature was raised to 950°C at 50°C/min and was held for 3 min. The furnace was then turned off and cooled in air. The Si substrates capped with SiO2 were placed face down on the alumina boat containing WO3. The S (100mg) powder was placed in a separate crucible and located in the front of the furnace and heated separately to 150 °C using a heating tape. The S vapor was carried using 10sccm of nitrogen to the reaction zone.

Fig. S1: Schematic illustration of our CVD setup.

Fig. S2a shows the optical image of large monolayer WS2 flakes. Atomic force microscopy (AFM) image of a monolayer flake is shown in Fig. S2b. The AFM step height at the edge of the flake is ~0.8nm. Raman spectroscopy and photoluminescence

(PL) measurements further confirm the monolayer growth of WS2 flakes, shown in Fig.

S2c, and S2d. Raman and high-resolution PL maps were acquired using Horiba XploRA confocal Raman microscope with 532nm excitation laser.

Fig. S2: (a) Optical image of monolayer CVD WS2. (Scale bar 50µm). (b) AFM step height measurements reveal the monolayer growth (Scale bar 10µm). (c) Raman and (d) PL spectra of a monolayer CVD WS2 flake.

The Hall bar device active regions were defined using electron beam lithography (EBL) followed by patterning in CF4/O2 plasma. The source/drain contacts were defined using

EBL, electron beam evaporation of 10/40nm Ti/Au, and lift-off. The high-k dielectric was deposited at 200°C using water and tetrakis (dimethylamido) hafnium (Hf(NMe2)4) precursors. The local metal gate was made through EBL, Cr/Au (5nm/40nm) deposition, and lift-off.

Fig. S3: (a) The map of PL peak intensity illustrating the bright and dim regions. (b) Normalized PL peak intensities corresponding to the highlighted points in (a).

Figure S3 shows the map of the PL peak intensity and the corresponding normalized PL peak spectra. It is evident from the data that the PL peak energies exhibit red shift in the dim region relative to the bright region. Further, the PL peaks in the dim region are boarder than those in the bright regions, suggesting the presence of additional excitonic states in the dim regions.

To determine the Schottky barrier at the source and drain contacts, we adopted the method described in ref. 30. We measured the transfer characteristics of the devices in the

3 bright and dim regions at different temperatures. The data was then plotted in the form of

2 Ln (Id/T ) as a function of 1/T for different gate voltages, where Id and T are the device drain current and temperature, shown in Fig. S4a and S4b. The effective Shottkey barrier was extracted from the slope of the curves in these plots and subsequently plotted as a function of the gate voltage (FigS4c). The true Schottky barrier occurs at the flat-band voltage. This corresponds to the gate voltage, at which the data begins to deviate from a linear relation. The true Schottky barrier of the device in the dim region is ~80meV.

Fig. S4: Arrhenius plots constructed from the temperature-dependent transfer characteristics of two devices located in (a) the bright region and (b) the dim region of the same flake. (c) The plot of the effective Schottky barrier height as a function of the gate voltage for the device in the dim region. The devices in the dim region typically exhibit larger Schottky barrier than those in the bright regions.

In order to determine the density of localized gap states and their corresponding time constants, we used the equivalent device model in Figure 3b. This model assumes two

4 types of trap states in the bandgap: mid-gap and band-edge states. The calculations below were used for extracting the density of trap states and their time constants from the series measured model consisting of the capacitance and resistance of Cs and Rs. In our calculations, CitM and CitB denote the interface trap capacitances at the mid-gap and the band-edge, while τitM and τitB correspond their time constants. The semiconductor capacitance was estimated by the quantum capacitance Cq in the inversion regime. The oxide capacitance Cox was determined from the capacitance-voltage curves.

��!"# = �!"# 1 + ��!"#

�!"# = ��!"# & �!"# = ��!"#

�!"# �!"# = �!"#

�!"# �!"# �!"#"$$%$ = �� + + �! = �!"# + �!"# + ��! 1 + ��!"# 1 + ��!"#

! �!"# + ��!"#�!"# + �!"# + ��!"#�!"# + �!(1 − � �!"#�!"# + ��(�!"# + �!"#)) = �� ! 1 − � �!"#�!"# + ��(�!"# + �!"#)

! (�!"# + �!"# + �!) − �!� �!"#�!"# + ��(�!"#�!"# + �!"#�!"# + �!(�!"# + �!"!)) = �� ! (1 − � �!"#�!"#) + ��(�!"# + �!"#)

!! 1 1 �!"!#$ = + �!"#"$$%$ ��!" ! 1 (1 − � �!"#�!"#) + ��(�!"# + �!"#) = ! �� (�!"# + �!"# + �!) − �!� �!"#�!"# + ��(�!"#�!"# + �!"#�!"# + �!(�!"# + �!"#)) 1 + ��!"

! � = (1 − � �!"#�!"#)

� = ��(�!"# + �!"#)

! � = (�!"# + �!"# + �!) − �!� �!"#�!"#

� = (�!"#�!"# + �!"#�!"# + �!(�!"# + �!"#))

!! 1 � + �� − �� 1 �� + �� (�� − �� 1 �!"!##$ = . = ! ! . ! ! + �� + �� − �� + � � + � ��!"

!! 1 �� + �� 1 ��(�!"!#$ ) = ! ! + �� + � ��!"

!! 1 1 �� + �� 1 1 ��(�!"!#$ ) = ! ! + = ��! �� + � ��!" ��!

!! 1 �� + �� 1 �� + �� 1 = ! ! + �! = ! ! + �! � + � �!" � + � �!"

A parallel circuit model was also derived from the measured series model shown in Fig.

S5. The parallel model was used for ac conductance calculations, described in the manuscript.

Fig. S5: Schematic illustrations of the measured series model and the calculated parallel model.

The output characteristics of the FETs begin to show Schottky behavior as the temperature is reduced. Fig. S6 illustrates the output characteristics of the device in

Figure 2, measured at lower temperatures.

Fig. S6: The Output characteristics begin to exhibit Schottky behavior at low temepratures.

Figure S7 shows the temperature dependence of Rc as a function of the gate bias. At large gate bias regime, when the channel is populated with electrons, the contact resistance of the ML-WS2 devices increases with decreasing temperature. We attribute this observation to the Schottky behavior of the contacts at low temperatures (Figure S6).

Fig. S7: Specific contact resistance increases with decreasing temperature due to pronounced Schottky behavior of the contacts at lower temperatures.

7 Figure S8 illustrates the transfer characteristics and intrinsic conductance of a back-gated device measured at room temperature (RT) and 25°K. This device does not have top gate dielectric and metal electrode. The device was located in the bright region of a WS2 flake. The device shows intrinsic field-effect mobility of 51 and 330cm2/V.s at RT and

25°K, respectively.

Fig. S8: Transfer characteristics and the corresponding intrinsic channel conductance of a back- gated device fabricated in the bright region measured at room temperature and 25°K.

Figure S9 shows the corresponding temperature-dependent intrinsic conductance of the dim device shown in Figure 5 in the manuscript. This device also exhibits apparent crossover from an apparent metallic phase at high carrier densities to an insulating phase at low carrier densities.

Fig. S9: Intrinsic conductance of the device in Figure 5 measured at different temperatures. Device exhibits appetent MIT.

8 Table SI gives the summary of the previous reports on CVD WS2.

Table. SI: Comparison of our results with the previous reports on CVD WS2.

Reference Precursors Carrier Substrate Flake size Field-effect mobility gas (µm) (cm2/V.s.) This work WO3 + S N2 SiO2/Si >200 48 (at 300K) ~300 (at 25k) [1] WO3 + S Ar Graphite on ~ 15 N. A. Quartz [2] WO3 + S Ar Au ~1000 <2 (at 300K) [3] WO2.9 + NaCl + S Ar+H2 SiO2/Si ~ 80 ~14.2 (at 300K)

[4] Ammonium H2S Au ~ 420 ~20 (at 300K) metatungstate hydrate +H2S [5] WO3 + S Ar+H2 SiO2/Si ~ 50 N. A.

[6] WO3 + S Ar+H2 Sapphire, ~ 135 ~4 (at 300K) SiO2/Si

[7] WO3 + S Ar SiO2/Si ~370 N. A. [8] WCl6 + S Ar h-BN < 5 N. A.

[9] WO3 + S Ar WO3 powder ~ 180 N. A. on SiO2/Si

[10] WO3 + S Ar SiO2/Si < 20 ~0.01 (at 300K) (PTAS seeds)

[11] WO3 + S Ar/H2 Sapphire < 50 ~0.46 (at 300K) [12] WO3 + S Ar WO3 film on < 10 N. A. SiO2/Si

[13] WO3 + S Ar SiO2/Si < 20 N. A.

References

[1] Y. Kobayashi, S. Sasaki, S. Mori, H. Hibino, Z. Liu, K. Watanabe, et al., "Growth and optical properties of high-quality monolayer WS2 on graphite," ACS nano, vol. 9, pp. 4056-4063, 2015. [2] Y. Gao, Z. Liu, D.-M. Sun, L. Huang, L.-P. Ma, L.-C. Yin, et al., "Large-area synthesis of high-quality and uniform monolayer WS2 on reusable Au foils," Nature communications, vol. 6, 2015. [3] S. Li, S. Wang, D.-M. Tang, W. Zhao, H. Xu, L. Chu, et al., "Halide-assisted atmospheric pressure growth of large WSe2 and WS2 monolayer crystals," Applied Materials Today, vol. 1, pp. 60-66, 11// 2015. [4] S. J. Yun, S. H. Chae, H. Kim, J. C. Park, J.-H. Park, G. H. Han, et al., "Synthesis of centimeter-scale monolayer tungsten disulfide film on gold foils," ACS nano, vol. 9, pp. 5510-5519, 2015. [5] Q. Fu, W. Wang, L. Yang, J. Huang, J. Zhang, and B. Xiang, "Controllable synthesis of high quality monolayer WS 2 on a SiO 2/Si substrate by chemical vapor deposition," RSC Advances, vol. 5, pp. 15795-15799, 2015. [6] Z.-Q. Xu, Y. Zhang, S. Lin, C. Zheng, Y. L. Zhong, X. Xia, et al., "Synthesis and transfer of large-area monolayer WS2 crystals: moving toward the recyclable use of sapphire substrates," ACS nano, vol. 9, pp. 6178-6187, 2015. [7] Y. Rong, Y. Fan, A. L. Koh, A. W. Robertson, K. He, S. Wang, et al., "Controlling sulphur precursor addition for large single crystal domains of WS 2," Nanoscale, vol. 6, pp. 12096-12103, 2014. [8] M. Okada, T. Sawazaki, K. Watanabe, T. Taniguch, H. Hibino, H. Shinohara, et al., "Direct chemical vapor deposition growth of WS2 atomic layers on hexagonal boron nitride," ACS nano, vol. 8, pp. 8273-8277, 2014. [9] C. Cong, J. Shang, X. Wu, B. Cao, N. Peimyoo, C. Qiu, et al., "Synthesis and Optical Properties of Large-Area Single-Crystalline 2D Semiconductor WS2 Monolayer from Chemical Vapor Deposition," Advanced Optical Materials, vol. 2, pp. 131-136, 2014. [10] Y.-H. Lee, L. Yu, H. Wang, W. Fang, X. Ling, Y. Shi, et al., "Synthesis and Transfer of Single-Layer Transition Metal Disulfides on Diverse Surfaces," Nano Letters, vol. 13, pp. 1852-1857, 2013/04/10 2013. [11] Y. Zhang, Y. Zhang, Q. Ji, J. Ju, H. Yuan, J. Shi, et al., "Controlled growth of high-quality monolayer WS2 layers on sapphire and imaging its grain boundary," ACS nano, vol. 7, pp. 8963-8971, 2013. [12] H. R. Gutiérrez, N. Perea-López, A. L. Elías, A. Berkdemir, B. Wang, R. Lv, et al., "Extraordinary Room-Temperature Photoluminescence in Triangular WS2 Monolayers," Nano Letters, vol. 13, pp. 3447-3454, 2013/08/14 2013. [13] N. Peimyoo, J. Shang, C. Cong, X. Shen, X. Wu, E. K. Yeow, et al., "Nonblinking, intense two-dimensional light emitter: monolayer WS2 triangles," Acs Nano, vol. 7, pp. 10985-10994, 2013.