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An Intermediate Representation for Optimizing Compilers Nico Reissmann, Jan Christian Meyer, Magnus Själander

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An Intermediate Representation for Optimizing Compilers Nico Reissmann, Jan Christian Meyer, Magnus Själander Thesis for the degree of Philosophiae Doctor Principles, Techniques, and Tools for Explicit and Automatic Parallelization Nico Reissmann January 28, 2019 Norwegian University of Science and Technology Faculty of Information Technology and Electrical Engineering Department of Computer Science Abstract The end of Dennard scaling also brought an end to technology scaling as a means to improve performance. Chip manufacturers had to abandon fre- quency and superscalar scaling as processors became increasingly power con- strained. An architecture’s power budget became the limiting factor to perfor- mance gains, and computations had to be performed more energy-efficiently. Designers turned to chip multiprocessors (CMPs) and developers began to employ specialized architectures, such as Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs), to further improve performance while meeting the power envelope. The exploitation of parallelism in an energy- efficient manner became the only way forward. Until the end of technology scaling, programs experienced transparent per- formance gains with every new processor generation. However, CMPs, GPUs, and FPGAs rely on the static extraction of parallelism to improve performance, and programs need to be modified to take advantage of these architectures. Thus, performance gains are no longer achieved transparently, and develop- ers and tools are forced to face new, as well as long-neglected challenges in program parallelization. These challenges include the detection and encod- ing of potential parallelism in automatic approaches, application portability issues on GPUs, and performance portability issues on CMPs. It is essential to address these challenges, as the continuous increase in computer perfor- mance now solely relies on the exploitation of parallelism. This thesis consists of three parts, each addressing one of the aforementioned challenges in program parallelization. The first part addresses the detection and encoding of potential parallelism in automatic approaches. It presents the Regionalized Value State Dependence Graph (RVSDG) as an alternative intermediate representation for optimizing and parallelizing compilers. The RVSDG exposes the hierarchical structure of programs and explicitly models the dependencies between computations, permitting the explicit encoding of iii concurrent operations and program structures, such as conditionals, loops, and functions. This helps to expose the inherent parallelism in programs and its structures by employing well-known methods for the extraction of instruc- tion level parallelism. The second part addresses application portability issues on GPUs. A GPU’s specialized architecture is optimized for highly regular data-parallel applica- tions, but compromises program performance for workloads with irregular control flow, potentially leading to redundant code execution. We propose a control flow restructuring method to effectively eliminate repeated code ex- ecution on GPUs and potentially improve performance. The third part addresses performance portability on CMPs. This issue arises as developers overfit their application to a specific architecture, which results in suboptimal performance for different program inputs or different architec- tures. We improve performance analysis for OpenMP programs by address- ing the scalability challenges of the grain graph visualization method. We present an aggregation method for grain graphs that hierarchically groups re- lated nodes into a single node. This aggregated graph can then be navigated by progressively uncovering nodes with performance issues, while hiding un- related regions of the graph. This enhances productivity by enabling devel- opers to understand performance problems of highly-parallel OpenMP pro- grams more easily. The insights and techniques developed by addressing these three challenges may result in improved methods and tools for the exploitation of parallelism. The RVSDG is a promising IR for parallelizing compilers, as it permits the en- coding of concurrent computations. The grain graph offers a familiar struc- tural view to developers along with the performance issues of a particular pro- gram. In the future, it is necessary to cast these ideas into mature tools to make them applicable in practice and foster further research. iv List of Contributions Thesis Articles 1. RVSDG: An Intermediate Representation for Optimizing Compilers Nico Reissmann, Jan Christian Meyer, Magnus Själander. Unpublished Manuscript 2. Perfect Reconstructability of Control Flow from Demand Dependence Graphs Helge Bahmann, Nico Reissmann, Magnus Jahre, and Jan Christian Meyer. In Transactions on Architecture and Code Optimization (TACO), Volume 11 Issue 4, ACM, 2015 3. Efficient Control Flow Restructuring for GPUs Nico Reissmann, Thomas L. Falch, Benjamin A. Björnseth, Helge Bah- mann, Jan Christian Meyer, and Magnus Jahre. In Proceedings of the International Conference on High Performance Com- puting & Simulation (HPCS), IEEE, 2016 Winner of Outstanding Paper Award 4. Diagnosing Highly-Parallel OpenMP Programs With Aggregated Grain Graphs Nico Reissmann and Ananya Muddukrishna. In Proceedings of the International European Conference on Parallel and Distributed Computing (Euro-Par), Springer, 2018 v Other Articles 1. A Study of Energy and Locality Effects using Space-filling Curves Nico Reissmann, Jan Christian Meyer, Magnus Jahre. In Proceedings of the 28th IEEE International Parallel & Distributed Pro- cessing Symposium (IPDPS) and IPDPS Workshops (IPDPSW), 2014. 2. Towards fine-grained dynamic tuning of HPC applications on modern multi-core architectures Mohammed Sourouri, Espen Birker Raknes, Nico Reissmann, Johannes Langguth, Daniel Hackenberg, Robert Schöne, Per Gunnar Kjeldsberg. In Proceedings of the International Conference for High Performance Com- puting, Networking, Storage and Analysis (SC), 2017. 3. Aggregating Large Grain Graphs For Improved OpenMP Productivity Nico Reissmann, Magnus Jahre, Ananya Muddukrishna. In Fourth International Workshop on Visual Performance Analysis (VPA), 2017. 4. RVSDG: An Intermediate Representation for the Multi-Core Era Nico Reissmann, Jan Christian Meyer, Magnus Själander. In 11th Nordic Workshop on Multi-Core Computing (MCC), 2018. 5. Load Balancing Domain Decompositions of a Lattice-Boltzmann Proxy Application Jan Christian Meyer, Janusa Ragunathan, Jørgen Valstad, Nico Reissmann. In 11th Nordic Workshop on Multi-Core Computing (MCC), 2018. vi Acknowledgements First and foremost, my deepest and sincerest thanks to Helge Bahmann and Jan Christian Meyer, for their invaluable guidance over the last twelve years. Both have challenged me to explore new and unfamiliar topics, broadened my perspective, sparked my love for compilers, and helped me to become a better engineer and researcher. My heartfelt thanks also to Magnus Själander for his advice and encouragement over the last few years, as well as for his interest in my work. Sincere thanks also to Gunnar Tufte for his support and the many insightful conversations. Gratitude is also due to my co-supervisors, Lasse Natvig and Per Gunnar Kjeldsberg, for their support throughout the years. Moreover, I am grateful to Anne Berit Dahl, Birgit Sørgård, Berit Hellan, and Ellen Solberg for finding solutions instead of problems, and trying to reduce bureaucracy to a minimum. I would also like to thank my colleagues from the Computing group for making the fourth floor a fun and engaging workplace, and especially for the innumerable and illuminating discussions during lunch time and over payday drinks. They have been an indispensable part of my aca- demic life, and contributed substantially to my social well-being and growth as a researcher. A big round of thanks to my friends from Germany, Gothenburg, and Trond- heim, for helping me to escape from the office and enriching my life. In par- ticular, I would like to thank my long-term friends Carina Walter, René Kaiser, Jens Teuscher, Franziska Holzhauer-Pansa, Oliver Holzhauer, Aleksejs Sen- cenko, Marina Vazhnova, Dragana Laketi´c,Leif Tore Rusten, Elizabeth and Ja- cob Sturdy, David Fallon, and John Naliboff. My deepest gratitude is also due to my parents, Luise and Friedmar Reiss- mann, to my brother’s family, Mario, Yvonne, and Felix Reissmann, and to my close family, Birgit and Joachim Reissmann, as well as Urs, Anja, Nadja, and vii Larissa Weber, for their boundless patience, unwavering support, and endless encouragement. Thanks for always having my back! Last, but not least, I am eternally grateful to my better half, Ramona Enache, for her help throughout in preserving my sanity, providing support in times of need, and her constant love. You make me a better person! Nico Reissmann Trondheim, 4th November 2018 viii Contents A. Overview1 1. Introduction3 2. Motivation and Scope7 2.1. Modern Architectures . 10 2.2. Programming Modern Architectures . 12 2.3. Parallelization Challenges . 17 2.4. Summary . 25 3. Research Contributions 27 3.1. Thesis Articles . 29 3.2. Frameworks and Tools . 31 3.3. Other Articles . 32 4. Background and Related Work 35 4.1. Compiler Intermediate Representations . 35 4.2. Graphics Processing Units . 38 4.3. Grain Graphs . 41 5. Concluding Remarks 47 5.1. FutureWork ............................ 48 5.2. Outlook . 55 B. Regionalized Value State Dependence Graph 59 B1. RVSDG: An Intermediate Representation for Optimizing Compilers 61 B1.1. Introduction . 62 B1.2. Motivation . 65 B1.3. The Regionalized Value State Dependence Graph . 67
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