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Compiler Optimization Effects on Register Collisions

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Compiler Optimization Effects on Register Collisions COMPILER OPTIMIZATION EFFECTS ON REGISTER COLLISIONS A Thesis presented to the Faculty of California Polytechnic State University, San Luis Obispo In Partial Fulfillment of the Requirements for the Degree Master of Science in Computer Science by Jonathan Tan June 2018 c 2018 Jonathan Tan ALL RIGHTS RESERVED ii COMMITTEE MEMBERSHIP TITLE: Compiler Optimization Effects on Register Collisions AUTHOR: Jonathan Tan DATE SUBMITTED: June 2018 COMMITTEE CHAIR: Aaron Keen, Ph.D. Professor of Computer Science COMMITTEE MEMBER: Theresa Migler, Ph.D. Professor of Computer Science COMMITTEE MEMBER: John Seng, Ph.D. Professor of Computer Science iii ABSTRACT Compiler Optimization Effects on Register Collisions Jonathan Tan We often want a compiler to generate executable code that runs as fast as possible. One consideration toward this goal is to keep values in fast registers to limit the number of slower memory accesses that occur. When there are not enough physical registers available for use, values are \spilled" to the runtime stack. The need for spills is discovered during register allocation wherein values in use are mapped to physical registers. One factor in the efficacy of register allocation is the number of values in use at one time (register collisions). Register collision is affected by compiler optimizations that take place before register allocation. Though the main purpose of compiler optimizations is to make the overall code better and faster, some optimiza- tions can actually increase register collisions. This may force the register allocation process to spill. This thesis studies the effects of different compiler optimizations on register collisions. iv ACKNOWLEDGMENTS Thanks to: • My advisor, Aaron Keen, for guiding, encouraging, and mentoring me on the thesis and classes. Words cannot describe the impact you had on me. • My committee members (John Seng and Theresa Migler) for taking time out of their busy schedules to help better my thesis. • My many great professors that taught me so many invaluable lessons. • My Dad, Mom, and Brother (Jeffrey Tan, Shirley Her, and Benjamin Tan) for taking care of me and calling me to check in and see how I am doing. • My roomates (Andrew Kim, Michael Djaja, Dylan Sun, Pierson Yieh) for en- couragement to push through the hard times and the great times. • My entire EPIC family for the continued support and many great laughs and times throughout college. v TABLE OF CONTENTS Page LIST OF FIGURES . viii CHAPTER 1 Introduction . .1 1.1 Register Collisions . .1 1.2 Optimizations . .3 1.3 Motivation . .4 1.4 Contributions . .4 2 Background & Related Works . .5 2.1 Control-Flow Graph . .5 2.2 Live Ranges . .6 2.3 Register Allocation . .8 2.3.1 Interference Graph . .9 2.3.2 Graph Coloring . 10 2.4 Related Works . 11 2.4.1 Heuristics . 11 2.4.2 Graph Coloring Algorithm . 11 3 Setup & Experimental Design . 13 3.1 Clang and LLVM . 13 3.2 Aggregation . 17 3.3 Benchmarks . 18 4 Results & Analysis . 20 4.1 Baseline Graph Anaylsis . 21 4.1.1 Average Register Collisions Across Functions . 21 4.1.2 Maximum Register Collisions Across Functions . 22 4.1.3 Register Collisions Across Registers . 24 4.1.4 Stack Space . 28 4.2 All-Loops Configuration . 28 4.2.1 All-Loops Optimization On . 28 vi 4.2.2 All-Loops Optimization Off . 32 4.3 General Observations . 35 4.3.1 Stack Space On Optimization . 36 4.3.2 Stack Space Off Optimization . 40 4.4 Double Optimizations . 41 4.4.1 All-Loops and Argpromotion Optimization . 42 4.4.2 Licm and All-loops Optimization . 45 4.4.3 Licm and Argpromotion Optimization . 50 4.5 Thumb Architecture . 52 4.5.1 All-Loops Optimization . 52 4.5.2 Jump-threading and Early-cse-memssa Optimization . 56 4.5.3 Spills Between Architectures . 57 5 Future Works & Conclusion . 61 5.1 Future Works . 61 5.1.1 Subject Optimizations . 61 5.1.2 Optimization Combinations . 61 5.1.3 Register Allocator . 61 5.1.4 Timings . 62 5.1.5 Architectures . 62 5.2 Conclusion . 62 BIBLIOGRAPHY . 64 APPENDICES A -O3 Optimization List . 67 B ARM Double Optimization Numbers . 69 C Register Collision Graphs . 70 D Double Optimizations Spill Count . 94 vii LIST OF FIGURES Figure Page 1.1 Example of the loop-unrolling compiler optimization. Left side is original loop. Right side is with loop-unrolling applied. .2 2.1 Example of creating a CFG given a program . .6 2.2 Example of a live range with virtual registers . .7 2.3 Example of Non-SSA form when compared to SSA form . .8 2.4 Example of why SSA may be beneficial . .9 4.1 Average Reg Collisions by Function, Baseline All Subject Optimizations Off, No Minimum Register Collisions Threshold . 21 4.2 Average Reg Collisions by Function, Baseline All Subject Optimizations On, No Minimum Register Collisions Threshold . 22 4.3 Baseline Average Register Collisions by Function . 23 4.4 Baseline Maximum Register Collisions by Function . 25 4.5 Baseline Register Collisions by Register . 26 4.6 Baseline Stack Space . 27 4.7 Average Register Collisions by Function, All-Loops On . 29 4.8 Maximum Register Collisions by Function, All-Loops On . 30 4.9 Register Collisions by Register, All-Loops On . 30 4.10 Stack Space All-Loops On . 31 4.11 Average Register Collisions by Function, All-Loops Off . 33 4.12 Maximum Register Collisions by Function, All-Loops Off . 33 4.13 Register Collisions by Register, All-Loops Off . 34 4.14 Stack Space All-Loops Off . 35 4.15 x86 Average Register Collisions by Function, Collision Statistics (Percentage at or Below Threshold) . 36 4.16 x86 Maximum Register Collisions by Function, Collision Statistics (Percentage at or Below Threshold) . 37 4.17 x86 Register Collisions by Register Statistics (Percentage at or Below Threshold) . 37 4.18 Stack On LICM . 38 viii 4.19 Stack On Tail Call Elimination . 39 4.20 Stack Off LICM . 40 4.21 x86 Double Optimization Average Collisions by Function, Collision Statistics (Percentage at or Below Threshold) . 42 4.22 x86 Double Optimization Maximum Collisions by Function, Collision Statistics (Percentage at or Below Threshold) . 42 4.23 x86 Double Optimization Register Collisions by Registers, Collision Statistics (Percentage at or Below Threshold) . 43 4.24 Register Level On All-Loops and Argpromotion . 44 4.25 Register Collisions by Register Level Off All-Loops and Argpromotion . 45 4.26 Stack On All-Loops and Argpromotion . 46 4.27 Stack Off All-Loops and Argpromotion . 46 4.28 Stack On Licm and All-Loops . 48 4.29 Stack Off, Licm and All-Loops . 49 4.30 Stack On, Licm and Argpromotion . 51 4.31 Stack Off Licm and Argpromotion . 51 4.32 Thumb Average Register Collisions by Function Statistics . 53 4.33 Thumb Maximum Register Collisions by Function Statistics . 53 4.34 Thumb Register Collisions by Register Statistics . 54 4.35 ARM Average Register Collisions by Function, All-loops Off . 55 4.36 ARM Stack Space All-loops Off . 55 4.37 ARM Average Register Collisions by Function, Off Early-CSE-Memssa . 57 4.38 ARM Average Register Collisions by Function, Off Jump-Threading . 58 4.39 ARM Stack Space Off Early-CSE-Memssa . 59 4.40 ARM Stack Space Off Jump-Threading . 59 4.41 Number of Spills in the x86 Architecture . 60 4.42 Number of Spills in the Thumb Architecture . 60 B.1 THUMB Average Register Collisions by Function Statistics . 69 B.2 THUMB Maximum Register Collisions by Function Statistics . 69 B.3 THUMB Register Collisions by Register Statistics . 69 ix C.1 x86 Average Register Collisions by Function, Off Licm . 70 C.2 x86 Average Register Collisions by Function, On Licm . 71 C.3 x86 Maximum Register Collisions by Function, On Licm . 71 C.4 x86 Maximum Register Collisions by Function, Off Licm . 72 C.5 x86 Register Collisions by Register, On Licm . 72 C.6 x86 Register Collisions by Register, Off Licm . 73 C.7 x86 Average Register Collisions by Function, Off Tail Call Elimination . 73 C.8 x86 Average Register Collisions by Function, On Tail Call Elimination . 74 C.9 x86 Maximum Register Collisions by Function, Off Tail Call Elimination . 74 C.10 x86 Maximum Register Collisions by Function, On Tail Call Elimination . 75 C.11 x86 Register Collisions by Register, Off Tail Call Elimination . 75 C.12 x86 Register Collisions by Register, On Tail Call Elimination . 76 C.13 x86 Stack Space, Off Tail Call Elimination . 76 C.14 x86 Average Register Collisions by Function, Off All-Loops and Argpromotion . 77 C.15 x86 Average Register Collisions by Function, On All-Loops and Argpromotion . 77 C.16 x86 Maximum Register Collisions by Function, Off All-Loops and Argpromotion . 78 C.17 x86 Maximum Register Collisions by Function, On All-Loops and Argpromotion . 78 C.18 x86 Average Register Collisions by Function, On Licm and All-Loops . 79 C.19 x86 Average Register Collisions by Function, Off Licm and All-Loops . 79 C.20 x86 Maximum Register Collisions by Function, On Licm and All-Loops . 80 C.21 x86 Maximum Register Collisions by Function, Off Licm and All-Loops . ..
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