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POWER8 Processor Users Manual for the Single-Chip Module

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POWER8 Processor Users Manual for the Single-Chip Module Title Page POWER8 Processor User’s Manual for the Single-Chip Module Advance 16 March 2016 Version 1.3 ® Copyright and Disclaimer © Copyright International Business Machines Corporation 2014, 2015, 2016 Printed in the United States of America March 2016 IBM, the IBM logo, and ibm.com are trademarks or registered trademarks of International Business Machines Corp., registered in many jurisdictions worldwide. Other product and service names might be trademarks of IBM or other compa- nies. A current list of IBM trademarks is available on the Web at “Copyright and trademark information” at www.ibm.com/legal/copytrade.shtml. The OpenPOWER word mark and the OpenPOWER Logo mark, and related marks, are trademarks and service marks licensed by OpenPOWER. Intel, Intel logo, Intel Inside, Intel Inside logo, Intel Centrino, Intel Centrino logo, Celeron, Intel Xeon, Intel SpeedStep, Itanium, and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Other company, product, and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this docu- ment was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. Note: This document contains information on products in the design, sampling and/or initial production phases of development. This information is subject to change without notice. Verify with your IBM field applications engineer that you have the latest version of this document before finalizing a design. This document is intended for development of technology products compatible with Power Architecture®. You may use this document, for any purpose (commercial or personal) and make modifications and distribute; however, modifications to this document may violate Power Architecture and should be carefully considered. Any distribution of this document or its derivative works shall include this Notice page including but not limited to the IBM warranty disclaimer and IBM liability limitation. No other licenses, expressed or implied, by estoppel or otherwise to any intellectual property rights are granted by this document. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. IBM makes no represen- tations or warranties, either express or implied, including but not limited to, warranties of merchantability, fitness for a particular purpose, or non-infringement, or that any practice or implementation of the IBM documentation will not infringe any third party patents, copyrights, trade secrets, or other rights. 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Version 1.3 16 March 2016 User’s Manual Single-Chip Module Advance POWER8 Processor Contents List of Tables .................................................................................................................. 13 List of Figures ................................................................................................................17 Revision Log .................................................................................................................. 19 About this Document ..................................................................................................... 21 Who Should Read this Document .......................................................................................................... 21 Conventions Used in This Document ..................................................................................................... 21 Representation of Numbers ............................................................................................................. 21 Bit Significance ................................................................................................................................ 21 Other Conventions ........................................................................................................................... 21 Related Documents ................................................................................................................................ 22 1. POWER8 Processor Overview ................................................................................. 23 1.1 General Features ............................................................................................................................ 23 2. POWER8 Processor Core ......................................................................................... 27 2.1 Key Design Fundamentals .............................................................................................................. 27 2.1.1 64-Bit Implementation of the Power ISA (version 2.07) ......................................................... 27 2.1.3 Speculative Superscalar Inner Core Organization ................................................................ 28 2.1.4 Specific Focus on Storage Latency Management ................................................................. 29 2.2 Pipeline Structure ............................................................................................................................ 29 2.3 Microprocessor Core - Detailed Features ....................................................................................... 31 2.3.1 Instruction Fetching and Branch Prediction ........................................................................... 31 2.3.3 Instruction Dispatch, Sequencing, and Completion Control .................................................. 33 2.3.4 Fixed-Point Execution Pipelines ............................................................................................ 35 2.3.5 Load and Store Execution Pipelines ...................................................................................... 35 2.3.6 Branch and Condition Register Execution Pipelines ............................................................. 37 2.3.7 Unified Second-Level Memory Management (Address Translation) ..................................... 37 2.3.8 Data Prefetch ......................................................................................................................... 38 2.3.9 VSU Execution Pipeline ......................................................................................................... 38 2.3.10 DFP Execution Pipeline ....................................................................................................... 39 3. Power Architecture Compliance .............................................................................. 41 3.1 Book I - User Instruction Set Architecture ....................................................................................... 41 3.1.1 Defined Instructions ............................................................................................................... 41 3.1.1.1 Illegal Instructions ........................................................................................................... 41 3.1.1.2 Instructions Supported ................................................................................................... 41 3.1.1.3 Invalid Forms .................................................................................................................. 41 3.1.2 Branch Processor .................................................................................................................. 42 3.1.2.1 Instruction Fetching ........................................................................................................ 42 3.1.2.2 Branch Prediction ........................................................................................................... 42 3.1.2.3 Instruction Cache Block Touch Hint ............................................................................... 42 3.1.2.4 Out-of-Order Execution and Instruction Flushes ............................................................ 42 3.1.2.5 Branch Processor Instructions with Undefined Results .................................................. 43 Version 1.3 Contents 16 March 2016 Page 3 of 450 User’s Manual Single-Chip Module POWER8 Processor Advance 3.1.3 Fixed-Point Processor ............................................................................................................ 43 3.1.3.1 Fixed-Point Exception Register (XER) ........................................................................... 43 3.1.4 Storage Access Alignment Support Overview ....................................................................... 44 3.1.4.1 Misaligned Flushes
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