DOCSLIB.ORG

MPC7410/MPC7400 RISC Microprocessor Reference Manual

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
MPC7410/MPC7400 RISC Microprocessor Reference Manual MPC7410/MPC7400 RISC Microprocessor Reference Manual Supports MPC7410 MPC7400 MPC7410UM/D 10/2008 Rev. 2 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support Information in this document is provided solely to enable system and software USA/Europe or Locations Not Listed: implementers to use Freescale Semiconductor products. There are no express or Freescale Semiconductor, Inc. implied copyright licenses granted hereunder to design or fabricate any integrated Technical Information Center, EL516 circuits or integrated circuits based on the information in this document. 2100 East Elliot Road Tempe, Arizona 85284 Freescale Semiconductor reserves the right to make changes without further notice to +1-800-521-6274 or any products herein. Freescale Semiconductor makes no warranty, representation or +1-480-768-2130 www.freescale.com/support guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH any product or circuit, and specifically disclaims any and all liability, including without Technical Information Center limitation consequential or incidental damages. “Typical” parameters which may be Schatzbogen 7 provided in Freescale Semiconductor data sheets and/or specifications can and do 81829 Muenchen, Germany vary in different applications and actual performance may vary over time. All operating +44 1296 380 456 (English) +46 8 52200080 (English) parameters, including “Typicals” must be validated for each customer application by +49 89 92103 559 (German) customer’s technical experts. Freescale Semiconductor does not convey any license +33 1 69 35 48 48 (French) under its patent rights nor the rights of others. Freescale Semiconductor products are www.freescale.com/support not designed, intended, or authorized for use as components in systems intended for Japan: surgical implant into the body, or other applications intended to support or sustain life, Freescale Semiconductor Japan Ltd. or for any other application in which the failure of the Freescale Semiconductor product Headquarters ARCO Tower 15F could create a situation where personal injury or death may occur. Should Buyer 1-8-1, Shimo-Meguro, Meguro-ku purchase or use Freescale Semiconductor products for any such unintended or Tokyo 153-0064 unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor Japan and its officers, employees, subsidiaries, affiliates, and distributors harmless against all 0120 191014 or +81 3 5437 9125 claims, costs, damages, and expenses, and reasonable attorney fees arising out of, [email protected] directly or indirectly, any claim of personal injury or death associated with such Asia/Pacific: unintended or unauthorized use, even if such claim alleges that Freescale Freescale Semiconductor China Ltd. Semiconductor was negligent regarding the design or manufacture of the part. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China Freescale and the Freescale logo are trademarks or registered trademarks +86 010 5879 8000 of Freescale Semiconductor, Inc. in the U.S. and other countries. All other [email protected] product or service names are the property of their respective owners. The For Literature Requests Only: described product is a PowerPC microprocessor. The PowerPC name is a trademark of IBM Corp. and is used under license. IEEE 1149.1a and 754 Freescale Semiconductor are trademarks of the Institute of Electrical and Electronics Engineers, Inc. Literature Distribution Center P.O. Box 5405 (IEEE). This product is not endorsed or approved by the IEEE. Denver, Colorado 80217 © Freescale Semiconductor, Inc., 2000, 2002, 2008. All rights reserved. +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC7410UM/D Rev. 2, 10/2008 Contents Paragraph Page Number Title Number About ThisCont ents Book Audience ........................................................................................................................... 36 Organization...................................................................................................................... 37 Suggested Reading............................................................................................................ 38 General Information...........................................................................................................38 Related Documentation......................................................................................................38 Conventions ...................................................................................................................... 39 Acronyms and Abbreviations ........................................................................................... 40 Terminology Conventions................................................................................................. 43 Chapter 1 Overview 1.1 General Operation............................................................................................................1-1 1.2 General Features .............................................................................................................. 1-4 1.2.1 Overview of Features................................................................................................... 1-4 1.2.2 Instruction Flow...........................................................................................................1-8 1.2.2.1 Instruction Queue and Dispatch Unit ...................................................................... 1-8 1.2.2.2 Branch Processing Unit (BPU)................................................................................ 1-8 1.2.2.3 Completion Unit ...................................................................................................... 1-9 1.2.2.4 Independent Execution Units................................................................................. 1-10 1.2.2.4.1 AltiVec Vector Permute Unit (VPU) ................................................................. 1-10 1.2.2.4.2 AltiVec Vector Arithmetic Logic Unit (VALU)................................................. 1-11 1.2.2.4.3 Integer Units (IUs)............................................................................................. 1-11 1.2.2.4.4 Floating-Point Unit (FPU) ................................................................................. 1-11 1.2.2.4.5 Load/Store Unit (LSU) ...................................................................................... 1-12 1.2.2.4.6 System Register Unit (SRU).............................................................................. 1-12 1.2.3 Memory Management Units (MMUs)....................................................................... 1-12 1.2.4 On-Chip Instruction and Data Caches ....................................................................... 1-13 1.2.5 L2 Cache Implementation.......................................................................................... 1-14 1.2.6 System Interface/Bus Interface Unit (BIU) ............................................................... 1-15 1.2.6.1 System Interface Operation ................................................................................... 1-16 1.2.6.2 Signal Groupings ................................................................................................... 1-17 1.2.6.2.1 Signal Configuration.......................................................................................... 1-20 1.2.6.2.2 Clocking............................................................................................................. 1-21 1.3 Implementation .............................................................................................................. 1-21 1.3.1 PowerPC Registers and Programming Model ........................................................... 1-22 MPC7410/MPC7400 RISC Microprocessor Reference Manual, Rev. 2 Freescale Semiconductor 3 Contents Paragraph Page Number Title Number 1.3.2 Instruction Set ............................................................................................................1-28 1.3.2.1 PowerPC Instruction Set........................................................................................ 1-28 1.3.2.2 AltiVec Instruction Set........................................................................................... 1-30 1.3.2.3 Instruction Set........................................................................................................ 1-30 1.3.3 On-Chip Cache Implementation ................................................................................ 1-31 1.3.3.1 Cache Model.......................................................................................................... 1-31 1.3.3.2 Cache Implementation ........................................................................................... 1-31 1.3.4 Exception Model........................................................................................................ 1-31 1.3.4.1 PowerPC Exception Model.................................................................................... 1-32 1.3.4.2 MPC7410 Exception Implementation ................................................................... 1-33 1.3.5 Memory Management...............................................................................................
Load more

Recommended publications
  • RISC-V Vector Extension Webinar II
    RISC-V Vector Extension Webinar II August 3th, 2021 Thang Tran, Ph.D. Principal Engineer Webinar II - Agenda • Andes overview • Vector technology background – SIMD/vector concept – Vector processor basic • RISC-V V extension ISA – Basic – CSR • RISC-V V extension ISA – Memory operations – Compute instructions • Sample codes – Matrix multiplication – Loads with RVV versions 0.8 and 1.0 • AndesCore™ NX27V • Summary Copyright© 2020 Andes Technology Corp. 2 Terminology • ACE: Andes Custom Extension • ISA: Instruction Set Architecture • CSR: Control and Status Register • GOPS: Giga Operations Per Second • SEW: Element Width (8-64) • GFLOPS: Giga Floating-Point OPS • ELEN: Largest Element Width (32 or 64) • XRF: Integer register file • XLEN: Scalar register length in bits (64) • FRF: Floating-point register file • FLEN: FP register length in bits (16-64) • VRF: Vector register file • VLEN: Vector register length in bits (128-512) • SIMD: Single Instruction Multiple Data • LMUL: Register grouping multiple (1/8-8) • MMX: Multi Media Extension • EMUL: Effective LMUL • SSE: Streaming SIMD Extension • VLMAX/MVL: Vector Length Max • AVX: Advanced Vector Extension • AVL/VL: Application Vector Length • Configurable: parameters are fixed at built time, i.e. cache size • Extensible: added instructions to ISA includes custom instructions to be added by customer • Standard extension: the reserved codes in the ISA for special purposes, i.e. FP, DSP, … • Programmable: parameters can be dynamically changed in the program Copyright© 2020 Andes Technology Corp. 3 RISC-V V Extension ISA Basic Copyright© 2020 Andes Technology Corp. 4 Vector Register ISA • Vector-Register ISA Definition: − All vector operations are between vector registers (except for load and store).
    [Show full text]
  • Optimizing Packed String Matching on AVX2 Platform
    Optimizing Packed String Matching on AVX2 Platform M. Akif Aydo˘gmu¸s1,2 and M.O˘guzhan Külekci1 1 Informatics Institute, Istanbul Technical University, Istanbul, Turkey [email protected], [email protected] 2 TUBITAK UME, Gebze-Kocaeli, Turkey Abstract. Exact string matching, searching for all occurrences of given pattern P on a text T , is a fundamental issue in computer science with many applica- tions in natural language processing, speech processing, computational biology, information retrieval, intrusion detection systems, data compression, and etc. Speeding up the pattern matching operations benefiting from the SIMD par- allelism has received attention in the recent literature, where the empirical results on previous studies revealed that SIMD parallelism significantly helps, while the performance may even be expected to get automatically enhanced with the ever increasing size of the SIMD registers. In this paper, we provide variants of the previously proposed EPSM and SSEF algorithms, which are orig- inally implemented on Intel SSE4.2 (Streaming SIMD Extensions 4.2 version with 128-bit registers). We tune the new algorithms according to Intel AVX2 platform (Advanced Vector Extensions 2 with 256-bit registers) and analyze the gain in performance with respect to the increasing length of the SIMD registers. Profiling the new algorithms by using the Intel Vtune Amplifier for detecting performance bottlenecks led us to consider the cache friendliness and shared-memory access issues in the AVX2 platform. We applied cache op- timization techniques to overcome the problems particularly addressing the search algorithms based on filtering. Experimental comparison of the new solutions with the previously known-to- be-fast algorithms on small, medium, and large alphabet text files with diverse pattern lengths showed that the algorithms on AVX2 platform optimized cache obliviously outperforms the previous solutions.
    [Show full text]
  • Optimizing Software Performance Using Vector Instructions Invited Talk at Speed-B Conference, October 19–21, 2016, Utrecht, the Netherlands
    Agner Fog, Technical University of Denmark Optimizing software performance using vector instructions Invited talk at Speed-B conference, October 19–21, 2016, Utrecht, The Netherlands. Abstract Microprocessor factories have a problem obeying Moore's law because of physical limitations. The answer is increasing parallelism in the form of multiple CPU cores and vector instructions (Single Instruction Multiple Data - SIMD). This is a challenge to software developers who have to adapt to a moving target of new instruction set additions and increasing vector sizes. Most of the software industry is lagging several years behind the available hardware because of these problems. Other challenges are tasks that cannot easily be executed with vector instructions, such as sequential algorithms and lookup tables. The talk will discuss methods for overcoming these problems and utilize the continuously growing power of microprocessors on the market. A few problems relevant to cryptographic software will be covered, and the outlook for the future will be discussed. Find more on these topics at author website: www.agner.org/optimize Moore's law The clock frequency has stopped growing due to physical limitations. Instead, the number of CPU cores and the size of vector registers is growing. Hierarchy of bottlenecks Program installation Program load, JIT compile, DLL's System database Network access Speed → File input/output Graphical user interface RAM access, cache utilization Algorithm Dependency chains CPU pipeline and execution units Remove
    [Show full text]
  • Idisa+: a Portable Model for High Performance Simd Programming
    IDISA+: A PORTABLE MODEL FOR HIGH PERFORMANCE SIMD PROGRAMMING by Hua Huang B.Eng., Beijing University of Posts and Telecommunications, 2009 a Thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in the School of Computing Science Faculty of Applied Science c Hua Huang 2011 SIMON FRASER UNIVERSITY Fall 2011 All rights reserved. However, in accordance with the Copyright Act of Canada, this work may be reproduced without authorization under the conditions for Fair Dealing. Therefore, limited reproduction of this work for the purposes of private study, research, criticism, review and news reporting is likely to be in accordance with the law, particularly if cited appropriately. APPROVAL Name: Hua Huang Degree: Master of Science Title of Thesis: IDISA+: A Portable Model for High Performance SIMD Pro- gramming Examining Committee: Dr. Kay C. Wiese Associate Professor, Computing Science Simon Fraser University Chair Dr. Robert D. Cameron Professor, Computing Science Simon Fraser University Senior Supervisor Dr. Thomas C. Shermer Professor, Computing Science Simon Fraser University Supervisor Dr. Arrvindh Shriraman Assistant Professor, Computing Science Simon Fraser University SFU Examiner Date Approved: ii Declaration of Partial Copyright Licence The author, whose copyright is declared on the title page of this work, has granted to Simon Fraser University the right to lend this thesis, project or extended essay to users of the Simon Fraser University Library, and to make partial or single copies only for such users or in response to a request from the library of any other university, or other educational institution, on its own behalf or for one of its users.
    [Show full text]
  • Counter Control Flow Divergence in Compiled Query Pipelines
    Make the Most out of Your SIMD Investments: Counter Control Flow Divergence in Compiled Query Pipelines Harald Lang Andreas Kipf Linnea Passing Technical University of Munich Technical University of Munich Technical University of Munich Munich, Germany Munich, Germany Munich, Germany [email protected] [email protected] [email protected] Peter Boncz Thomas Neumann Alfons Kemper Centrum Wiskunde & Informatica Technical University of Munich Technical University of Munich Amsterdam, The Netherlands Munich, Germany Munich, Germany [email protected] [email protected] [email protected] ABSTRACT Control flow graph: SIMD lane utilization: Increasing single instruction multiple data (SIMD) capabilities in out scan σ ⋈ ⋈ ⋈ out scan σ ⋈ ... modern hardware allows for compiling efficient data-parallel query index 7 x x x x x x x pipelines. This means GPU-alike challenges arise: control flow di- traversal 6 x x Index ⋈ vergence causes underutilization of vector-processing units. In this 5 x x x paper, we present efficient algorithms for the AVX-512 architecture 4 x 3 x x x x x σ no to address this issue. These algorithms allow for fine-grained as- x x x x x x x x match SIMD lanes 2 signment of new tuples to idle SIMD lanes. Furthermore, we present 1 x x x strategies for their integration with compiled query pipelines with- scan 0 x x x out introducing inefficient memory materializations. We evaluate t our approach with a high-performance geospatial join query, which Figure 1: During query processing, individual SIMD lanes shows performance improvements of up to 35%.
    [Show full text]
  • A Second Generation SIMD Microprocessor Architecture
    A Second Generation SIMD Microprocessor Architecture Mike Phillip Motorola, Inc. Austin, TX [email protected] Mike Phillip 8/17/98 1 WhyWhy SIMDSIMD ?? ¥ ÒBut isnÕt that really old technology ?Ó Ð Yes, architecturally speaking, but... Ð SIMD within registers provides ÒcheapÓ interelement communictaions that wasnÕt present in prior SIMD systems ¥ Provides a reasonable tradeoff between increased computational bandwidth and manageable complexity Ð Fewer register ports needed per Òunit of useful workÓ Ð Naturally takes advantage of stream-oriented parallelism ¥ Can be easily scaled for various price/performance points ¥ Can be applied in addition to traditional techniques Mike Phillip 8/17/98 2 SomeSome AlternativesAlternatives ¥ Wider superscalar machines Benefits: High degree of flexibility; easy to program Problems: Complex implementations; higher power consumption ¥ Special purpose DSP and Media architectures Benefits: Low power; efficient use of silicon Problems: Traditional design approaches tend to limit CPU speeds; lack of generality; lack of development tools ¥ VLIW Benefits: Reduced implementation complexity; impresses your friends Problems: Need VERY long words to provide sufficient scalability; limited to compile-time visibility of parallelism; difficult to program Mike Phillip 8/17/98 3 TheThe FirstFirst GenerationGeneration ¥ First generation implementations tend to overlay SIMD instructions on existing architectural space Ð Permitted quick time to market, but limits scalability Ð Intel, Cyrix, AMD (MMX), SPARC (VIS) are
    [Show full text]
  • Effective Vectorization with Openmp 4.5
    ORNL/TM-2016/391 Effective Vectorization with OpenMP 4.5 Joseph Huber Oscar Hernandez Graham Lopez Approved for public release. Distribution is unlimited. March 2017 DOCUMENT AVAILABILITY Reports produced after January 1, 1996, are generally available free via US Department of Energy (DOE) SciTech Connect. Website: http://www.osti.gov/scitech/ Reports produced before January 1, 1996, may be purchased by members of the public from the following source: National Technical Information Service 5285 Port Royal Road Springfield, VA 22161 Telephone: 703-605-6000 (1-800-553-6847) TDD: 703-487-4639 Fax: 703-605-6900 E-mail: [email protected] Website: http://classic.ntis.gov/ Reports are available to DOE employees, DOE contractors, Energy Technology Data Ex- change representatives, and International Nuclear Information System representatives from the following source: Office of Scientific and Technical Information PO Box 62 Oak Ridge, TN 37831 Telephone: 865-576-8401 Fax: 865-576-5728 E-mail: [email protected] Website: http://www.osti.gov/contact.html This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any in- formation, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial prod- uct, process, or service by trade name, trademark, manufacturer, or otherwise, does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof.
    [Show full text]
  • Jon Stokes Jon
    Inside the Machine the Inside A Look Inside the Silicon Heart of Modern Computing Architecture Computer and Microprocessors to Introduction Illustrated An Computers perform countless tasks ranging from the business critical to the recreational, but regardless of how differently they may look and behave, they’re all amazingly similar in basic function. Once you understand how the microprocessor—or central processing unit (CPU)— Includes discussion of: works, you’ll have a firm grasp of the fundamental concepts at the heart of all modern computing. • Parts of the computer and microprocessor • Programming fundamentals (arithmetic Inside the Machine, from the co-founder of the highly instructions, memory accesses, control respected Ars Technica website, explains how flow instructions, and data types) microprocessors operate—what they do and how • Intermediate and advanced microprocessor they do it. The book uses analogies, full-color concepts (branch prediction and speculative diagrams, and clear language to convey the ideas execution) that form the basis of modern computing. After • Intermediate and advanced computing discussing computers in the abstract, the book concepts (instruction set architectures, examines specific microprocessors from Intel, RISC and CISC, the memory hierarchy, and IBM, and Motorola, from the original models up encoding and decoding machine language through today’s leading processors. It contains the instructions) most comprehensive and up-to-date information • 64-bit computing vs. 32-bit computing available (online or in print) on Intel’s latest • Caching and performance processors: the Pentium M, Core, and Core 2 Duo. Inside the Machine also explains technology terms Inside the Machine is perfect for students of and concepts that readers often hear but may not science and engineering, IT and business fully understand, such as “pipelining,” “L1 cache,” professionals, and the growing community “main memory,” “superscalar processing,” and of hardware tinkerers who like to dig into the “out-of-order execution.” guts of their machines.
    [Show full text]
  • Altivec Extension to Powerpc Accelerates Media Processing
    ALTIVEC EXTENSION TO POWERPC ACCELERATES MEDIA PROCESSING DESIGNED AROUND THE PREMISE THAT MULTIMEDIA WILL BE THE PRIMARY CONSUMER OF PROCESSING CYCLES IN FUTURE PCS, ALTIVEC—WHICH APPLE CALLS THE VELOCITY ENGINE—INCREASES PERFORMANCE ACROSS A BROAD SPECTRUM OF MEDIA PROCESSING APPLICATIONS. There is a clear trend in personal com- extension to a general-purpose architecture. puting toward multimedia-rich applications. But the similarity ends there. Whereas the These applications will incorporate a wide vari- other extensions were obviously constrained ety of multimedia technologies, including audio by backward compatibility and a desire to and video compression, 2D image processing, limit silicon investment to a small fraction of 3D graphics, speech and handwriting recogni- the processor die area, the primary goal for Keith Diefendorff tion, media mining, and narrow-/broadband AltiVec was high functionality. It was designed signal processing for communication. from scratch around the premise that multi- Microprocessor Report In response to this demand, major micro- media will become the primary consumer of processor vendors have announced architec- processing cycles8 in future PCs and therefore tural extensions to their general-purpose deserves first-class treatment in the CPU. Pradeep K. Dubey processors in an effort to improve their multi- Unlike most other extensions, which over- media performance. Intel extended IA-32 with load their floating-point (FP) registers to IBM Research Division MMX1 and SSE (alias KNI),2 Sun enhanced accommodate multimedia data, AltiVec ded- Sparc with VIS,3 Hewlett-Packard added icates a large new register file exclusively to it. MAX4 to its PA-RISC architecture, Silicon Although overloading the FP registers avoids Ron Hochsprung Graphics extended the MIPS architecture with new architectural state, eliminating the need MDMX,5 and Digital (now Compaq) added to modify the operating system, it also signif- Apple Computer MVI to Alpha.
    [Show full text]
  • Register Level Sort Algorithm on Multi-Core SIMD Processors
    Register Level Sort Algorithm on Multi-Core SIMD Processors Tian Xiaochen, Kamil Rocki and Reiji Suda Graduate School of Information Science and Technology The University of Tokyo & CREST, JST {xchen, kamil.rocki, reiji}@is.s.u-tokyo.ac.jp ABSTRACT simultaneously. GPU employs a similar architecture: single- State-of-the-art hardware increasingly utilizes SIMD paral- instruction-multiple-threads(SIMT). On K20, each SMX has lelism, where multiple processing elements execute the same 192 CUDA cores which act as individual threads. Even a instruction on multiple data points simultaneously. How- desktop type multi-core x86 platform such as i7 Haswell ever, irregular and data intensive algorithms are not well CPU family supports AVX2 instruction set (256 bits). De- suited for such architectures. Due to their importance, it veloping algorithms that support multi-core SIMD architec- is crucial to obtain efficient implementations. One example ture is the precondition to unleash the performance of these of such a task is sort, a fundamental problem in computer processors. Without exploiting this kind of parallelism, only science. In this paper we analyze distinct memory accessing a small fraction of computational power can be utilized. models and propose two methods to employ highly efficient Parallel sort as well as sort in general is fundamental and bitonic merge sort using SIMD instructions as register level well studied problem in computer science. Algorithms such sort. We achieve nearly 270x speedup (525M integers/s) on as Bitonic-Merge Sort or Odd Even Merge Sort are widely a 4M integer set using Xeon Phi coprocessor, where SIMD used in practice.
    [Show full text]
  • G4 Is First Powerpc with Altivec: 11/16/98
    G4 Is First PowerPC With AltiVec Due Mid-1999, Motorola’s Next Chip Aims at Macintosh, Networking by Linley Gwennap the original PowerPC 603. The integer core uses a simple five-stage pipeline (four stages for ALU operations) with a Motorola will extend its PowerPC limited amount of instruction reordering. Each cycle, the line with the first G4 processor core, CPU can issue two instructions plus a branch. As Figure 1 which it unveiled at last month’s shows, integer execution resources include dual ALUs plus a Microprocessor Forum. According to project leader Paul “system” unit (which handles the more complicated integer Reed, the new core adds a faster floating-point unit to the instructions) and a load/store unit. older G3 core and doubles its cache and system-bus band- Although the integer core was deemed acceptable, width. The G4 is also the first chip to incorporate the AltiVec Motorola felt the floating-point unit needed improvement. extensions, which greatly increase performance on many For single-precision instructions, the G3 FPU is fully pipe- bandwidth- or compute-intensive applications, including lined with a three-cycle latency, but it requires an extra cycle both integer and floating-point algorithms. The chip is already for double-precision operations, halving the issue rate and sampling and is due to appear in products by mid-1999. increasing the latency. The G4 FPU, however, is fully After IBM pulled out of Somerset (see MPR 6/22/98, pipelined, even for double-precision operations. Most tech- p. 4), the G4 became the sole property of Motorola; IBM has nical FP applications use double precision and will see a no plans to sell the part.
    [Show full text]
  • Performance Portable Short Vector Transforms
    Dissertation Performance Portable Short Vector Transforms ausgefuhrt¨ zum Zwecke der Erlangung des akademischen Grades eines Doktors der technischen Wissenschaften unter der Leitung von Ao. Univ.-Prof. Dipl.-Ing. Dr. techn. Christoph W. Uberhuber¨ E115 – Institut fur¨ Angewandte und Numerische Mathematik eingereicht an der Technischen Universit¨at Wien Fakult¨at fur¨ Technische Naturwissenschaften und Informatik von Dipl.-Ing. Franz Franchetti Matrikelnummer 9525993 Hartiggasse 3/602 2700 Wiener Neustadt Wien, am 7. J¨anner 2003 Kurzfassung In dieser Dissertation wird eine mathematische Methode entwickelt, die automati- sche Leistungsoptimierung von Programmen zur Berechnung von diskreten linearen Transformationen fur¨ Prozessoren mit Multimedia-Vektorerweiterungen (short vector SIMD extensions) erm¨oglicht, wobei besonderes Gewicht auf die diskrete Fourier- Transformation (DFT) gelegt wird. Die neuentwickelte Methode basiert auf dem Kronecker-Produkt-Formalismus, der erweitert wurde, um die spezifischen Eigenschaf- ten von Multimedia-Vektorerweiterungen abzubilden. Es wurde auch eine speziell ange- paßte Cooley-Tukey-FFT-Variante1 entwickelt, die sowohl fur¨ Vektorl¨angen der Form N =2k als auch fur¨ allgemeinere Problemgr¨oßen anwendbar ist. Die neuentwickelte Methode wurde als Erweiterung fur¨ Spiral2 und Fftw3,die derzeitigen Top-Systeme im Bereich der automatischen Leistungsoptimierung fur¨ dis- krete lineare Transformationen, getestet. Sie erlaubt es, extrem schnelle Programme zur Berechnung der DFT zu erzeugen, welche die derzeit schnellsten Programme zur Berechnung der DFT auf Intel-Prozessoren mit den Multimedia-Vektorerweiterungen “Streaming SIMD Extensions” (SSE und SSE 2) sind. Sie sind schneller als die ent- sprechenden Programme aus der manuell optimierten Intel-Softwarebibliothek MKL (Math Kernel Library). Zus¨atzlich wurden die bisher ersten und einzigen automatisch leistungsoptimierten Programme zur Berechnung der Walsh-Hadamard-Transformation und fur¨ zwei-dimensionale Kosinus-Transformationen erzeugt.
    [Show full text]