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Instruction Set Architecture of MIPS Processor

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MIPS Processor CSE 675.02: Introduction to Computer Architecture Memory Instruction Set Architecture CPU Coprocessor 1 (FPU) Registers Registers of $0 $0 $31 $31 Control MIPS Processor rithmetic Multiply A Logic unit divide Arithmetic Prog. Counter Lo Hi unit Presentation B Coprocessor 0 (traps and memory) Registers BadVAddr Cause Slides by Status EPC Gojko Babić Figure A.10.1 06/21/2005 g. babic Presentation B 2 MIPS Registers MIPS Registers (continued) •CPU: • Coprocessor 0 – CP0 is incorporated on the MIPS CPU chip – 32 32-bit general purpose registers – GPRs (r0 – r31); and it provides functions necessary to support operating r0 has fixed value of zero. Attempt to writing into r0 is not system: exception handling, memory management scheduling and control of critical resources. illegal, but its value will not change; – two 32-bit registers – Hi & Lo, hold results of integer • Coprocessor 0 (CP0) registers (partial list): multiply and divide – Status register (CP0reg12) – processor status and control; – 32-bit program counter – PC; – Cause register (CP0reg13) – cause of the most recent • Floating Point Processor – FPU (Coprocessor 1 – CP1): exception; – 32 32-bit floating point registers – FPRs (f0 – f31); – EPC register (CP0reg14) – program counter at the last – five control registers; exception; – BadVAddr register (CP0reg08) – the address for the most recent address related exception; g. babic Presentation B 3 g. babic Presentation B 4 MIPS Data Types MIPS arithmetic • MIPS operates on: • All instructions have 3 operands – 32-bit (unsigned or 2’s complement) integers, • Operand order is fixed (destination first) – 32-bit (single precision floating point) real numbers, Example: – 64-bit (double precision floating point) real numbers; C code: a = b + c • bytes and half words loaded into GPRs are either zero or sign MIPS ‘code’: add a, b, c bit expanded to fill the 32 bits; • only 32-bit units can be loaded into FPRs; 32-bit real numbers “The natural number of operands for an operation like are stored in even numbered FPRs. addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to • 64-bit real numbers are stored in two consecutive FPRs, the philosophy of keeping the hardware simple” starting with even-numbered register. g. babic Presentation B 5 MIPS arithmetic Registers vs. Memory • Design Principle: simplicity favors regularity. • Arithmetic instructions operands must be • Of course this complicates some things... registers, C code: a = b + c + d; — only 32 registers provided • Compiler associates variables with registers MIPS code: add a, b, c add a, a, d • What about programs with lots of variables • Operands must be registers, only 32 registers provided Control Input • Each register contains 32 bits Memory Datapath Output • Design Principle: smaller is faster. Why? Processor I/O MIPS Addressing Modes Memory Organization • register addressing; • Viewed as a large, single-dimension array, • immediate addressing; • only one memory data addressing: with an address. – register content plus offset (register indexed); • A memory address is an index 0 8 bits of data • since r0 always contains value 0: into the array 1 8 bits of data – r0 + offset Æ absolute addressing; 2 8 bits of data • offset = 0 Æ register indirect; • "Byte addressing" means that 3 8 bits of data 4 8 bits of data • MIPS supports byte addressability: the index points to a byte of 5 8 bits of data – it means that a byte is the smallest unit with its address; memory. 6 8 bits of data ... • MIPS supports 32-bit addresses: – it means that an address is given as 32-bit unsigned integer; g. babic Presentation B 10 MIPS Alignment Memory Organization • MIPS restricts memory accesses to be aligned as follows: • Bytes are nice, but most data items use larger "words" – 32-bit word has to start at byte address that is multiple of 4; • For MIPS, a word is 32 bits or 4 bytes. 32-bit word at address 4n includes four bytes with addresses 0 32 bits of data 4n, 4n+1, 4n+2, and 4n+3. Registers hold 32 bits of data 4 32 bits of data – 16-bit half word has to start at byte address that is multiple 32 bits of data 8 of 2; 12 32 bits of data ... 16-bit word at address 2n includes two bytes with addresses •232 bytes with byte addresses from 0 to 232-1 2n and 2n+1. •230 words with byte addresses 0, 4, 8, ... 232-4 • Words are aligned i.e., what are the least 2 significant bits of a word address? g. babic Presentation B 12 MIPS Instructions • 32-bit fixed format instruction and 3 formats; Our First Example • register – register and register-immediate computational instructions; • Can we figure out the code? Guess!!! swap(int v[], int k); { int temp; • single address mode for load/store instructions: temp = v[k] v[k] = v[k+1]; – register content + offset (called base addressing); v[k+1] = temp; } swap: • simple branch conditions; muli $2, $5, 4 add $2, $4, $2 – branch instructions use PC relative addressing; lw $15, 0($2) lw $16, 4($2) – branch address = [PC] + 4 + 4×offset sw $16, 0($2) sw $15, 4($2) • jump instructions with: jr $31 – 28-bit addresses (jumps inside 256 megabyte regions), or – absolute 32-bit addresses. g. babic Presentation B 13 MIPS Instruction (continued) Stored Program Concept • Instructions that move data: – load to register from memory, – store from register to memory, • Instructions are bits • Programs are stored in memory – move between registers in same and different — to be read or written just like data coprocessors memory for data, programs, • ALU integer instructions, compilers, editors, etc. Processor Memory • Floating point instructions, • Control-related instructions, • Fetch & Execute Cycle – Instructions are fetched and put into a special register • Special control-related instructions. – Bits in the register "control" the subsequent actions – Fetch the “next” instruction and continue g. babic Presentation B 15 MIPS Instruction Layout CPU Load & Store Instructions • lw rt, offset(rs) ; load 32-bits: • MIPS instructions are an example of fixed field decoding Regs[rt] Å Mem [offset+Regs[rs]] • sw rt, offset(rs) ; store 32-bits: /ft /offset Mem [offset+Regs[rs]] Å Regs[rt] • lb rt, offset(rs) ; load 8-bits (byte): Regs[rt] Å 24-bit sign-extend || Mem [offset+Regs[rs]] Note: || means concatenation. /ft /fs /fd • lbu rt, offset(rs) ; load 8-bits (byte) unsigned: and fd Å fs funct ft Regs[rt] Å 24-bit zero-extend || Mem [offset+Regs[rs]] • sh rt, offset(rs) ; store 16-bits: jump_target Mem [offset+Regs[rs]] Å Regs[rt] (16 least significant bits taken from the register) Plus: sb, lh, & lhu g. babic Presentation B 17 g. babic Presentation B 18 FP Load, Store & Move Instructions Move Instructions • lwc1 ft, offset(rs) ; load into FP register: Regs[ft] Å Mem [offset+Regs[rs]] • mfc1 rt, fs ; move from FPU to CPU: Regs[rt] Å Regs[fs] • swc1 ft, offset(rs) ; store from FP register: • mtc1 rt, fs ; move from CPU to FPU: Regs[fs] Å Regs[rt] Mem [offset+Regs[rs]] Å Regs[ft] • mfc0 rt, rd ; move from CP0 to CPU: Regs[rt] Å CP0Regs[rd] • mov.d fd, fs ; move FP double precision between FPRs: Regs[fd] || Regs[fd+1]Å Regs[fs] || Regs[fs+1] • mtc0 rt, rd ; move from CPU to CP0: CP0Regs[rd] Å Regs[rt] • mov.s fd, fs ; move FP single precision between FPRs: Regs[fd] Å Regs[fs] • mfhi rd ; move from Hi: Regs[rd] Å Hi; • mflo rd ; move from Lo: Regs[rd] Å Lo; g. babic Presentation B 19 g. babic Presentation B 20 ALU Integer Instructions ALU Integer Instructions (continued) • add rd, rs, rt ; add integer@: Regs[rd] Å Regs[rs] + Regs[rt] • mul rs, rt ; multiply integer: Hi || LoÅ Regs[rs] × Regs[rt] Note: mul does not generate an arithmetic exception, since Note: Instructions flagged by @ may cause an arithmetic exception. a storage for the result is always sufficiently large. • addi rt, rs, immediate ; add immediate integer@: • div rs, rt ; divide integer: Lo Å Regs[rs] / Regs[rt] Regs[rt] Å Regs[rs] + 16-bit sign-extend || immediate Hi Å Regs[rs] mod Regs[rt] Note: div does not generate an arithmetic exception and • and rd, rs, rt ; bit-wise AND 32 bits: software should test for zero divisor. Regs[rd] Å Regs[rs] AND Regs[rt] • andi rt, rs, immediate ; bit-wise AND immediate 32 bits: • sll rd, rt, shamt ; shift left logical: Regs[rt] Å Regs[rs] AND 16-bit zero-extend || immediate Regs[rd] Å Regs[rt] << shamt • lui rt, immediate ; load upper immediate: • slt rd, rs, rt ; set less than integer: Regs[rt] Å immediate || 16 zero-bits if (Regs[rs] < Regs[rt]) then Regs[rd] Å 1 else Regs[rd] Å0 g. babic Presentation B 21 g. babic Presentation B 22 ALU Integer Instructions (continued) Arithmetic FP Instructions • addu rd, rs, rt ; add unsigned integer: • add.d fd, fs, ft ; FP double precision add: Regs[rd] Å Regs[rs] + Regs[rt] Regs[fd]||Regs[fd+1]Å ÅRegs[fs]||Regs[fs+1] + Regs[ft]||Regs[ft+1] Note: This instructions does not cause an arithmetic exception. Plus: addiu, sub @, subu, mulu, divu, or, ori, xor, xori, • mul.s fd, fs, ft ; FP single precision multiply: nor, slti, sltu, sltiu, srl, sra Regs[fd]Å Regs[fs] × Regs[ft] Plus: add.s, sub.d, sub.s, mul.d, div.d, div.s, several • Instructions addu, addiu, subu, mulu, divu, sltu, and sltiu convert floating point to/from integer instructions, operate on unsigned numbers and these instructions do not several compare instructions. trap on overflow. They are appropriate for unsigned arithmetic, Note: Any of instructions above may cause FP exception.
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