Multithreaded Programming Guide

Total Page:16

File Type:pdf, Size:1020Kb

Multithreaded Programming Guide Multithreaded Programming Guide Sun Microsystems, Inc. 4150 Network Circle Santa Clara, CA 95054 U.S.A. Part No: 816–5137–10 January 2005 Copyright 2005 Sun Microsystems, Inc. 4150 Network Circle, Santa Clara, CA 95054 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Third-party software, including font technology, is copyrighted and licensed from Sun suppliers. Parts of the product may be derived from Berkeley BSD systems, licensed from the University of California. UNIX is a registered trademark in the U.S. and other countries, exclusively licensed through X/Open Company, Ltd. Sun, Sun Microsystems, the Sun logo, docs.sun.com, AnswerBook, AnswerBook2, and Solaris are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the U.S. and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. The OPEN LOOK and Sun™ Graphical User Interface was developed by Sun Microsystems, Inc. for its users and licensees. Sun acknowledges the pioneering efforts of Xerox in researching and developing the concept of visual or graphical user interfaces for the computer industry. Sun holds a non-exclusive license from Xerox to the Xerox Graphical User Interface, which license also covers Sun’s licensees who implement OPEN LOOK GUIs and otherwise comply with Sun’s written license agreements. U.S. Government Rights – Commercial software. Government users are subject to the Sun Microsystems, Inc. standard license agreement and applicable provisions of the FAR and its supplements. DOCUMENTATION IS PROVIDED “AS IS” AND ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD TO BE LEGALLY INVALID. Copyright 2005 Sun Microsystems, Inc. 4150 Network Circle, Santa Clara, CA 95054 U.S.A. Tous droits réservés. Ce produit ou document est protégé par un copyright et distribué avec des licences qui en restreignent l’utilisation, la copie, la distribution, et la décompilation. Aucune partie de ce produit ou document ne peut être reproduite sous aucune forme, par quelque moyen que ce soit, sans l’autorisation préalable et écrite de Sun et de ses bailleurs de licence, s’il y en a. Le logiciel détenu par des tiers, et qui comprend la technologie relative aux polices de caractères, est protégé par un copyright et licencié par des fournisseurs de Sun. Des parties de ce produit pourront être dérivées du système Berkeley BSD licenciés par l’Université de Californie. UNIX est une marque déposée aux Etats-Unis et dans d’autres pays et licenciée exclusivement par X/Open Company, Ltd. Sun, Sun Microsystems, le logo Sun, docs.sun.com, AnswerBook, AnswerBook2, et Solaris sont des marques de fabrique ou des marques déposées, de Sun Microsystems, Inc. aux Etats-Unis et dans d’autres pays. Toutes les marques SPARC sont utilisées sous licence et sont des marques de fabrique ou des marques déposées de SPARC International, Inc. aux Etats-Unis et dans d’autres pays. Les produits portant les marques SPARC sont basés sur une architecture développée par Sun Microsystems, Inc. L’interface d’utilisation graphique OPEN LOOK et Sun™ a été développée par Sun Microsystems, Inc. pour ses utilisateurs et licenciés. Sun reconnaît les efforts de pionniers de Xerox pour la recherche et le développement du concept des interfaces d’utilisation visuelle ou graphique pour l’industrie de l’informatique. Sun détient une licence non exclusive de Xerox sur l’interface d’utilisation graphique Xerox, cette licence couvrant également les licenciés de Sun qui mettent en place l’interface d’utilisation graphique OPEN LOOK et qui en outre se conforment aux licences écrites de Sun. CETTE PUBLICATION EST FOURNIE “EN L’ETAT” ET AUCUNE GARANTIE, EXPRESSE OU IMPLICITE, N’EST ACCORDEE, Y COMPRIS DES GARANTIES CONCERNANT LA VALEUR MARCHANDE, L’APTITUDE DE LA PUBLICATION A REPONDRE A UNE UTILISATION PARTICULIERE, OU LE FAIT QU’ELLE NE SOIT PAS CONTREFAISANTE DE PRODUIT DE TIERS. CE DENI DE GARANTIE NE S’APPLIQUERAIT PAS, DANS LA MESURE OU IL SERAIT TENU JURIDIQUEMENT NUL ET NON AVENU. 040915@9495 Contents Preface 11 1 Covering Multithreading Basics 15 Defining Multithreading Terms 15 Meeting Multithreading Standards 17 Benefiting From Multithreading 17 Improving Application Responsiveness 17 Using Multiprocessors Efficiently 18 Improving Program Structure 18 Using Fewer System Resources 18 Combining Threads and RPC 18 Multithreading Concepts 19 Concurrency and Parallelism 19 Looking at Multithreading Structure 19 Thread Scheduling 20 Thread Cancellation 20 Thread Synchronization 21 Using the 64-bit Architecture 21 2 Basic Threads Programming 23 The Threads Library 23 Creating a Default Thread 23 Waiting for Thread Termination 25 Simple Threads Example 26 Detaching a Thread 27 Creating a Key for Thread-Specific Data 28 3 Deleting the Thread-Specific Data Key 29 Setting Thread-Specific Data 30 Getting Thread-Specific Data 30 Getting the Thread Identifier 33 Comparing Thread IDs 34 Initializing Threads 34 Yielding Thread Execution 35 Setting the Thread Priority 35 Getting the Thread Priority 36 Sending a Signal to a Thread 37 Accessing the Signal Mask of the Calling Thread 37 Forking Safely 38 Terminating a Thread 39 Finishing Up 39 Cancel a Thread 40 Cancelling a Thread 41 Enabling or Disabling Cancellation 42 Setting Cancellation Type 43 Creating a Cancellation Point 43 Pushing a Handler Onto the Stack 44 Pulling a Handler Off the Stack 44 3 Thread Attributes 47 Attribute Object 47 Initializing Attributes 48 Destroying Attributes 49 Setting Detach State 50 Getting the Detach State 51 Setting the Stack Guard Size 52 Getting the Stack Guard Size 53 Setting the Scope 53 Getting the Scope 54 Setting the Thread Concurrency Level 55 Getting the Thread Concurrency Level 55 Setting the Scheduling Policy 56 Getting the Scheduling Policy 57 Setting the Inherited Scheduling Policy 58 Getting the Inherited Scheduling Policy 58 4 Multithreaded Programming Guide • January 2005 Setting the Scheduling Parameters 59 Getting the Scheduling Parameters 60 Setting the Stack Size 61 Getting the Stack Size 62 About Stacks 63 Setting the Stack Address and Size 64 Getting the Stack Address and Size 65 4 Programming with Synchronization Objects 67 Mutual Exclusion Lock Attributes 68 Initializing a Mutex Attribute Object 70 Destroying a Mutex Attribute Object 70 Setting the Scope of a Mutex 71 Getting the Scope of a Mutex 72 Setting the Mutex Type Attribute 72 Getting the Mutex Type Attribute 74 Setting the Mutex Attribute’s Protocol 74 Getting the Mutex Attribute’s Protocol 76 Setting the Mutex Attribute’s Priority Ceiling 77 Getting the Mutex Attribute’s Priority Ceiling 78 Setting the Mutex’s Priority Ceiling 79 Getting the Mutex’s Priority Ceiling 80 Setting the Mutex’s Robust Attribute 81 Getting the Mutex’s Robust Attribute 83 Using Mutual Exclusion Locks 84 Initializing a Mutex 84 Making a Mutex Consistent 86 Locking a Mutex 87 Unlocking a Mutex 88 Locking With a Nonblocking Mutex 89 Destroying a Mutex 91 Code Examples of Mutex Locking 91 Condition Variable Attributes 95 Initializing a Condition Variable Attribute 96 Removing a Condition Variable Attribute 97 Setting the Scope of a Condition Variable 98 Getting the Scope of a Condition Variable 99 Using Condition Variables 100 5 Initializing a Condition Variable 100 Blocking on a Condition Variable 101 Unblocking One Thread 103 Blocking Until a Specified Time 104 Blocking For a Specified Interval 105 Unblocking All Threads 106 Destroying the Condition Variable State 108 Lost Wake-Up Problem 108 Producer and Consumer Problem 109 Synchronization With Semaphores 111 Named and Unnamed Semaphores 113 Counting Semaphores Overview 113 Initializing a Semaphore 114 Incrementing a Semaphore 115 Blocking on a Semaphore Count 116 Decrementing a Semaphore Count 117 Destroying the Semaphore State 117 Producer and Consumer Problem Using Semaphores 118 Read-Write Lock Attributes 119 Initializing a Read-Write Lock Attribute 120 Destroying a Read-Write Lock Attribute 121 Setting a Read-Write Lock Attribute 121 Getting a Read-Write Lock Attribute 122 Using Read-Write Locks 123 Initializing a Read-Write Lock 123 Acquiring the Read Lock on Read-Write Lock 124 Reading a Lock With a Nonblocking Read-Write Lock 125 Writing a Lock on Read-Write Lock 125 Writing a Lock With a Nonblocking Read-Write Lock 126 Unlocking a Read-Write Lock 127 Destroying a Read-Write Lock 128 Synchronization Across Process Boundaries 129 Producer and Consumer Problem Example 129 Comparing Primitives 130 5 Programming With the Solaris Software 133 Forking Issues in Process Creation 133 Fork-One Model 134 6 Multithreaded Programming Guide • January 2005 Fork-All Model 136 Choosing the Right Fork 137 Process Creation: exec and exit Issues 137 Timers, Alarms, and Profiling 138 Per-LWP POSIX Timers 138 Per-Thread Alarms 139 Profiling a Multithreaded Program 139 Nonlocal Goto: setjmp and longjmp 140 Resource Limits 140 LWPs and Scheduling Classes 140 Timeshare Scheduling 141
Recommended publications
  • JHDF5 (HDF5 for Java) 19.04
    JHDF5 (HDF5 for Java) 19.04 Introduction HDF5 is an efficient, well-documented, non-proprietary binary data format and library developed and maintained by the HDF Group. The library provided by the HDF Group is written in C and available under a liberal BSD-style Open Source software license. It has over 600 API calls and is very powerful and configurable, but it is not trivial to use. SIS (formerly CISD) has developed an easy-to-use high-level API for HDF5 written in Java and available under the Apache License 2.0 called JHDF5. The API works on top of the low-level API provided by the HDF Group and the files created with the SIS API are fully compatible with HDF5 1.6/1.8/1.10 (as you choose). Table of Content Introduction ................................................................................................................................ 1 Table of Content ...................................................................................................................... 1 Simple Use Case .......................................................................................................................... 2 Overview of the library ............................................................................................................... 2 Numeric Data Types .................................................................................................................... 3 Compound Data Types ................................................................................................................ 4 System
    [Show full text]
  • Sun 64-Bit Binary Alignment Proposal
    1 KMIP 64-bit Binary Alignment Proposal 2 3 To: OASIS KMIP Technical Committee 4 From: Matt Ball, Sun Microsystems, Inc. 5 Date: May 1, 2009 6 Version: 1 7 Purpose: To propose a change to the binary encoding such that each part is aligned to an 8-byte 8 boundary 9 10 Revision History 11 Version 1, 2009-05-01: Initial version 12 Introduction 13 The binary encoding as defined in the 1.0 version of the KMIP draft does not maintain alignment to 8-byte 14 boundaries within the message structure. This causes problems on hard-aligned processors, such as the 15 ARM, that are not able to easily access memory on addresses that are not aligned to 4 bytes. 16 Additionally, it reduces performance on modern 64-bit processors. For hard-aligned processors, when 17 unaligned memory contents are requested, either the compiler has to add extra instructions to perform 18 two aligned memory accesses and reassemble the data, or the processor has to take a „trap‟ (i.e., an 19 interrupt generated on unaligned memory accesses) to correctly assemble the memory contents. Either 20 of these options results in reduced performance. On soft-aligned processors, the hardware has to make 21 two memory accesses instead of one when the contents are not properly aligned. 22 This proposal suggests ways to improve the performance on hard-aligned processors by aligning all data 23 structures to 8-byte boundaries. 24 Summary of Proposed Changes 25 This proposal includes the following changes to the KMIP 0.98 draft submission to the OASIS KMIP TC: 26 Change the alignment of the KMIP binary encoding such that each part is aligned to an 8-byte 27 boundary.
    [Show full text]
  • Making Classes Provable Through Contracts, Models and Frames
    View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by CiteSeerX DISS. ETH NO. 17610 Making classes provable through contracts, models and frames A dissertation submitted to the SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH (ETH Zurich)¨ for the degree of Doctor of Sciences presented by Bernd Schoeller Diplom-Informatiker, TU Berlin born April 5th, 1974 citizen of Federal Republic of Germany accepted on the recommendation of Prof. Dr. Bertrand Meyer, examiner Prof. Dr. Martin Odersky, co-examiner Prof. Dr. Jonathan S. Ostroff, co-examiner 2007 ABSTRACT Software correctness is a relation between code and a specification of the expected behavior of the software component. Without proper specifica- tions, correct software cannot be defined. The Design by Contract methodology is a way to tightly integrate spec- ifications into software development. It has proved to be a light-weight and at the same time powerful description technique that is accepted by software developers. In its more than 20 years of existence, it has demon- strated many uses: documentation, understanding object-oriented inheri- tance, runtime assertion checking, or fully automated testing. This thesis approaches the formal verification of contracted code. It conducts an analysis of Eiffel and how contracts are expressed in the lan- guage as it is now. It formalizes the programming language providing an operational semantics and a formal list of correctness conditions in terms of this operational semantics. It introduces the concept of axiomatic classes and provides a full library of axiomatic classes, called the mathematical model library to overcome prob- lems of contracts on unbounded data structures.
    [Show full text]
  • IBM Informix Glossary
    IBM Informix Version 11.70 IBM Informix Glossary SC27-3531-00 IBM Informix Version 11.70 IBM Informix Glossary SC27-3531-00 Note Before using this information and the product it supports, read the information in “Notices” on page B-1. This document contains proprietary information of IBM. It is provided under a license agreement and is protected by copyright law. The information contained in this publication does not include any product warranties, and any statements provided in this manual should not be interpreted as such. When you send information to IBM, you grant IBM a nonexclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. © Copyright IBM Corporation 1996, 2010. US Government Users Restricted Rights – Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Glossary ..................................1-1 Numerics ....................................1-1 A......................................1-1 B ......................................1-3 C......................................1-4 D......................................1-8 E......................................1-13 F......................................1-15 G......................................1-16 H......................................1-17 I......................................1-17 J......................................1-19 K......................................1-19 L......................................1-19 M......................................1-21 N......................................1-22
    [Show full text]
  • High Dynamic Range Video
    High Dynamic Range Video Karol Myszkowski, Rafał Mantiuk, Grzegorz Krawczyk Contents 1 Introduction 5 1.1 Low vs. High Dynamic Range Imaging . 5 1.2 Device- and Scene-referred Image Representations . ...... 7 1.3 HDRRevolution ............................ 9 1.4 OrganizationoftheBook . 10 1.4.1 WhyHDRVideo? ....................... 11 1.4.2 ChapterOverview ....................... 12 2 Representation of an HDR Image 13 2.1 Light................................... 13 2.2 Color .................................. 15 2.3 DynamicRange............................. 18 3 HDR Image and Video Acquisition 21 3.1 Capture Techniques Capable of HDR . 21 3.1.1 Temporal Exposure Change . 22 3.1.2 Spatial Exposure Change . 23 3.1.3 MultipleSensorswithBeamSplitters . 24 3.1.4 SolidStateSensors . 24 3.2 Photometric Calibration of HDR Cameras . 25 3.2.1 Camera Response to Light . 25 3.2.2 Mathematical Framework for Response Estimation . 26 3.2.3 Procedure for Photometric Calibration . 29 3.2.4 Example Calibration of HDR Video Cameras . 30 3.2.5 Quality of Luminance Measurement . 33 3.2.6 Alternative Response Estimation Methods . 33 3.2.7 Discussion ........................... 34 4 HDR Image Quality 39 4.1 VisualMetricClassification. 39 4.2 A Visual Difference Predictor for HDR Images . 41 4.2.1 Implementation......................... 43 5 HDR Image, Video and Texture Compression 45 1 2 CONTENTS 5.1 HDR Pixel Formats and Color Spaces . 46 5.1.1 Minifloat: 16-bit Floating Point Numbers . 47 5.1.2 RGBE: Common Exponent . 47 5.1.3 LogLuv: Logarithmic encoding . 48 5.1.4 RGB Scale: low-complexity RGBE coding . 49 5.1.5 LogYuv: low-complexity LogLuv . 50 5.1.6 JND steps: Perceptually uniform encoding .
    [Show full text]
  • National Technical University of Athens School of Electrical and Computer Engineering Division of Computer Science
    National Technical University of Athens School of Electrical and Computer Engineering Division of Computer Science Detection Of Opaque Type Violations in Erlang Using Static Analysis Diploma Thesis by Manouk-Vartan Manoukian Supervisors: N.T.U.A Associate Prof. Konstantinos Sagonas Software Laboratory Athens, September 2009 National Technical University of Athens School of Electrical and Computer Engineering Division of Computer Science Software Laboratory Detection Of Opaque Type Violations in Erlang Using Static Analysis Diploma Thesis by Manouk-Vartan Manoukian Supervisors: N.T.U.A Associate Prof. Konstantinos Sagonas This thesis was approved by the examining committee on the 16th of September, 2009. (Signature) (Signature) (Signature) ........................ ........................ ........................ Kostas Kontogiannis Nikolaos Papaspyrou Konstantinos Sagonas N.T.U.A Associate Prof. N.T.U.A Assistant Prof. N.T.U.A Associate Prof. i (Signature) ........................ Manouk-Vartan Manoukian Graduate Electrical and Computer Engineer, N.T.U.A. c 2009 { All rights reserved] ii National Technical University of Athens School of Electrical and Computer Engineering Division of Computer Science Software Laboratory Copyright c All rights reserved Manouk-Vartan Manoukian, 2009 Publication and distribution of this thesis is allowed for non-commercial use only with ap- propriate acknowledgement of the author. For commercial use, permission can be obtained by contacting the author at [email protected]. iii iv Abstract Erlang is a general-purpose programming language designed at the Ericsson Computer Science Laboratory. Erlang has extensive dynamic libraries in which a plethora of abstract data types are defined. However, programming in Erlang suffers from the lack of opaque types. Opaque types are especially necessary in a production environment since they provide solid contractual guarantees.
    [Show full text]
  • IBM Informix User-Defined Routines and Data Types Developer.S Guide
    DB2 ® IBM Informix Version 10.0 IBM Informix User-Defined Routines and Data Types Developer’s Guide G251-2301-00 DB2 ® IBM Informix Version 10.0 IBM Informix User-Defined Routines and Data Types Developer’s Guide G251-2301-00 Note! Before using this information and the product it supports, read the information in “Notices” on page B-1. First Edition (December 2004) This document contains proprietary information of IBM. It is provided under a license agreement and is protected by copyright law. The information contained in this publication does not include any product warranties, and any statements provided in this manual should not be interpreted as such. When you send information to IBM, you grant IBM a nonexclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. © Copyright International Business Machines Corporation 1996, 2004. All rights reserved. US Government Users Restricted Rights – Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Introduction . .ix About This Manual . .ix Types of Users . .x Software Dependencies . .x Assumptions About Your Locale . .x Demonstration Databases . .x New Features . .xi Version 10.0 Enhancements . .xi Version 9.4 Enhancements . xii Documentation Conventions . xii Typographical Conventions . xii Feature, Product, and Platform . xiii Syntax Diagrams . xiv Example Code Conventions . xvii Additional Documentation . xviii Installation Guides . xviii Online Notes . xviii Informix Error Messages . .xx Manuals . xxi Online Help . xxi Accessibility . xxi IBM Informix Dynamic Server Version 10.0 and CSDK Version 2.90 Documentation Set . xxi Compliance with Industry Standards . xxiv IBM Welcomes Your Comments .
    [Show full text]
  • Proposal to Allocate Ranges to P1619.3
    1 From: Matt Ball, Sun Microsystems 2 To: OASIS KMIP TC 3 Date: June 25, 2009 4 Subject: Proposal to reserve values for IEEE P1619.3 5 Overview 6 This proposal requests allocating ranges of values within the binary encoding to IEEE P1619.3 so that 7 P1619.3 can make extensions without colliding with future KMIP versions or with vendor-specific or 8 proprietary extensions. 9 See changes below (with changebars) 10 9 Message Encoding 11 To support different transport protocols and different client capabilities, a number of message-encoding 12 mechanisms are supported. 13 9.1 TTLV Encoding 14 In order to minimize the resource impact on potentially low-function clients, one encoding 15 mechanism to be used for protocol messages is a simplified TTLV (Tag, Type, Length, Value) 16 scheme. 17 The scheme is designed to minimize the CPU cycle and memory requirements of clients that 18 must encode or decode protocol messages, and to provide optimal alignment for both 32-bit and 19 64-bit processors. Minimizing bandwidth over the transport mechanism is considered to be of 20 lesser importance. 21 9.1.1 TTLV Encoding Fields 22 Every Data object encoded by the TTLV scheme consists of 4 items, in order: 23 9.1.1.1 Item Tag 24 An Item Tag is a 3-byte binary unsigned integer, transmitted big endian, which contains a 25 number that designates the specific Protocol Field or Object that the TTLV object 26 represents. To ease debugging, and to ensure that malformed messages are detected 27 more easily, all tags must contain either the value 42 in hex or the value 54 in hex as the 28 high order (first) byte.
    [Show full text]
  • AN5092, FIR Filtering Using the Lightweight Signal Processor on MPC5777M
    Freescale Semiconductor, Inc. Document Number: AN5092 Application note Rev. 1 , 05/2015 FIR Filtering Using the Lightweight Signal Processor on MPC5777M by: Andrew Turner and Ian Howie 1 Introduction The Lightweight Signal Processing (LSP) auxiliary Contents processing unit (APU) is designed to accelerate processing applications normally suited to digital signal 1 Introduction .............................................................................. 1 processing (DSP) operations. The LSP-APU is 2 LSP comparison with SPE and SPE2 ....................................... 2 embedded in the e200z425n3 I/O processor found on 3 LSP –APU Programming basics .............................................. 2 3.1 GPR Registers .................................................................. 2 the Freescale’s MPC5777M device. The LSP-APU can 3.2 GPR Register pairings ..................................................... 3 be used to accelerate signal processing routines such as 3.3 Instruction Overview ....................................................... 3 finite impulse response (FIR) and infinite impulse 3.4 Example instructions ....................................................... 3 3.5 LSP-APU Data formats ................................................... 4 response (IIR) filters. This is accomplished using the 3.6 Fractional arithmetic and its benefits to signal processing5 standard 32-bit general purpose registers (GPRs), and 4 FIR Filter Introduction ............................................................. 6 supports vector
    [Show full text]
  • Fundamental Data Structures Contents
    Fundamental Data Structures Contents 1 Introduction 1 1.1 Abstract data type ........................................... 1 1.1.1 Examples ........................................... 1 1.1.2 Introduction .......................................... 2 1.1.3 Defining an abstract data type ................................. 2 1.1.4 Advantages of abstract data typing .............................. 4 1.1.5 Typical operations ...................................... 4 1.1.6 Examples ........................................... 5 1.1.7 Implementation ........................................ 5 1.1.8 See also ............................................ 6 1.1.9 Notes ............................................. 6 1.1.10 References .......................................... 6 1.1.11 Further ............................................ 7 1.1.12 External links ......................................... 7 1.2 Data structure ............................................. 7 1.2.1 Overview ........................................... 7 1.2.2 Examples ........................................... 7 1.2.3 Language support ....................................... 8 1.2.4 See also ............................................ 8 1.2.5 References .......................................... 8 1.2.6 Further reading ........................................ 8 1.2.7 External links ......................................... 9 1.3 Analysis of algorithms ......................................... 9 1.3.1 Cost models ......................................... 9 1.3.2 Run-time analysis
    [Show full text]
  • Essentials of Programming Languages Third Edition Daniel P
    computer science/programming languages PROGRAMMING LANGUAGES ESSENTIALS OF Essentials of Programming Languages third edition Daniel P. Friedman and Mitchell Wand ESSENTIALS OF This book provides students with a deep, working understanding of the essential concepts of program- ming languages. Most of these essentials relate to the semantics, or meaning, of program elements, and the text uses interpreters (short programs that directly analyze an abstract representation of the THIRD EDITION program text) to express the semantics of many essential language elements in a way that is both clear PROGRAMMING and executable. The approach is both analytical and hands-on. The book provides views of program- ming languages using widely varying levels of abstraction, maintaining a clear connection between the high-level and low-level views. Exercises are a vital part of the text and are scattered throughout; the text explains the key concepts, and the exercises explore alternative designs and other issues. The complete LANGUAGES Scheme code for all the interpreters and analyzers in the book can be found online through The MIT Press website. For this new edition, each chapter has been revised and many new exercises have been added. Significant additions have been made to the text, including completely new chapters on modules and continuation-passing style. Essentials of Programming Languages can be used for both graduate and un- dergraduate courses, and for continuing education courses for programmers. Daniel P. Friedman is Professor of Computer Science at Indiana University and is the author of many books published by The MIT Press, including The Little Schemer (fourth edition, 1995), The Seasoned Schemer (1995), A Little Java, A Few Patterns (1997), each of these coauthored with Matthias Felleisen, and The Reasoned Schemer (2005), coauthored with William E.
    [Show full text]
  • A Transprecision Floating-Point Cluster for Efficient Near-Sensor
    1 A Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Fellow, IEEE, Davide Rossi, Member, IEEE, and Giuseppe Tagliavini, Member, IEEE Abstract—Recent applications in the domain of near-sensor computing require the adoption of floating-point arithmetic to reconcile high precision results with a wide dynamic range. In this paper, we propose a multi-core computing cluster that leverages the fined-grained tunable principles of transprecision computing to provide support to near-sensor applications at a minimum power budget. Our design – based on the open-source RISC-V architecture – combines parallelization and sub-word vectorization with near-threshold operation, leading to a highly scalable and versatile system. We perform an exhaustive exploration of the design space of the transprecision cluster on a cycle-accurate FPGA emulator, with the aim to identify the most efficient configurations in terms of performance, energy efficiency, and area efficiency. We also provide a full-fledged software stack support, including a parallel runtime and a compilation toolchain, to enable the development of end-to-end applications. We perform an experimental assessment of our design on a set of benchmarks representative of the near-sensor processing domain, complementing the timing results with a post place-&-route analysis of the power consumption. Finally, a comparison with the state-of-the-art shows that our solution outperforms the competitors in energy efficiency, reaching a peak of 97 Gflop/s/W on single-precision scalars and 162 Gflop/s/W on half-precision vectors. Index Terms—RISC-V, multi-core, transprecision computing, near-sensor computing, energy efficiency F 1 INTRODUCTION HE pervasive adoption of edge computing is increas- point implementation of linear time-invariant digital filters T ing the computational demand for algorithms targeted described in [4]).
    [Show full text]