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Nanofabrics: Spatial Computing Using Molecular Electronics

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Nanofabrics: Spatial Computing Using Molecular Electronics To Appear in Proc. of The 28th Annual International Symposium on Computer Architecture, June 2001. NanoFabrics: Spatial Computing Using Molecular Electronics Seth Copen Goldstein and Mihai Budiu Carnegie Mellon University g fseth,mihaib @cs.cmu.edu Abstract compile time (which is inexpensive) for manufacturing pre- cision (which is expensive). We achieve this through a com- The continuation of the remarkable exponential in- bination of reconfigurable computing, defect tolerance, ar- creases in processing power over the recent past faces immi- chitectural abstractions and compiler technology. The result nent challenges due in part to the physics of deep-submicron will be a high-density low-power substrate which will have CMOS devices and the costs of both chip masks and future inherently lower fabrication costs than CMOS counterparts. fabrication plants. A promising solution to these problems Using EN to build computer systems requires new ways is offered by an alternative to CMOS-based computing, of thinking about computer architecture and compilation. chemically assembled electronic nanotechnology (CAEN). CAEN differs from CMOS: CAEN is extremely unlikely In this paper we outline how CAEN-based computing to be used to construct complex aperiodic structures. We can become a reality. We briefly describe recent work introduce an architecture based on fabricating dense regu- in CAEN and how CAEN will affect computer architec- lar structures, which we call nanoBlocks, that can be pro- ture. We show how the inherently reconfigurable nature grammed after fabrication to implement complex functions. of CAEN devices can be exploited to provide high-density We call an array of connected nanoBlocks a nanoFabric. chips with defect tolerance at significantly reduced manu- Compared to CMOS, CAEN-based devices have a facturing costs. We develop a layered abstract architecture higher defect density. Such circuits will thus require built-in for CAEN-based computing devices and we present prelim- defect tolerance. A natural method of handling defects is to inary results which indicate that such devices will be com- first configure the nanoFabric for self-diagnosis and then to petitive with CMOS circuits. implement the desired functionality by configuring around 1 Introduction the defects. Reconfigurabilty is thus integral to the oper- ation of the nanoFabric. Their nature makes nanoFabrics We are approaching the end of a remarkably success- particularly well suited for reconfigurable computing. ful era in computing: the era where Moore’s Law reigns, Reconfigurable computing changes as needed the func- where processing power per dollar doubles every year. This tion of programmable logic elements and their connections success is based in large part on advances in complemen- to storage, building efficient, highly parallel processing ker- tary metal-oxide semiconductor (CMOS)-based integrated nels, tailored for the application under execution. The net- circuits. Although we have come to expect, and plan for, work of processing elements is called a reconfigurable fab- the exponential increase in processing power in our every- ric. The data used to program the interconnect and process- day lives, today Moore’s Law faces imminent challenges ing elements is called a configuration. Examples of current both from the physics of deep-submicron CMOS devices reconfigurable fabrics are commercial Field Programmable and from the costs of both chip masks and next-generation Gate Arrays (FPGAs) such as [39, 2], and research proto- fabrication plants. types, e.g. Chimaera [40] and PipeRench [18]. As we show A promising alternative to CMOS-based computing un- later, one advantage of nanoFabrics over CMOS-based re- der intense investigation is chemically assembled electronic configurable fabrics is that the area overhead for supporting nanotechnology (CAEN), a form of electronic nanotechnol- reconfiguration is virtually eliminated. This will magnify ogy (EN) which uses self-alignment to construct electronic the benefits of reconfigurable computing, yielding comput- circuits out of nanometer-scale devices that take advantage ing devices that may outperform traditional ones by orders of quantum-mechanical effects [10, 30]. In this paper we of magnitude in many metrics, such as computing elements show how CAEN can be harnessed to create useful compu- per cm ¾ and operations per watt. ½¼ tational devices with more than ½¼ gate-equivalents per In the next section we present some recent research re- cm¾ . The fundamental strategy we will use is to substitute sults, which indicate CAEN will be a successful technol- ogy for implementing computing devices. We next analyze out CMOS transistor2. A simple logic gate or an static how the unique features of CAEN devices can be exploited, memory cell requires several transistors, separate p- and n- 5 and how their limitations can be circumvented. In Sec- wells, etc., resulting in a factor of ½¼ difference in density tion 3 we present an architecture that utilizes the capabil- between CAEN and CMOS. CAEN devices use much less ities of CAEN devices without requiring Herculean fabri- power, since very few electrons are required for switching. cation technology. In Section 4 we describe our top-level CAEN devices are particularly suited for reconfigurable architectural abstraction, the Split-Phase Abstract Machine computing since the configuration information for a switch (SAM), which enables fast compilation of large programs. does not need to be stored in a device separately from the The simulation results in Section 5 indicate that the SAM switch itself [10]. On the other hand, A CMOS-based re- abstraction does not hide the efficiency of the nanoFabric. configurable device requires a static RAM cell to controls each pass transistor. Also, two sets of wires are needed in 2 Electronic Nanotechnology CMOS: one for addressing the configuration bit and one for the actual signals. Perhaps a more realistic comparison of While CMOS fabrication will soon hit a wall due CAEN is to floating-gate technology which also stores the to a combination of economic and technical factors, 1 configuration information at the transistor itself. Like tradi- we are nowhere near the theoretical limits of physical tional transistors, floating-gate transistors also require two computation[17]. In order to achieve these limits at room sets of wires. Furthermore, A CAEN switch behaves like temperature we must work in the nanoscale regime, which a diode, but a floating gate transistor is bi-directional, and currently involves various technologies that exploit the thus less useful for building programmable logic. quantum-mechanical effects of small devices. Among these Electronic nanotechnology is quickly progressing and are single-electron transistors [9], nanowire transistors [11], promises incredibly small, dense, and low-power devices. quantum dots [37], quantum cellular automata [23], res- Harnessing this power will require new ways of thinking onant tunneling devices [6], negative differential resistors about the manufacturing process. We will no longer be (NDR) [7], and reconfigurable switches [8, 10]. In all cases, able to manufacture devices deterministically; instead, post- the fabricated devices are on the order of a few nanome- fabrication reconfiguration will be used to determine the ters. Given the small sizes involved, these devices must properties of the device and to avoid defects. be created and connected through self-assembly and self- alignment instead of lithography. 2.1 Fabrication and Architectural Implications In this paper we limit ourselves to molecular devices which have I-V characteristics similar to those of their Here we briefly outline a plausible fabrication process. bulk counterparts. For example, the basis of rectifica- The process is hierarchical, proceeding from basic compo- tion is different between a silicon-based p-n junction diode nents (e.g. wires and switches), through self-assembled ar- and a molecular diode, yet they both have similar I-V rays of components, to complete systems. In the first step, curves [4]. We choose to look at systems that can be built wires of different types are constructed through chemical from nanoscale devices with bulk-semiconductor analogs so self-assembly.3 The next step aligns groups of wires. Also that (1) we can apply our experience with standard circuits through self-assembly, two planes of aligned wires will be to the system and (2) we can model the system with stan- combined to form a two-dimensional grid with configurable dard tools such as SPICE. molecular switches at the crosspoints. The resulting grids While there are still many challenges left in creating will be on the order of a few microns. A separate process fully functional EN computing devices, recent advances in- will create a silicon-based die using standard lithography. dicate that EN could be a very successful post-CMOS tech- The circuits on this die will provide power, clock lines, an nology. Several groups have recently demonstrated CAEN I/O interface, and support logic for the grids of switches. devices that are self-assembled or self-aligned (or both) [10, The die will contain “holes” in which the grids are placed, 28, 16, 32]. Advances have also been made in creating aligned, and connected with the wires on the die. wires out of single-wall carbon nanotubes and aligning Using only self-assembly and self-alignment restricts them on a silicon substrate [36, 29]. Even more practical us to manufacturing simple, regular structures, e.g., rafts is the fabrication of metal nanowires, which scale down of parallel wires or grids composed of orthogonal rafts. to 5nm and can include embedded devices [25, 27]. Com- 2For the CAEN device we assume that the nanowires are on 10nm cen- bined,these advances compel us to investigate further how ters. A CMOS transistor with a 4:1 ratio in a 70nm process, (even using to harness CAEN for computing in the post-CMOS age. Silicon on Insulator, which does not need wells) with no wires attached CAEN devices are very small: A single RAM cell will measures 210nm x 280nm. Attaching minimally-sized wires to the termi- ¾ ¾ nals increases the size to 350nm x 350nm.
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