Received 13 June 2016; revised 24 February 2017; accepted 8 March 2017. Date of publication 20 March 2017; date of current version 7 June 2017. Digital Object Identifier 10.1109/TETC.2017.2684781 NP-Dynamic Skybridge: A Fine-Grained 3D IC Technology with NP-Dynamic Logic JIAJUN SHI, MINGYU LI, MOSTAFIZUR RAHMAN, SANTOSH KHASANVIS, AND CSABA ANDRAS MORITZ J. Shi, M. Li, and C.A. Moritz are with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003 M. Rahman is with the School of Computing and Engineering, University of Missouri, Kansas City, MO 65211 S. Khasanvis is with BlueRISC Inc., Amherst, MA 01002 CORRESPONDING AUTHOR: J. SHI (
[email protected]) ABSTRACT A new 3D IC fabric named NP-Dynamic Skybridge is proposed that provides fine-grained vertical 3D integration for future technology scaling. Relying on a template of vertical nanowires, it expands our prior work to incorporate and utilize both n- and p-type transistors in a novel NP-Dynamic circuit-style compatible with true 3D integration. This enables a wide range of elementary logics leading to more compact circuits, simple clocking schemes for cascading logic stages and low buffer requirement. We detail new design concepts for larger-scale circuits, and evaluate our approach using a 4-bit nanoprocessor implemented in 16 nm technology node. A new pipelining scheme specifically designed for our 3D NP-Dynamic circuits is employed in the nanoprocessor. We compare our approach with 2D CMOS as well as state-of-the-art tran- sistor-level monolithic 3D IC (T-MI) approach. Benchmarking results for the 4-bit nanoprocessor show bene- fits of up to 56.7x density, 3.8x power and 1.7x throughput over 2D CMOS.