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Powerpc Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual

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Powerpc Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual Title Page PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual Version 2.07c October 26, 2006 ® Copyright and Disclaimer © Copyright International Business Machines Corporation 1998, 2003, 2004, 2005, 2006 All Rights Reserved Printed in the United States of America October 2006 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM PowerPC IBM Logo PowerPC Architecture ibm.com Cell Broadband Engine is a trademark of Sony Computer Entertainment, Inc. Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Java and all Java-based trademarks are trademarks of Sun Microsystems, Inc. in the United States, other countries, or both. Other company, product, and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this docu- ment was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Systems and Technology Group 2070 Route 52, Bldg. 330 Hopewell Junction, NY 12533-6351 The IBM home page can be found at ibm.com The IBM semiconductor solutions home page can be found ibm.com/chips Version 2.07c October 26, 2006 Programming Environments Manual Vector/SIMD Multimedia Extension Technology Contents List of Tables ................................................................................................................... 7 List of Figures ................................................................................................................. 9 About This Book ........................................................................................................... 15 Audience ............................................................................................................................................... 16 Organization .......................................................................................................................................... 16 Suggested Reading ............................................................................................................................... 16 General Information .............................................................................................................................. 17 PowerPC Documentation ...................................................................................................................... 17 Conventions .......................................................................................................................................... 19 Acronyms and Abbreviations ................................................................................................................ 20 Terminology Conventions ..................................................................................................................... 22 1. Overview .................................................................................................................... 23 1.1 Vector Processing Technology Overview ....................................................................................... 25 1.1.1 64-Bit Vector Processing Technology and the 32-Bit Subset ................................................ 26 1.1.2 Levels of the Vector ISA ........................................................................................................ 26 1.1.3 Features Not Defined by the Vector ISA ............................................................................... 27 1.2 Vector Processing Architectural Model ........................................................................................... 27 1.2.1 Vector Registers and Programming Model ............................................................................ 27 1.2.2 Operand Conventions ............................................................................................................ 28 1.2.2.1 Byte Ordering ................................................................................................................. 28 1.2.2.2 Floating-Point Conventions ............................................................................................ 29 1.2.3 Vector Addressing Modes ..................................................................................................... 30 1.2.4 Vector Instruction Set ............................................................................................................ 31 1.2.5 Vector Cache Model .............................................................................................................. 32 1.2.6 Vector Exception Model ......................................................................................................... 32 1.2.7 Memory Management Model ................................................................................................. 32 2. Vector Register Set ................................................................................................... 33 2.1 Overview of the Vector and PowerPC Registers ............................................................................ 33 2.2 Registers Defined by Vector ISA ..................................................................................................... 35 2.2.1 Vector Register File ............................................................................................................... 35 2.2.2 Vector Status and Control Register ....................................................................................... 36 2.2.3 VRSAVE Register (VRSAVE) ................................................................................................ 38 2.3 Additions to the PowerPC UISA Registers ...................................................................................... 39 2.3.1 PowerPC Condition Register ................................................................................................. 39 2.4 Additions to the PowerPC OEA Registers ...................................................................................... 40 2.4.1 VPU Bit in the PowerPC Machine State Register (MSR) ...................................................... 40 2.4.2 Machine Status Save/Restore Registers (SRR) .................................................................... 41 2.4.2.1 Machine Status Save/Restore Register 0 (SRR0) ......................................................... 41 2.4.2.2 Machine Status Save/Restore Register 1 (SRR1) ......................................................... 42 Version 2.07c Contents October 26, 2006 Page 3 of 329 Programming Environments Manual Vector/SIMD Multimedia Extension Technology 3. Operand Conventions ............................................................................................... 43 3.1 Data Organization in Memory .......................................................................................................... 43 3.1.1 Aligned and Misaligned Accesses ......................................................................................... 43 3.1.2 Vector Processing Unit Byte Ordering ................................................................................... 44 3.1.3 Vector Register and Memory Access Alignment .................................................................... 44 3.1.4 Quadword Data Alignment ..................................................................................................... 44 3.1.4.1 Loading an Unaligned Quadword Using Vector Permute ............................................... 45 3.1.4.2 Storing an Unaligned Quadword Using Vector Permute ................................................ 46 3.1.4.3 Loading an Unaligned Quadword Using Load Vector Left/Right .................................... 47 3.1.4.4 Storing an Unaligned Quadword Using Store Vector Left/Right Indexed ....................... 48 3.1.4.5 Scalar Loads and Stores ................................................................................................ 48 3.1.4.6 Misaligned Scalar Loads and Stores .............................................................................. 48 3.2 Vector Floating-Point Instructions—UISA ....................................................................................... 49 3.2.1 Floating-Point Modes ............................................................................................................. 49 3.2.1.1 Java Mode ...................................................................................................................... 49 3.2.1.2 Non-Java Mode .............................................................................................................
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