Applying Digital Technology to PWM Control-Loop Designs Mark Hagen and Vahid Yousefzadeh
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Applying Digital Technology to PWM Control-Loop Designs Mark Hagen and Vahid Yousefzadeh ABSTR A CT This topic discusses the application of digital-control to DC/DC-switching converters and how to model the digitally controlled system. The main blocks that appear in almost every digital controller—the error ADC, the compensator, and the digital PWM engine—are discussed and used to model small-signal characteristics such as frequency response, stability criteria, the effects of quantization, as well as the impact of sampling rate and delay introduced by the digital controller to the system. This model is extended to include nonlinear gain and its benefits. Finally, a graphical user interface is introduced and demonstrated for use with the design of a two-phase synchronous-buck converter. I. INTRODUCT I ON regulation. Fig. 1 shows a typical analog controller Switch-mode power-supply (SMPS) converters that uses analog feedback to provide output voltage find use in a wide variety of applications, ranging regulation. from a fraction of a milliwatt in on-chip power Over the past few decades, digital controllers management to hundreds of megawatts in power in the form of digital-signal processors (DSPs), systems. All of these applications require efficient microcontrollers, and field-programmable gate and cost-effective static and dynamic power arrays (FPGAs) have seen extensive application in regulation over a wide range of operating motor-drive controllers and high-voltage and high- conditions. An analog or digital controller closes current power electronics. In these applications the feedback loop around the switching converter the control algorithms are generally sophisticated, and actively controls the on/off states of the power- while the semiconductor devices operate at semiconductor devices to achieve input or output relatively low switching frequencies, e.g. at tens of kilohertz. L1 R L1 i1 L2 RL2 i2 Vout Vg RESR + R – + VC C – Compensator PWM d(t) + e(t) + + – 7 Topic – – + + Vramp + Vramp Vref – 12– – Fig. 1. Analog-controlled SMPS. 7-1 L1 R L1 i1 L2 RL2 i2 Vout Vg RESR + R – + VC – C ...c1 c2 Vsense – e[n] Digital d[n] Compensator Error e(t) PWM GC(z) ADC + Vref DAC Set/Measure V;out Monitor Processing Memory Communication Report I,in I,out ADC Unit Temperature and Faults Fig. 2. Digital controller in an SMPS. Continued rapid advances in CMOS and VLSI width modulator (DPWM) that converts the technology have enabled the development of a sampled, compensated error signal into the gate- high-performance, practical, cost-effective, and drive signals. low-power digital SMPS controller. Fig. 2 shows a Because most digital controllers contain a block diagram of an advanced digital controller serial interface, they can be easily configured that closes the feedback around a SMPS. Such a from design software. This allows the design controller, because it is implemented in a digital software to do the “heavy lifting” in terms of silicon technology, usually includes a standard modeling the system and calculating appropriate communication block; general-purpose ADCs compensation for the SMPS. In this topic we (ADCs); digital I/Os; memory; and a processing discuss the what goes on “under the covers” of the unit (microcontroller) that handles programming, design software. communication, diagnostics, power management, etc. The result is that a digital controller not only II. MODEL I NG A DIGITAL CONTROLLER regulates the output voltage, but also can perform Switch-mode power supplies have always had complex sequencing and can monitor key a digital component; they have a control effort parameters like average current and power for the with a discrete update interval. That interval is the host system. switching period. The net result is that there can This topic focuses on the use of digital be a latency in the response to disturbance in the technology to implement a SMPS controller. control effort. When we analyze a SMPS system, Specific examples are for a non-isolated point-of- this latency shows up as a rotation in the phase of load (POL) application. We first review the the open-loop system. When we introduce digital techniques necessary to model the discrete time components into the system, there are additional controller. Then the new features and functions phenomena that must be taken into account. These that digital control enables are discussed. There things are: are three specific blocks that enable the digital 1. Feedback quantization Topic 7 Topic controller to achieve the high-performance 2. Control effort quantization regulation requirements of an SMPS: the ADC 3. Delay needed to sample the feedback and used to sample the error voltage (and an associated calculate the control effort setpoint reference DAC), the digital filter that The key to implementing a digitally-controlled compensates the error signal, and the digital pulse- power supply is understanding these effects. 7-2 G(s) u[n] Vout GDelay 2 GPlant GDiv Vsense H(s) d[n]e[n] Ve Vr KPWM GDelay 1 GCLA KNLR KEADC KAFE + KDAC ref Fig. 3. Closed-loop block diagram. Fig. 3 shows the closed-loop block diagram TA BLE 1. CLOSED -LOO P SYSTE M for a digitally controlled SMPS that first generates CONTR I BUTORS an analog error voltage and then digitizes that KAFE Analog front-end gain in V/V voltage to calculate the PWM control effort. For K Error ADC gain in LSB/volt this system the total open-loop gain is EADC K Nonlinear boost gain Ts()=×Gs() Hs() (1) NLR GCLA Control-law accelerator (digital compensator) Then the closed-loop gain, from the PWM gain control effort, u, to the sensed output voltage, GDelay1 Total sampling and CLA computational delay v , is sense KPWM PWM gain in duty/LSB vsense Gs() G On-time and any delay to multiple power stages = (2) Delay2 u 1+ Gs()× Hs() driving Vout GPlant* Transfer function from the time location of the The contributors to the closed-loop system are falling edge of the PWM signal to Vout of the itemized in Table 1. To determine the frequency power stage response of the power supply, and from that, GDiv Divider network transfer function in V/V determine the stability margin of the system, we *The frequency response of the plant is derived from the need to define the dynamic gain for each block. average model of the power stage(s). Once we have the transfer function for each block, the standard measure of stability can be applied: III. POWER -ST A GE MODEL I NG • Gain Margin—The inverse of the magnitude of the open-loop gain, expressed in dB, at the The development of the frequency response of frequency where the phase of the open-loop the plant is identical for analog or digitally- gain is 180 degrees. controlled power supplies. It is derived for the • Phase Margin—The phase of the open-loop average model of the power stage(s). For a buck gain, expressed in degrees, where the magnitude regulator, such as used in the POL power supply, of the open-loop gain is 1.0 (0 dB). the continuous-mode, small-signal-transfer function is simply In addition to developing a frequency-domain vout model of the system, it is important to develop a Gs()==VG× ()s , (3) plant duty in LC time-domain model of the digitally-controlled power supply so that the effects of quantization where G (s) is the transfer function of the LC 7 Topic can be observed. In the following sections we will LC low-pass filter and load resistance of the power work our way around the feedback loop and stage. develop the necessary description of each There are several reasons that the derived functional block so that both a frequency-domain frequency response of the average model may be model and a time-domain model can be created. insufficient when designing a digitally-controlled 7-3 power supply. Digital control introduces A. Review of the Average Model quantization of the error voltage and quantization Switch averaging removes the switching of the output-PWM control effort. There also are ripples in the inductor-current and capacitor- additional delays in a digital system such as the voltage waveforms over the switching period. The time it takes to convert the error voltage to a following equations define the low-frequency numerical value, and the time it takes the digital components of the inductor and capacitor filter to calculate the control effort. Finally, waveforms: processing the error signal digitally enables non- diL ()t linear gains to be applied to the signal. All of these Ts L = vtL () , and dt Ts effects are best observed in a time model of the (4) system. dvC ()t Ts A time-domain model of the system should C = itC () , dt Ts describe how variations in input voltage, load current, and duty cycle affect the output voltage. where Since the power stage of a switching converter forms a nonlinear system, designing a linear xt() Ts controller usually involves linearizing this power stage. The traditional approach uses average denotes the average of x(t) over an interval of one modeling to provide a dynamic model for PWM- switching period, Ts: operated DC/DC converters [1]. The frequency tT+ s range of interest is much smaller than the switching xt() = xd()ττ. (5) Ts ∫t frequency, so the model ignores the switching frequency and its harmonics. The small-signal Although averaging removes the high- linear model of the power stage is easily derived frequency switching ripple, the average value still from the average model. varies from one switching period to the next so as Although a linearized model based on switch to model low-frequency variations.