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United States Patent (19) (11) 4,445,170 Hughes Et Al

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United States Patent (19) (11) 4,445,170 Hughes Et Al United States Patent (19) (11) 4,445,170 Hughes et al. 45 Apr. 24, 1984 54 COMPUTER SEGMENTED MEMORY Specification-Preliminary, Zilog, Inc., Cupertino, Oct. MANAGEMENT TECHNIQUE WHEREN 1979. TWO EXPANDABLE MEMORY PORTIONS Z8010 MMU Memory Management Unit, Technical ARE CONTAINED WITHNA SINGLE Manual-Preliminary, Zilog, Inc., Cupertino, Oct. 1980. SEGMENT Z8000 PLZ/ASM, Assembly Language Programming 75) Inventors: Ronald P. Hughes, Santa Clara; Manual, Zilog, Inc., Cupertino, Apr. 1979, pp. iii, v-ix, Douglas G. Swartz, Cupertino; Bruce 1-1 to 1-14. E. Weiner, Palo Alto, all of Calif. Primary Examiner-Raulfe B. Zache (73) Assignee: Zilog, Inc., Campbell, Calif. Attorney, Agent, or Firm-Majestic, Gallagher, Parsons 21 Appl. No.: 245,483 & Siebert (22 Filed: Mar. 19, 1981 (57) ABSTRACT Separate memory management units are described for 51) Int. Cl. ................................................ G06F 3/00 use with a central processing unit to separately control 52) U.S. Cl. .................................................... 364/200 expanding stack and data memory portions within a (58) Field of Search. 364/200 MS File, 900 MS File single logical memory segment. The stack and data (56) References Cited portions are prevented from expanding into each other by a break register which contains an address between U.S. PATENT DOCUMENTS the two memory portions and is updated as the stack 3,510,847 5/1970 Carlson ............................... 364/200 and data memory portions expand and contract. The 3,787,813 1/1974 Cole ........... ... 364/200 stack memory management unit only is enabled when a 4,037,215 7/1977 Birney ... ...... 364/200 portion of the memory is addressed on one side of the 4,177,510 12/1979 Appell ................................. 364/200 break value while the data memory management unit 4,268,903 5/1981 Miki .................................... 364/200 only is utilized when the address is on the other side of OTHER PUBLICATIONS the break value. Z8010 MMU Memory Management Unit, Product 11 Claims, 2 Drawing Figures U.S. Patent ,170 MOT](JBC]}}OSSEHOOVLÅE3. U.S. Patent Apr. 24, 1984 Sheet 2 of 2 4,445,170 USER STACK LOGICAL SEG ENT PHYSICAL 63 67 USER STACK PHYSICAL SEGMENT C 65 PHYSICAL LOGICAL SEGMENT B SEGMENT A PHYSICAL 47 SEGMENT A 6 FIG. 2. 4,445,170 1. 2 CPU depending upon whether that address is above or COMPUTER SEGMENTED MEMORY below the break address value stored in the register. MANAGEMENTTECHNIQUE WHEREIN TWO This break value may be updated to reflect the changing EXPANDABLE MEMORY PORTIONS ARE relative sizes of the memory portions. By being able to CONTAINED WITHNA SINGLE SEGMENT include two variable size memory portions within a single logical memory segment, more of the limited BACKGROUND OF THE INVENTION physical memory is then available to the programmer This invention relates generally to computer and for other uses. microcomputer systems structure, particularly to a cir Other advantages, objects and features of the various cuit technique for managing the computer system mem 10 aspects of the present invention are set forth in connec ory. tion with the following description of their preferred It is a common goal in any computer system, particu embodiments, which should be taken in conjunction larly in a microcomputer system, to minimize the with the accompanying drawings. amount of random access memory (RAM) that is re quired since memory elements are an expensive part of BRIEF DESCRIPTION OF THE DRAWINGS any system. At the same time, it is a goal of any com FIG. 1 is a block schematic diagram of a memory puter structure to provide flexibility in programming so management circuit improvement according to the that the limitations on memory size do not create added problems for the programmer. As a result, a technique present invention; and has been employed of using a separate memory manage 20 FIG. 2 illustrates both logical and physical memory ment unit (MNU) disposed between the microprocessor utilization by the circuit of FIG. 1. or other central processing unit (CPU) and the RAM. DESCRIPTION OF THE PREFERRED Use of the MMU allows the program to call for data in EMBODIMENT the memory at "logical” addresses that are converted by it to "physical' memory addresses where the data 25 FIG. 1 shows in block diagram form the schematic actually resides. The physical memory actually allo diagram of a computer system utilizing the circuit im cated is generally much less than the logical memory provements of the present invention. In this example, assumed to be available by the program. Thus, the the micro computer system is shown wherein the cen MMU is an important element in efficiently using the tral processing unit is a microprocessor 11 available as a physical memory available to carry out the software 30 single integrated circuit from Zilog, Inc., its Z8001 operations commanded of the system. microprocessor. The microprocessor communicates As a particular example of such a system, the Z8001 with a semiconductor RAM 13 of a standard type. The microprocessor available from Zilog, Inc. is utilized computer system would normally operate in conjunc with one or more Zilog Z8010 MMU memory manage tion with some magnetic media memory, such as floppy ment units. This particular microprocessor designates 35 discs or tape, but this is not shown in FIG. 1. The por on a segment bus one of 128 different logical memory tion of a complete computer system shown in FIG. 1 is segmen in which a particular location within the seg that which allows the microprocessor 11 to address ment is designated on an address bus. Each of the 128 particular portions of the memory 13. In that connec segments may have up to 64 K bytes of memory. The tion, three Z8010 memory management units 15, 17 and MMU may be utilized to control the size of each seg 19 are employed. Other portions of a complete com ment of the memory in increments of 256 bytes. The puter system, such as data paths and elements for ma MMU contains a register for each of 64 memory seg nipulating data, are not shown but are well known. ments that designates for the physical memory the ac There are many publications available which de tual beginning address of each physical segment as well scribe the structure and use of the commercially avail as the size of that segment. The MMU's ability to con 45 able microprocessor and memory management units of trol that size is useful for stack or variable size data Zilog, Inc. Examples of this are manuals available from memories. A variable stack memory size, for example, Zilog, Inc. itself. Two such manuals relating to the would occupy one of the 128 logical memory segments, Z8001 microprocessor and associated circuits are the resulting in eliminating usable logical memory within "Z8000 CPU Technical Manual' dated August, 1980 that segment that is outside the size of the stack. 50 and the "Z8000 PLZ/ASM Assembly Language Pro It is a primary object of the present invention to pro gramming Manual" dated April, 1979. A copy of pages vide an improved memory management system that 1-1 through 1-14 of the latter identified manual is better utilizes the available logical and physical memory reproduced as Appendix II hereto. The memory man space. agement units are described to some extent in those 55 publications and in more detail in the following two SUMMARY OF THE INVENTION publications: "Z8010 MMU Memory Management Briefly, the improvement of the present invention Unit, Product Specification', October, 1979, and utilizes two separate memory management units that are "Z8010 MMU Memory Management Manual, Techni operated one at a time to control the same logical mem cal Unit,' dated October, 1980. These four publications ory segment. Each of the portions of the memory seg are expressly incorporated by reference herein. ment controlled by each of the MMU's can be expand This particular type of microprocessor 11 includes a ing, thus making it possible to provide an expanding 16 bit address bus, the least significant bits being carried stack and an expanding data memory within a single by a bus 21 and the most significant bits being carried by logical memory segment. Overlapping of these two a bus 23, the address bus being shown as these two memory portions is prevented by a break register that 65 separate buses for ease of explanation. In addition, the contains an address within the segment that divides the microprocessor has a memory segment bus 25. The left two portions, one of the MMU's being enabled in re hand column of FIG. 2 shows a representation of the sponse to a particular address access command from the two of the available 128 logical memory segments that 4,445,170 3. 4. can be accessed individually by the appropriate code on tions of segment "A" are being accessed are made by the memory segment bus 25. The two logical segments the comparator 33 and its output control signals. Simi designated as "A" and "B" in FIG. 2 are shown for larly, the user register 29 contains an address for use explanation purposes. The microprocessor 11 views the with the memory logical segment "B". The stack MMU memory 13 as if it contained 128 such segments, each up 17 has one of its 64 segment descriptor registers devoted to 64 K bytes in size, but the physical memory 13 may to logical segment "A" and another of the registers contain less or a large memory will be accessed by devoted to logical segment "B". The MMU begins with several different users, thus making only a portion of it a reference logical address at the top of the segment and available to a given microprocessor.
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