DOCSLIB.ORG

ARM Mali GPU Midgard Architecture

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
ARM Mali GPU Midgard Architecture Title 44pt sentence case ARM Mali GPU Midgard Architecture Mathias Palmqvist Affiliations 24pt sentence case Senior Software Engineer/ARM MPG 20pt sentence case Lund University, Faculty of Engineering LTH December 6th 2016 © ARM 2016 Title 40pt sentence case Agenda Bullets 24pt sentence case . Midgard Architecture Overview . Power Consumption & Bandwidth Reduction Sub-bullets 20pt sentence case . Device Driver Work building . Power Consumption . Forward Pixel Kill . GPU Software Interface . Transaction Elimination . GPU Hardware Jobs . ARM Framebuffer Compression . Job Manager . Pixel local storage . Unified Shader Core . Shader Core: Vertex Work . ARM Lund . Tiling Unit . ARM Lund GPU teams . Shader Core: Fragment Work . GPU HW/SW development . Shader Core: Tripipe . Party! . Student Oppurtunities 2 © ARM 2016 Title 40pt sentence case Mathias Palmqvist Bullets 24pt sentence case Work Interests Sub-bullets 20pt sentence case . Senior Software Engineer, ARM ~5 years • Game Development(often non-graphics related) GPU driver, EGL on Android/X11, Multimedia. • Real-time techniques with mobile focus . Previously at Sony Ericsson 7 years Personal Android Graphics Integration. • Married to California girl from UCSD since 13 Education years • Two children, 5 and 2. Aiden and Avery. LTH, M.S.EE (e98). Fourth year at U.C. San Diego. Hardware and graphics main focus. 3 © ARM 2016 Text 54pt sentence case Midgard GPU Architecture 4 © ARM 2016 Title 40pt sentence case Acrynoms Bullets 24pt sentence case AMBA Advanced Microcontroller Bus Architecture Sub-bullets 20pt sentence case AXI AMBA Advanced eXtensible Interface APB AMBA Advanced Peripherial Bus ACE AMBA AXI Coherency Extensions GPU Graphics Processing Unit VPU Video Processing Unit DPU Display Processing Unit ISA Instruction Set Architecture SIMD Single Instruction Multiple Data 5 © ARM 2016 Title 40pt sentence case Midgard Architecture Overview Bullets 24pt sentence case . Tile-based, Unified Shading Architecture Sub-bullets 20pt sentence case . Latest Midgard GPU is T880 . Maximum of 16 shader cores . Tile size 16x16 (4x4-32x32 internally) . GLES 3.2, Vulkan 1.0, CL 1.2, DX FL11_2 . MSAA 4x, 8x,16x . T880 in Samsung GS7 and Huawei P9 . First product T604 in 2011q4 . SoC: Samsung Exynos 5250 . Products: Nexus10, Samsung Chromebook 6 © ARM 2016 Title 40pt sentence case GPU top level Bullets 24pt sentence case Interconnect Sub-bullets 20pt sentence case Shader Shader Shader core Job corecore MMU Tiling Unit Manager Interconnect L2 Cache #0 L2 Cache #1 Driver External Shared Memory 7 © ARM 2016 Title 40pt sentence case Simplified Application-Driver Interaction Bullets 24pt sentence case Sub-bullets 20pt sentence case App Frame 0 Frame 1 Frame 2 Frame 3 Flushed Flushed Flushed Flushed Driver F0 F1 F2 F3 Scheduled Scheduled Scheduled GPU F0 F1 F2 Post Post Post DPU F0 F1 8 © ARM 2016 Title 40pt sentence case Driver building GPU resource structures App Driver Tex Structure Shader1 Structure Bullets 24pt sentence case glTexImageX() Build Texture structure Format, Dimensions ProgramPointer Sub-bullets 20pt sentence case Data Pointer Buffer Structure glShaderX() Build Shader structure Format, Dimensions Data Pointer VertexJob1 Structure VertexJob2 glBufferX() Build Vertex/Index BufferStructure Pointer Index Pointer buffer structures Shader2 Structure Buffer Pointer Shader Pointer ProgramPointer Index Pointer glDraw() Build Vertex Job Structure Shader Pointer glShaderX() Link with vertex/index/shader glDraw() structures FragmentJob ... Structure eglSwapBuffers() Build Fragment Job Structure FrameBuffer Pointer Link with FB and last Vertex Job Last Job Pointer 9 © ARM 2016 Title 40pt sentence case GPU hardware job types Vertex Job(V) Vertex shader running on a set of vertices Bullets 24pt sentence case Sub-bullets 20pt sentence case Tiler Job(T) Tiling Unit (Fixed Function) work to split transformed primitives into affected tiles Fragment Job(F) Single render target job running over all tiles Job Chain A chain of jobs Job Chain 1 Job Chain 2 V V V V T T T T F 10 © ARM 2016 Title 40pt sentence case GPU job progression Bullets 24pt sentence case Sub-bullets 20pt sentence case 11 © ARM 2016 Title 40pt sentence case GPU Software Interface CPU GPU Bullets 24pt sentence case Job Sub-bullets 20pt sentence case Kernel User A Manager MMU P Power B Interrup Submit tJobs chains AXI External Shared Memory AXI VertexJob1 Structure TilingJob1 Structure FragmentJob Structure VertexJob2 Structure TilingJob2 Structure 12 © ARM 2016 Title 40pt sentence case Job Manager VertexJob (96 vertices) TilingJob FragmentJob (Full Frame) Bullets 24pt sentence case Sub-bullets 20pt sentence case Job Manager VTask1(32) VTask2(32) VTaskN(32) TTask1 FTask1(Tile1) FTask2(Tile2) VTaskN TTaskN FTask3 VTask2 TTask2 FTask2 Shader Core VTask1 TTask1 FTask1 Shader Core Shader Core Shader Core Shader Core Tiling Unit Shader Core External Shared Memory 13 © ARM 2016 Title 40pt sentence case Unified Shader Core Vertex Frontend Fragment Frontend External Shared Memory Bullets 24pt sentence case Sub-bullets 20pt sentence case Tiler Data Tripipe Attributes/Uniforms in Varyings out Textures Framebuffer Tile Tile Buffer TileBuffer Fragment Backend Buffer 14 © ARM 2016 Title 40pt sentence case Shader Core: Vertex Work Vertex Thread Creator . Vertex Threads do not write to tile buffers but Bullets 24pt sentence case directly to main memory Sub-bullets 20pt sentence case Thread 1 Thread 2 . Vertex Tasks contain multiple of 4 vertices Thread 3 Thread 4 External Shared Memory Attributes/Uniforms in Varyings out 15 © ARM 2016 Title 40pt sentence case Tiling Unit Tiler’s goal Hierarchy Level 0 - 16x16 tile bins Bullets 24pt sentence case Hierarchy Level 1 - 32x32 tile bins Find out what tiles are covered by a Sub-bullets 20pt sentence case Hierarchy Level 2 - 64x64 tile bins primtive. Update tile structure with that info. 1 2 3 4 5 Assumptions 6 7 8 9 10 Small primitive -> Affect few tiles -> Use low hierarchy 11 12 13 14 15 level -> Save read bandwidth Large primitive -> Affect many tiles -> Use high 16 17 18 19 20 hierarchy level -> Save write bandwidth 21 22 23 24 25 Heuristic approach Determine what is best given distribution 16 © ARM 2016 Title 40pt sentence case Shader Core: Fragment Work Fragment Front-End Fragment Back-End Bullets 24pt sentence case Polygon List Reader Sub-bullets 20pt sentence case Depth-bounds & Hierarchical ZS Test Tile Writeback Rasterizer Tile Memory Early ZS Testing FPK Queue (128 Quads) Blending Fragment Thread Creator Tripipe Late ZS Testing 17 © ARM 2016 Title 40pt sentence case Shader Core: Tripipe details Bullets 24pt sentence case . SIMD processing core that executes Sub-bullets 20pt sentence case instructions from the Midgard ISA . 3 types of pipes, but 5 total . 3 Arithmetic . 1 Load/Store . 1 Texture . 128-bit operands, float or integer . 2xFP64, 4xFP32, 8xFP16 . Up to 256 active threads at the same time 18 © ARM 2016 Power Consumption Text 54pt sentence case and Bandwidth Reduction 19 © ARM 2016 Title 40pt sentence case Power Consumption Approximate GPU power Bullets 24pt sentence case . Power comparision consumption distribution Sub-bullets 20pt sentence case . Phone SoC 1-3W TexturePipe . Tablet ~10W ArithmeticPipes . Desktop Gfx card ~100-200W Other . Constraints . Battery life time & heat dissapation . Static and Dynamic power consumption . Static power. Related to technology and area. Improved through power management(gating) . Dynamic power. Heavily tied to use case. Responsability of designer. Performance Density FPS/mm^2. Smaller Area and less dynamic power -> possibly more cores 20 © ARM 2016 Title 40pt sentence case Reduce Overdraw: Forward Pixel Kill Bullets 24pt sentence case Sub-bullets 20pt sentence case Insert small FIFO for 2x2 quads after EarlyZ but before entering tripipe. Reject quads ”in front” before they reach expensive tripipe execution 21 © ARM 2016 Title 40pt sentence case Transaction Elimination . Signature/Hash calculated of color tilebuffer before write-out and saved. Bullets 24pt sentence case Sub-bullets 20pt sentence case . If it matches previous signature, write-out is skipped saving bandwidth. 22 © ARM 2016 Title 40pt sentence case ARM Framebuffer Compression/AFBC . Real-time, lossless, small-area framebuffer compression technology Bullets 24pt sentence case Sub-bullets 20pt sentence case . Used on both external(window) and internal(FBO) buffers for GPU . Formats: RGB/YUV (including 10-bit), depth/stencil 23 © ARM 2016 Title 40pt sentence case EXT_shader_pixel_local_storage Bullets 24pt sentence case . Bandwidth Efficient Deferred Shading Sub-bullets 20pt sentence case . Define G-Buffer in Pixel Local Storage space(in tile memory) G-Buffer initialization Lighting accumulation Final shading 24 © ARM 2016 Text 54pt sentence case ARM Lund 25 © ARM 2016 Title 40pt sentence case ARM Lund GPU teams Bullets 24pt sentence case . Hardware design/verification 15 (Fragment front/back-end) Sub-bullets 20pt sentence case . GPU Modelling 17 . Graphics/Backend Compiler team 16 . HW/SW regression testing 10 . Multimedia(GPU+VPU+DPU) development+regression 4 ARM Lund total ~100. Remaining are Video IP development. Cambridge/Trondheim major GPU development sites 26 © ARM 2016 Title 40pt sentence case GPU HW Development Bullets 24pt sentence case . HDL: Verilog + System Verilog Sub-bullets 20pt sentence case . git/gerrit . Cluster based RTL simulation framework . HW Engineers usually with low-spec desktop/laptop. Everything runs on massive CPU clusters in Cambridge 27 © ARM 2016 Title
Load more

Recommended publications
  • GPU Developments 2018
    GPU Developments 2018 2018 GPU Developments 2018 © Copyright Jon Peddie Research 2019. All rights reserved. Reproduction in whole or in part is prohibited without written permission from Jon Peddie Research. This report is the property of Jon Peddie Research (JPR) and made available to a restricted number of clients only upon these terms and conditions. Agreement not to copy or disclose. This report and all future reports or other materials provided by JPR pursuant to this subscription (collectively, “Reports”) are protected by: (i) federal copyright, pursuant to the Copyright Act of 1976; and (ii) the nondisclosure provisions set forth immediately following. License, exclusive use, and agreement not to disclose. Reports are the trade secret property exclusively of JPR and are made available to a restricted number of clients, for their exclusive use and only upon the following terms and conditions. JPR grants site-wide license to read and utilize the information in the Reports, exclusively to the initial subscriber to the Reports, its subsidiaries, divisions, and employees (collectively, “Subscriber”). The Reports shall, at all times, be treated by Subscriber as proprietary and confidential documents, for internal use only. Subscriber agrees that it will not reproduce for or share any of the material in the Reports (“Material”) with any entity or individual other than Subscriber (“Shared Third Party”) (collectively, “Share” or “Sharing”), without the advance written permission of JPR. Subscriber shall be liable for any breach of this agreement and shall be subject to cancellation of its subscription to Reports. Without limiting this liability, Subscriber shall be liable for any damages suffered by JPR as a result of any Sharing of any Material, without advance written permission of JPR.
    [Show full text]
  • Mali-400 MP: a Scalable GPU for Mobile Devices
    Mali-400 MP: A Scalable GPU for Mobile Devices Tom Olson Director, Graphics Research, ARM Outline . ARM and Mobile Graphics . Design Constraints for Mobile GPUs . Mali Architecture Overview . Multicore Scaling in Mali-400 MP . Results 2 About ARM . World’s leading supplier of semiconductor IP . Processor Architectures and Implementations . Related IP: buses, caches, debug & trace, physical IP . Software tools and infrastructure . Business Model . License fees . Per-chip royalties . Graphics at ARM . Acquired Falanx in 2006 . ARM Mali is now the world’s most widely licensed GPU family 3 Challenges for Mobile GPUs . Size . Power . Memory Bandwidth 4 More Challenges . Graphics is going into “anything that has a screen” . Mobile . Navigation . Set Top Box/DTV . Automotive . Video telephony . Cameras . Printers . Huge range of form factors, screen sizes, power budgets, and performance requirements . In some applications, a huge difference between peak and average performance requirements 5 Solution: Scalability . Address a wide variety of performance points and applications with a single IP and a single software stack. Need static scalability to adapt to different peak requirements in different platforms / markets . Need dynamic scalability to reduce power when peak performance isn’t needed 6 Options for Scalability . Fine-grained: Multiple pipes, wide SIMD, etc . Proven approach, efficient and effective . But, adding pipes / lanes is invasive . Hard for IP licensees to do on their own . And, hard to partition to provide dynamic scalability . Coarse-grained: Multicore . Easy for licensees to select desired performance . Putting cores on separate power islands allows dynamic scaling 7 Mali 400-MP Top Level Architecture Asynch Mali-400 MP Top-Level APB Geometry Pixel Processor Pixel Processor Pixel Processor Pixel Processor Processor #1 #2 #3 #4 CLKs MaliMMUs RESETs IRQs IDLEs MaliL2 AXI .
    [Show full text]
  • Intel Desktop Board DG41MJ Product Guide
    Intel® Desktop Board DG41MJ Product Guide Order Number: E59138-001 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DG41MJ Product Guide February 2009 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and the receiver. • Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected.
    [Show full text]
  • GMAI: a GPU Memory Allocation Inspection Tool for Understanding and Exploiting the Internals of GPU Resource Allocation in Critical Systems
    The final publication is available at ACM via http://dx.doi.org/ 10.1145/3391896 GMAI: A GPU Memory Allocation Inspection Tool for Understanding and Exploiting the Internals of GPU Resource Allocation in Critical Systems ALEJANDRO J. CALDERÓN, Universitat Politècnica de Catalunya & Ikerlan Technology Research Centre LEONIDAS KOSMIDIS, Barcelona Supercomputing Center (BSC) CARLOS F. NICOLÁS, Ikerlan Technology Research Centre FRANCISCO J. CAZORLA, Barcelona Supercomputing Center (BSC) PEIO ONAINDIA, Ikerlan Technology Research Centre Critical real-time systems require strict resource provisioning in terms of memory and timing. The constant need for higher performance in these systems has led industry to recently include GPUs. However, GPU software ecosystems are by their nature closed source, forcing system engineers to consider them as black boxes, complicating resource provisioning. In this work we reverse engineer the internal operations of the GPU system software to increase the understanding of their observed behaviour and how resources are internally managed. We present our methodology which is incorporated in GMAI (GPU Memory Allocation Inspector), a tool which allows system engineers to accurately determine the exact amount of resources required by their critical systems, avoiding underprovisioning. We first apply our methodology on a wide range of GPU hardware from different vendors showing itsgeneralityin obtaining the properties of the GPU memory allocators. Next, we demonstrate the benefits of such knowledge in resource provisioning of two case studies from the automotive domain, where the actual memory consumption is up to 5.6× more than the memory requested by the application. ACM Reference Format: Alejandro J. Calderón, Leonidas Kosmidis, Carlos F. Nicolás, Francisco J.
    [Show full text]
  • Intel® Desktop Board DG965RY Product Guide
    Intel® Desktop Board DG965RY Product Guide Order Number: D46818-003 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DG965RY Product Guide June 2006 -002 Second release of the Intel® Desktop Board DG965RY Product Guide September 2006 -003 Added operating system support December 2006 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna.
    [Show full text]
  • Intel® Desktop Board DG41TX Product Guide
    Intel® Desktop Board DG41TX Product Guide Order Number: E88309-001 Revision History Revision Revision History Date ® -001 First release of the Intel Desktop Board DG41TX Product Guide February 2010 Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel Desktop Board DG41TX may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from Intel Corporation by going to the World Wide Web site at: http://intel.com/ or by calling 1-800-548-4725. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. * Other names and brands may be claimed as the property of others.
    [Show full text]
  • The Bifrost GPU Architecture and the ARM Mali-G71 GPU
    The Bifrost GPU architecture and the ARM Mali-G71 GPU Jem Davies ARM Fellow and VP of Technology Hot Chips 28 Aug 2016 Introduction to ARM Soft IP . ARM licenses Soft IP cores (amongst other things) to our Silicon Partners . They then make chips and sell to OEMs, who sell consumer devices . “ARM doesn’t make chips”… . We provide all the RTL, integration testbenches, memories lists, reference floorplans, example synthesis scripts, sometimes models, sometimes FPGA images, sometimes with implementation advice, always with memory system requirements/recommendations . Consequently silicon area, power, frequencies, performance, benchmark scores can therefore vary quite a bit in real silicon… 2 © ARM2016 ARM Mali: The world’s #1 shipping GPU 750M 65 27 Mali-based new Mali GPUs shipped 140 Total licenses in in 2015 Total licenses licensees FY15 Mali is in: Mali graphics based IC shipments (units) 750m ~75% ~50% ~40% 550m of of of 400m DTVs… tablets… smartphones 150m <50m 2011 2012 2013 2014 2015 3 © ARM2016 ARM Mali graphics processor generations Mali-G71 BIFROST … GPU Unified shader cores, scalar ISA, clause execution, full coherency, Vulkan, OpenCL MIDGARD Mali-T600 GPU series Mali-T700 GPU series Mali-T800 GPU series Unified shader cores, SIMD ISA, OpenGL ES 3.x, OpenCL, Vulkan Presented at HotChips 2015 Mali-200 Mali-300 Mali-400 Mali-450 Mali-470 UTGARD GPU GPU GPU GPU GPU Separate shader cores, SIMD ISA, OpenGL ES 2.x 4 © ARM2016 Bifrost features . Leverages Mali’s scalable architecture . Scalable to 32 shader cores 20% Scalable to 32 Higher energy Shader cores . Major shader core redesign efficiency* .
    [Show full text]
  • AI Acceleration – Image Processing As a Use Case
    AI acceleration – image processing as a use case Masoud Daneshtalab Associate Professor at MDH www.idt.mdh.se/~md/ Outline • Dark Silicon • Heterogeneouse Computing • Approximation – Deep Neural Networks 2 The glory of Moore’s law Intel 4004 Intel Core i7 980X 2300 transistors 1.17B transistors 740 kHz clock 3.33 GHz clock 10um process 32nm process 10.8 usec/inst 73.4 psec/inst Every 2 Years • Double the number of transistors • Build higher performance general-purpose processors ⁻ Make the transistors available to masses ⁻ Increase performance (1.8×↑) ⁻ Lower the cost of computing (1.8×↓) Semiconductor trends ITRS roadmap for SoC Design Complexity Trens ITRS: International Technology Roadmap for Semiconductors Expected number of processing elements into a System-on-Chip (SoC). 4 Semiconductor trends ITRS roadmap for SoC Design Complexity Trens 5 Semiconductor trends Network-on-Chip (NoC) –based Multi/Many-core Systems Founder: Andreas Olofsson Sponsored by Ericsson AB 6 Dark Silicon Era The catch is powering exponentially increasing number of transistors without melting the chip down. 10 10 Chip Transistor Count 2,200,000,000 109 Chip Power 108 107 106 105 2300 104 103 130 W 102 101 0.5 W 100 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 If you cannot power them, why bother making them? 7 Dark Silicon Era The catch is powering exponentially increasing number of transistors without melting the chip down. 10 10 Chip Transistor Count 2,200,000,000 109 Chip Power 108 107 Dark Silicon 106 105 (Utilization Wall) 2300 104 Fraction of transistors that need to be 103 powered off at all times due to power 130 W 2 constraints.
    [Show full text]
  • Intel® Desktop Board DG43GT Product Guide
    Intel® Desktop Board DG43GT Product Guide Order Number: E68221-001 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DG43GT Product Guide June 2009 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and the receiver. • Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected.
    [Show full text]
  • I.MX Graphics Users Guide Android
    NXP Semiconductors Document Number: IMXGRAPHICUG Rev. 0, 02/2018 i.MX Graphics User’s Guide Contents Chapter 1 Introduction ............................................................................................................................................. 6 Chapter 2 i.MX G2D API ............................................................................................................................................ 6 2.1 Overview ...................................................................................................................................................... 6 2.2 Enumerations and structures ....................................................................................................................... 6 2.3 G2D function descriptions .......................................................................................................................... 10 2.4 Support of new operating system in G2D .................................................................................................. 16 2.5 Sample code for G2D API usage ................................................................................................................. 16 2.6 Feature list on multiple platforms.............................................................................................................. 19 Chapter 3 i.MX EGL and OGL Extension Support .................................................................................................... 20 3.1 Introduction ..............................................................................................................................................
    [Show full text]
  • Intel® Desktop Board DQ33HS Product Guide
    Intel® Desktop Board DQ33HS Product Guide Order Number: E20672-001 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DQ33HS Product Guide August 2007 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and the receiver. • Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected.
    [Show full text]
  • The Hitchhiker's Guide to Cross-Platform Opencl Application
    The Hitchhiker’s Guide to Cross-Platform OpenCL Application Development Tyler Sorensen and Alastair F. Donaldson Imperial College London, UK IWOCL April 2016 1 “OpenCL supports a wide range of applications… through a low-level, high-performance, portable abstraction.” Page 11: OpenCL 2.1 specification 2 “OpenCL supports a wide range of applications… through a low-level, high-performance, portable abstraction.” Page 11: OpenCL 2.1 specification 3 “OpenCL supports a wide range of applications… through a low-level, high-performance, portable abstraction.” Page 11: OpenCL 2.1 specification We consider functional portability rather than performance portability 4 Example • single source shortest path application Quadro K5200 (Nvidia) Intel HD5500 5 Example • single source shortest path application Quadro K5200 (Nvidia) Intel HD5500 6 Example • single source shortest path application Quadro K5200 (Nvidia) Intel HD5500 7 An experience report on OpenCL portability • How well is portability evaluated? • Our experience running applications on 8 GPUs spanning 4 vendors • Recommendations going forward 8 An experience report on OpenCL portability • How well is portability evaluated? • Our experience running applications on 8 GPUs spanning 4 vendors • Recommendations going forward 9 Portability in research literature • Reviewed the 50 most recent OpenCL papers on: http://hgpu.org/ • Only considered papers including GPU targets • Only considered papers with some type of experimental evaluation • How many different vendors did the study experiment with?
    [Show full text]