Languages for Meta-Programmable Logic and SDR Techniques for Quantum Information

Sébastien Bourdeauducq, Robert Jördens

M-Labs Ltd – https://m-labs.hk

August 20, 2017

David Ilif, CC-BY-SA M-Labs Limited

• Founded after Milkymist, similar to a small research institute • Engineering contracts for physics are fun: • Purpose • Challenging problems, multidisciplinary, advanced technology • Often open source friendly • Incorporated in Hong Kong in 2013, now several full-time staf History of Migen

• Built Milkymist SoC in Verilog (2007-2011) • Datalow graphics pipeline, hardcoded • Wanted a language for hardware datalow • Tried to implement on top of MyHDL, failed (2011) • Developed Migen FHDL, based on metaprogramming • Started implementing again on top of Migen FHDL • Found out it was excellent for SoC, started MiSoC (2012) • Migen datalow is not used much these days Migen’s basic idea: metaprogramming

• Use high level language (Python) to build code in low level language (HDL). • Migen gives you Python objects to assemble to build your design. • Contains hacks for syntactic sugar. • Those objects assembled by your Python program are converted to Verilog so that third-party tools can synthesize the design. • Helps with FSMs, busses, interconnect, portability, simulations, and more. A simple design

a = Signal() b = Signal() x = Signal() y = Signal() module.comb += x.eq(a | b) module.comb += _Assign(y,_Operator( "+", [a,b])) verilog.convert(module) A simple design

module top();

reg a = 1'd0; reg b = 1'd0; wire x; wire y;

assign x = (a | b); assign y = (a | b);

endmodule MiSoC

• Provides high level classes for bus interconnect and MMIO: • Wishbone • Coniguration and status registers • streaming (ex-datalow) interfaces • Provides many cores: • Processors (wrapped Verilog): LM32, mor1kx (a better OpenRISC) • SDRAM controllers and PHYs (SDR, DDR1-3, fastest open source DDR3 controller @64Gbps) • UART, timer, SPI, 10/100/1000 Ethernet • VGA/DVI/HDMI framebufer, DVI/HDMI sampler MiSoC

• Provides bare-metal software (bootloader, low-level libraries) for your SoC. • Provides SoC integration template classes. • Provides basic and extensible SoC ports to FPGA boards. • If those do not it you, you can import the cores only and integrate yourself. LTE base station • PCIe x1 generic SDR board (Artix7 with AD9361: 70MHz to 6GHz) • Almost 100% Migen/MiSoC code (the only exception is the PCIe transceiver wrapper) • Designed to be coupled together for MIMO 4x4 • With software LTE stack: allows afordable LTE BaseStation (10x cheaper than traditionnal solutions) • > 50 boards already produced. LTE base station

A few beneits of using Migen/MiSoC: • Increased productivity compared with VHDL/Verilog. • Developing a PCIe core would have been too expensive with traditional solutions, it has been done as part of this project. • C header iles that describes the hardware (registers/lags/interrupts) automatically generated. • Kintex-7 KC705 prototyping board and Artix inal board share most of the code. SATA 1.5/3/6G core

• Connect hard drives to FPGAs, 6Gbps per drive. • Used in research project at University of Hong Kong. • Kintex-7 FPGA (KC705). • All Migen, including transceiver block instantiation. HDD picture by Evan-Amos, CC BY-SA 3.0 HDMI2USB project • HDMI2USB: Open video capture hardware + irmware • Created by the TimVideos project to enable every user group and conference to record and livestream • Based around making hardware problems, software problems using FPGAs. • Appears as a UVC webcam and CDC ACM serial port, allowing capture and control. • Successfully used to stream linux.conf.au! Conversion from VHDL/Verilog Firmware to Migen/MiSoC

Original irmware was hand coded mix of VHDL and Verilog. • Had questionable license as used Xilinx Coregen for parts. • Slow progress, took 2 years of development. • Poor testing. Conversion from VHDL/Verilog Firmware to Migen/MiSoC New Migen+MiSoC irmware was much easier to use! • Took about 4 weeks to re-implement everything apart from MJPEG core. • Unambigious, full FOSS licensing! • VHDL/Verilog are very hard to use, Python is signiicantly faster to develop in. Softcore approach means much of code is C now. • Already signiicantly more functionality then original irmware (Ethernet, Bufering, Multi-board support). ARTIQ

• ARTIQ is the Advanced Real-Time Infrastructure for Quantum physics. • An integrated software/gateware/hardware system that controls many aspects of atomic physics experiments. • Initially developed with the NIST Ion Storage Group, now with many labs. • Managing/scheduling experiments, driving distributed devices, displaying/archiving results. • Timing is important. The ARTIQ-Python language

trigger.sync() # waitfortriggerinput start = now_mu() # capturetriggertime for i in range(3): delay(5*us) dds.pulse(900*MHz, 7*us) # firstpulse5µsaftertrigger # re-referencetime-line at_mu(start + seconds_to_mu(1*ms)) dds.pulse(200*MHz, 11*us) # exactly1msaftertrigger

• A subset of Python + timing • Executed on a CPU embedded on a FPGA (the core device) • Exact time is kept in an internal variable • That variable only loosely tracks the execution time of CPU instructions • The value of that variable is exchanged with the RTIO fabric that does precise timing • All gateware using Migen/MiSoC Convenient syntax additions

with sequential: with parallel: a.pulse(100*MHz, 10*us) b.pulse(200*MHz, 20*us) with parallel: c.pulse(300*MHz, 30*us) d.pulse(400*MHz, 20*us)

• Experiments are inherently parallel: simultaneous laser pulses, parallel cooling of ions in diferent trap zones • parallel and sequential contexts with arbitrary nesting • a and b pulses both start at the same time • c and d pulses both start when a and b are both done (after 20 µs) Invite organizing experiment components and code reuse

class Experiment: def build(self): self.ion1 = Ion(...) self.ion2 = Ion(...) self.transporter = Transporter(...)

@kernel def run(self): with parallel: self.ion1.cool(duration=10*us) self.ion2.cool(frequency=...) self.transporter.move(speed=...) delay(100*ms) self.ion1.detect(duration=...) Kernel deployment to the core device

• The Python AST is converted to LLVM IR • The LLVM IR is compiled to OpenRISC machine code • The OpenRISC binary is sent to the core device • The runtime in the core device links and runs the kernel • The kernel calls the runtime for communication (e.g. sending back results) and interfacing with core device peripherals (RTIO, DDS, SAWG)

Languages for Meta-Programmable Logic and SDR Techniques for Quantum Information

Robert Jördens Sébastien Bourdeauducq

QUARTIQ and M-Labs https://m-labs.hk https://quartiq.de

WISTA Management GmbH Ion trap (NIST John Jost)

DC RF groundRF RF

DC RF RFRF ground Quantum gate sequences (NIST) 10 attenuators

50 DAC

50 GPIO

20 DDS 10 motors ion trap

FPGA 10 power supplies

10 lasers ∼10 attenuators

∼50 DAC

∼50 GPIO

∼20 DDS ∼10 motors ion trap

FPGA ∼10 power supplies

∼10 lasers Making pulses for Quantum Information: Phaser

• Smart Arbitrary Waveform Generator (SAWG) gateware for Sayma • Multiple Digitally Controlled Oscillators per channel • Interpolating in phase, amplitude, and frequency using B-Splines • Orders of magnitude data reduction through parametrization • GS/s data rate, interpolating up to 2.4 GS/s sample rate • Sample-accurate event timing SAWG

RTIO port cubic spline interpolator x x CORDIC y limiting RTIO port linear freq z adder spline accumulator RTIO port phase

RTIO port cubic spline interpolator x x limiting CORDIC y adder RTIO port linear freq z spline accumulator RTIO port phase

HBF interpolator 32-tap parallel FIRs limitinglimiting x x limitinglimiting DAC adderadder adderadder HBF interpolator y neighbor 32-tap parallel FIRs xchg y parallel CORDICs

RTIO port linear freq spline interpolating accumulator RTIO port phase z

RTIO port cubic spline interpolator SAWG

• Two baseband DDS tones • Up-converted by parallel array of DUCs (not enabled here) • Cubic spline amplitude shaping • Absolute phase control Sayma AMC Front

• Advanced Mezzanine Carrier (AMC) • Kintex Ultrascale, DDR3 RAM • SFP+, FMC, SATA, µTCA backplane • 16 Multi-Gigabit transciever pairs to RTM Sayma RTM Front

• Rear Transition Module (RTM) • 2x 4 channel, 16 bit, 2.4 GS/s, JESD204B DACs • 2x 4 channel, 16 bit, 125 MS/s, JESD204B ADCs Sayma RTM Back

• Ultra low noise sample clock PLL • Extremely lexible clocking tree Sayma RTM

• One PLL mezzanine • Four AFE mezzanines (2 DAC, 2 ADC channels, LO each) Sayma Analog Frontend Mezzanine

Modular analog mezzanines (application dependent): DC signals, iltering, IQ upconversion/downconversion Sinara

• µTCA crate with AMC, RTM, MCH crate management • Telecommunication industry standard • Robustness and reliability • Redundant power supplies, thermal management • High-performance, well-deined, adaptive cooling • Multi-gigabit interconnect fabric • Dedicated and isolated rear transition modules for sensitive RF components Sinara DRTIO

• Custom multi-gigabit link for clock, time, and data transfer • Provides sample-accurate reproducible timing over distributed network of crates Issue tracking

• Used for software and hardware • Milestones and dashboards for high-level overview Issue tracking

• Used for software and hardware • Labels for categorizations Continuous integration

• Multiple kinds of tests and veriication • Linked with source code revision control system • Easy access to deep and inely resolved history of changes Build Bot

• Automated testing of software, gateware, and hardware • At multiple levels through unit tests, integration tests, and benchmarks • Rapid identiication of beneicial or problematic changes Build Bot

...

...

... • Indiscriminate and complete test suite • Automated tooling for compilation, coniguration, and execution Hardware In The Loop (HITL)

• Ensures rapid issue discovery and responsible triage • Dramatically lowers testing complexity and entry barrier for contributors • Allows long term tracking of various igures of merit • Creates conidence in current status ARTIQ and Sinara

Sinara

• https://m-labs.hk/artiq • https://github.com/m-labs/sinara