An Efficient Programmable 10 Gigabit Ethernet Network Interface Card Paul Willmann Hyong-youb Kim Scott Rixner Vijay S. Pai Rice University Purdue University Houston, TX West Lafayette, IN {willmann,hykim,rixner}@rice.edu
[email protected] Abstract latency communication with the system’s host proces- sor for all incoming and outgoing frames. These challenges This paper explores the hardware and software mech- must all be met subject to the constraints of a periph- anisms necessary for an efficient programmable 10 Giga- eral within the server, limiting the area and power con- bit Ethernet network interface card. Network interface pro- sumption of the NIC. cessing requires support for the following characteristics: A 10 Gb/s programmable NIC must be able to support a large volume of frame data, frequently accessed frame at least 4.8 Gb/s of control data bandwidth and 39.5 Gb/s metadata, and high frame rate processing. This paper pro- of frame data bandwidth to achieve full-duplex line rates poses three mechanisms to improve programmable network for maximum-sized (1518 byte) Ethernet frames. The con- interface efficiency. First, a partitioned memory organiza- trol data must be accessed by the processor cores in order tion enables low-latency access to control data and high- to process frames that have been received or are about to be bandwidth access to frame contents from a high-capacity transmitted. On the other hand, the frame data must simply memory. Second, a novel distributed task-queue mecha- be stored temporarily in either the transmit or receive buffer nism enables parallelization of frame processing across as it waits to be transferred to the Ethernet or the system many low-frequency cores, while using software to main- host.