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Ampere Guest Expert May 21, 2021 Jeff Wittich Ampere | Chief Product Officer Key Takeaway Jefferies/Ampere Conf

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Ampere Guest Expert May 21, 2021 Jeff Wittich Ampere | Chief Product Officer Key Takeaway Jefferies/Ampere Conf EQUITY RESEARCH USA | Semiconductors Semiconductors Semis on Fire: ARMageddon Part 2 – Ampere Guest Expert May 21, 2021 Jeff Wittich Ampere | Chief Product Officer Key Takeaway Jefferies/Ampere Conf. Call Replay here We spoke with Jeff Wittich, Chief Product Officer at Ampere, a fabless ARM Server CPU (see detailed bio on next page) company. Key Takes: 1) 80-Core, 7nm ARM CPU shipping today, 128-Core in 2H21, 5nm in '22, 2) Ampere announced customers: Azure, Alibaba, Tencent, et.al., 3) 25-50% lower power vs x86, 4) ARM Ecosystem at critical mass and inflecting. We think ARM is one of the biggest disrupters in computing over the next 5-to-10 yrs. Top ARM-in-Datacenter Plays, MRVL, NVDA, AMD. Video here. ARMageddon Part 1 vs ARMageddon Part 2. We view ARM entering the high-performance computing market as one of the most disruptive forces in both datacenters and PCs over the next 5-to-10 years, and refer to this disruption as ARMageddon. Part 1 refers to the . work we have done around AWS' ARM Server CPU, Graviton (see links in sidebar). Part Links to related notes 2 refers to Ampere, which is offering a standardized merchant ARM Server CPU today Cloud Instance Analysis - Mar'21: AMD called Altra, with Altra Max expect to ship in 2H21. Ampere appears to be gaining traction Regaining / Datacenter Reaccelerating with Cloud Service Providers. 1Q21 CPU Share: AMD Gains 300bps in Ampere is currently shipping Altra, a 7nm, 80-core ARM server CPU, and sampling its Servers + Notebook ARMageddon 128-core Altra Max. Its 5nm customized ARM CPU architecture should sample in 2022. Semis on Fire: ARMageddon + Azure announced its intent to use Ampere Altra this week in its cloud platform. Oracle, Chipageddon = Secular Inflections in Tencent, Bytedance CloudFlare, Equinix, Kingsoft, Meituan, UCloud, and Scaleway also Semis announced as customers. Another Graviton-ARM Success Story - Ampere's Altra, ARM CPU, uses materially less power for same performance as Intel's Notes from Graviton Expert Meetings x86 CPU. The power consumption advantages stem from: JEF U Graviton ARM CPU Expert Call + 1. Extra circuitry required by x86 to support legacy instruction set extensions Transcript 2. Intel’s processor is designed to work on desktops, notebooks and servers, as Cloud Instance Analysis - Feb'21: Graviton opposed to Ampere's CPU, which is optimized for servers (ARM) and Inferentia Gain 3. INTC x86 has a hyperthreaded processing architecture running two threads Semis on Fire: ARMs Suppliers and Mid- per core, which leads to extra circuitry for redundant decode engines and an Cycle Musings architecture that optimizes core utilization at the expense of performance of processing threads MRVL: Hyperscale Inflection: To Strategic Partner From Key Supplier Consistent with our work on Graviton, Mr. Wittich believes that the ARM ecosystem Mark Lipacis * has critical mass and hit an important inflection in 2020. Today, nearly all OS's and key Equity Analyst (415) 229-1438 hypervisors, including VMWare, support ARM. The GCC Opensource ARM compiler had [email protected] a massive upgrade with its version 10 release in mid-2020 Brian Chen * Apple M1 MacBooks are a catalyst to the ARM momentum in cloud. Software engineers Equity Associate favor the MacBook as a development platform. Coding, testing and debugging software (415) 229-1478 on an M1-based MacBook means code is being optimized for ARM [email protected] Natalia Winkler, CFA * Top ARM-in-Datacenter Plays, MRVL, NVDA, AMD. We continue to believe that ARM will Equity Associate be one of the most disruptive forces in computing over the next 5-to-10 years in both (415) 229-1511 datacenters and PCs. We are more cautious on INTC given its dominant position as the [email protected] incumbent supplier of x86 CPUs into PCs and the datacenter. ^Prior trading day closing price unless otherwise noted. Please see analyst certifications, important disclosure information, and information regarding the status of non-US analysts on pages 8 to 14 of this report. * Jefferies LLC / Jefferies Research Services, LLC EQUITY RESEARCH USA | Semiconductors Jeff Wittich Employment History • Ampere | Chief Product Officer | Jan 21 – Current • Ampere | Senior VP of Products | Jun 19 – Jan 21 • Intel | Senior Director, Cloud Business and Platform Strategy | May 14 – May 19 • Intel | Senior Manager, Product Reliability Engineering | Jun 12 – May 14 • Intel | Senior Product Quality and Reliability Engineer | Jun 09 – Jun 12 • Intel | Senior Device Engineer | Jun 05 – Jun 09 • Intel | Process Engineer | Jun 04 – Jun 05 Education • UC Santa Barbara | MS, Electrical Engineering | 2002 – 2004 • University of Notre Dame | BS, Electrical Engineering | 1998 – 2002 Background1 Jeff Wittich is the chief product officer at Ampere. Jeff has extensive leadership experience in the semiconductor industry in roles ranging from product and process development to business strategy to marketing. Prior to joining Ampere, he worked at Intel for 15 years in a variety of positions throughout the company. Most recently, he was responsible for the Cloud Service Provider Platform business, driving global market reach, product customization, and ultimately defining the products and platforms being used across the cloud worldwide. While at Intel, Jeff also led a product development team responsible for 5 generations of Xeon processors. He received an Intel Achievement Award for his work in developing the Custom CPU program. Jeff has an MS in Electrical and Computer Engineering from the University of California, Santa Barbara, and a BS in Electrical Engineering from the University of Notre Dame. 1Sourced from Ampere Computing Leadership Team Web Page May 21, 2021 2 Please see important disclosure information on pages 8 - 14 of this report. EQUITY RESEARCH USA | Semiconductors Notes from Call Why does ARM outperform x86 on a performance per watt basis? 1) The fundamentally same x86 processor cores that were initially designed and developed for client laptop or cell phone products are also being used in server products. Given that clients product needs and the way they focus on power efficiency are inherently different from how servers focus on power efficiency, server products that replicate x86 cores intended for client products are not an efficient design. a) Client products are built around only 4-8 high performance cores with low overall power for the product versus Ampere's server product that uses up to 30x the cores at 128 cores but only 5-6x the power of a client product. Ampere's core designed for scale-out power efficiency is a key design win. While changes are made for core communications, memory and IO functions, none of the x86 vendors have embraced a core designed for the cloud. 2) Hyperthreading, a vestige feature of x86 cores, has created performance unpredictability and security issues. Hyperthreading allowed two threads to be run in 1 core. When renting a vCPU based on x86, which uses hyperthreading, the user will only receive one thread of a physical CPU, unaware of who is renting the other thread of the same CPU. As a result, performance could suffer if the other user is running very intensive workloads that suck up most of the resources of the same CPU. Additionally, a few years ago, security issues have arisen due to side-channel issues that arose from resource sharing via hyperthreading. 3) The efficiencies gained are inherent in the two different approaches to building the instruction set. RISC used by ARM is a simplified reduced instruction set compared to CISC used by x86 being more complex with more instructions. RISC is viewed as a more streamlined design vs the more bloated design of the x86 architecture that innately carries more transistors. 4) x86 supports legacy applications not used in the cloud, making it "bloated". The legacy support applications don't have relevance for the cloud market and just take up space and power within the CPU. ARM's instruction set does not have these unnecessary features, as it is designed for the way that the cloud is scaled out with an inherently efficient base. Hyperthreading 101 Hyperthreading came iton vogue a couple of decades ago by Intel when CPUs previously only had 1 core. Hyperthreading allowed two threads to be run in the 1 physical core. A thread can be simply defined as an execution process that consists of instructions. Hyperthreading can be helpful when 2 applications are running simultaneously on a laptop with instructions from both programs interweaved into the same execution engine. In other words, the core 'resource' is being oversubscribed; when a register is only used 80% of the time, the other 20% can now be used for another program. Issues occur when there is more work that needs to be done than there are actual physical resources resulting in threads fighting for resources and contact switching resulting in back and forth sharing of threads. While more aggregate work may be done over the long term, any individual task doesn't get done better in hyperthreading. Hyperthreading makes sense when there were scarce resources in the CPU historically; however, in a multi-tenant cloud environment where there are multiple users running on May 21, 2021 3 Please see important disclosure information on pages 8 - 14 of this report. EQUITY RESEARCH USA | Semiconductors the same machine, it no longer as logical. Mr. Wittich notes that for this reason, customers prefer a full physical core where they get the performance expected without the worry of security isolation from others. Ampere is designed in this way to effectively utilize all resources and cycles. What can INTC do to recover from these deficits? Mr. Wittich views Intel simplifying its instruction set and stripping out legacy instruction as difficult in practice given Intel's key strength of a 20-year incumbency in the datacenter and legacy base that is all backward-compatible.
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