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Ampere® Altra® 64-Bit Multi-Core Arm® Processor Datasheet

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Ampere® Altra® 64-Bit Multi-Core Arm® Processor Datasheet Ampere® Altra® Datasheet Ampere® Altra® 64-Bit Multi-Core Arm® Processor Features Processor Subsystem Connectivity • 80 Arm® v8.2+ 64-bit CPU cores up to 3.30 GHz maximum • 128 lanes of PCIe Gen4 • 64 KB L1 I-cache, 64 KB L1 D-cache per core ‒ 8 x8 PCIe + 4 x16 PCIe/CCIX with Extended Speed Mode • 1 MB L2 cache per core (ESM) support for data transfers at 20/25 GT/s • 32 MB System Level Cache (SLC) ‒ 48 controllers to support up to 32 x2 links • 2x full-width (128b) SIMD • 192 PCIe lanes in 2P configuration • Coherent Mesh Interconnect (CMI): • Coherent multi-socket support ‒ Distributed snoop filtering • 4 x16 CCIX lanes Memory Technology and Functionality • 8x 72-bit DDR4-3200 channels • Armv8.2+, SBSA Level 4 • SECDED ECC, Symbol-based ECC, and DDR4 RAS features • Advanced Power Management • Up to 16 DIMMs and 4 TB/socket ‒ Dynamic estimation, Voltage droop mitigation System Resources Performance and Power • Full interrupt virtualization (GICv3) • Est. SPECrate® 2017_int_base: 300 • Full I/O virtualization (SMMUv3) • TDP: 45 W to 250 W • Enterprise server-class RAS Process Technology • TSMC 7 nm FinFET Ampere® Altra® Block Diagram 80 Armv8.2+ Cores @ 3.30 GHz 8x DDR4 – 3200 GICv3 Interrupt Controller 72b DDR4 with ECC 72b DDR4 with ECC L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L2 ArmCache v8.2+ CPU L2 ArmCache v8.2+ CPU L2 ArmCache v8.2+ CPU L2 ArmCache v8.2+ CPU L2 Cache L2 Cache L2 Cache L2 Cache 72b DDR4 with ECC 72b DDR4 with ECC L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache Coherent Mesh Interconnect (CMI) + Distributed Snoop Directories Low Speed I/O Secure Boot and Arm SMMUv3 + GICv3 ITS Interfaces Management Processors I2C 2 x8 2 x8 x16 x16 x16 x16 2 x8 2 x8 QSPI UART SMpro PMpro PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe Timers Gen4 / Gen4 / Gen4 / Gen4 / Gen4 Gen4 Gen4 Gen4 GPIOs CCIX CCIX CCIX CCIX GPIs Document Issue 1.10 Ampere Computing Proprietary AMP 2020-0061 Ampere® Altra® Datasheet June 12, 2021 Ampere Computing reserves the right to change or discontinue this product without notice. This document is the Ampere® Altra® datasheet. Make sure you are using the correct edition for the level of the product. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. The information contained in this document is subject to change or withdrawal at any time without notice and is being provided on an “AS IS” basis without warranty or indemnity of any kind, whether express or implied, including without limitation, the implied warranties of non-infringement, merchantability, or fitness for a particular purpose. Any products, services, or programs discussed in this document are sold or licensed under Ampere Computing’s standard terms and conditions, copies of which may be obtained from your local Ampere Computing representative. Nothing in this document shall operate as an expressed or implied license or indemnity under the intellectual property rights of Ampere Computing or third parties. Without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal Ampere Computing test. Therefore, the results obtained in other operating environments may vary significantly. Under no circumstances will Ampere Computing be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein. Ampere Computing 4655 Great America Parkway, Santa Clara, CA 95054 Phone: (669) 770-3700 https://www.amperecomputing.com Ampere Computing reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Ampere, Ampere Computing, the Ampere Computing and ‘A’ logos, Altra, and eMAG are registered trademarks of Ampere Computing. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All other trademarks are the property of their respective holders. Copyright © 2021 Ampere Computing. All rights reserved Document Issue 1.10 Ampere Computing Proprietary 2 Ampere® Altra® Datasheet Contents 1. Device Ordering Information. 7 2. Ampere® Altra® Multi-Core 64-Bit Processor . 7 2.1. Processor Complex (PCP) . 8 2.2. Core Features . 8 2.3. L1 Cache Features . 9 2.3.1. L1 Data Cache . 9 2.3.2. L1 Instruction Cache. 9 2.4. L2 Cache Features . 9 2.5. System Level Cache (SLC) Features. 9 2.6. Generic Interrupt Controller (GIC) Features . 9 2.7. System MMU (SMMU). 10 2.7.1. Translation Buffer Unit (TBU). 10 2.7.2. Translation Control Unit (TCU). 10 2.7.3. DTI Interconnect . 10 2.8. Generic Timer . 11 2.9. Watchdog Timer. 11 2.10. Eight DDR4-3200 SDRAM Memory Controllers. 11 2.11. PCI Express (PCIe) Controller . 11 2.12. System Control Processors (SMpro and PMpro) . 12 2.12.1. SMpro Features . 12 2.12.2. PMpro Features . 13 2.13. Low-Speed Interfaces . 13 2.13.1. I2C Interface . 13 2.13.2. Quad Serial Peripheral Interface (QSPI) . 14 2.13.3. UART . 14 2.13.4. Timers . 14 2.13.5. General Purpose I/Os (GPIOs) . 14 2.13.6. General Purpose Inputs (GPIs) . 15 2.13.7. JTAG . 15 3. Mechanical Data and Package Marking . 16 4. Processor Mass Specification . 17 5. Pin Assignment — Sorted by Pin Number . 18 6. Signal Descriptions. ..
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