NTSC/PAL/SECAM Video Decoder with Component Input And
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Te c h w e l l NTSC/PAL/SECAM Video Decoder with Component Input and Progressive Output Support TW9912 Features Video Decoder Analog Video Input NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N Triple 10-bit ADCs with independent clamping and combination), PAL (60), SECAM support with gain control automatic format detection Supports 480i/480p/576i/576p analog component Software selectable analog input control input with SOG Built-in analog anti-alias filter Digital Output Fully programmable static gain or automatic gain ITU-R 656 compatible YCbCr(4:2:2) output format control for the Y channel Progressive ITU-R 656 output format support for both Programmable white peak control for the Y channel interlaced and progressive inputs 4-H adaptive comb filter Y/C separation Miscellaneous PAL delay line for color phase error correction Two wire MPU serial bus interface Image enhancement with peaking and CTI Power save and Power down mode Digital sub-carrier PLL for accurate color decoding Low power consumption Digital Horizontal PLL for synchronization processing and pixel sampling Single 27MHz crystal for all operations Advanced synchronization processing and sync 3.3V tolerant I/O detection for handling non-standard and weak signal 1.8V/3.3 V power supply Programmable hue, brightness, saturation, contrast, 48 pin QFN package and sharpness Automatic color control and color killer Chroma IF compensation VBI slicer supporting CC and WSS data services Programmable output control 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved FN7945.1 Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. September 27, 2012 All other trademarks mentioned are the property of their respective owners. TW9912 Functional Description SOG PLL VD[7:0] VBI Slicer VBI VIN 0 U CIN1-0 bit AFE bit - Chroma YIN3-0 V Demodulation HSO Analog Video In Video Analog Triple 10 Triple Adaptive Adaptive processing Y Luma/Chroma Comb Filter Comb 4H 4H VSO CLKO 27 Mhz Interface Video lock lock - Clock MPOUT clock clock Line Generator PDN Sync Sync RSTB Processor SCLK Processing SDAT Component 2 Wire Wire 2 Bus Serial FIGURE 1. TW9912 BLOCK DIAGRAM Ordering Information PART PART PACKAGE PKG. NUMBER MARKING (Pb-free) DWG. # TW9912-NA3-CR TW9912 NA3-CR 48 Ld QFN L48.7X7L (Note 1) NOTE: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 TW9912 0x17 – Vertical Peaking Control I ...................................... 44 Table of Contents 0x18 – Coring Control Register (CORING) ...................... 44 0x19 – Reserved ................................................................ 44 Ordering Information .................................................................. 2 0x1A – CC/EDS Status Register (CC_STATUS) ............. 45 Functional Description ............................................................... 2 0x1B – CC/EDS Data Register (CC_DATA) .................... 45 Introduction ............................................................................... 5 0x1C – Standard Selection (SDT) ..................................... 46 Analog Front End ..................................................................... 5 0x1D – Standard Recognition (SDTR) .............................. 46 Sync Processor ........................................................................ 5 0x1E – Component Video Format (CVFMT) .................... 47 Y/C Separation ......................................................................... 5 0x1F – Reserved ............................................................... 47 Color Demodulation ................................................................. 5 0x20 – Clamping Gain (CLMPG) ...................................... 47 Automatic Chroma Gain Control .......................................... 6 0x21 – Individual AGC Gain (IAGC) ................................. 47 Color Killer ............................................................................ 6 0x22 – AGC Gain (AGCGAIN) .......................................... 48 Automatic standard detection .............................................. 6 0x23 – White Peak Threshold (PEAKWT) ........................ 48 Component Processing ........................................................... 7 0x24– Clamp level (CLMPL) ............................................. 48 Sharpness............................................................................. 7 0x25– Sync Amplitude (SYNCT) ....................................... 48 Color Transient Improvement .............................................. 7 0x26 – Sync Miss Count Register (MISSCNT) ................. 48 Power Management ................................................................ 7 0x27 – Clamp Position Register (PCLAMP) ..................... 49 Host Interface ........................................................................... 7 0x28 – Vertical Control I .................................................... 49 Cropping ................................................................................... 8 0x29 – Vertical Control II ................................................... 49 Output Interface ....................................................................... 9 0x2A – Color Killer Level Control ...................................... 50 ITU-R BT.656 ....................................................................... 9 0x2B – Comb Filter Control ............................................... 50 Control Signals ..................................................................... 9 0x2C – Luma Delay and HFilter Control ........................... 50 Vertical timing diagram ......................................................... 9 0x2D – Miscellaneous Control Register I (MISC1) ........... 50 HSYNC ...............................................................................12 0x2E – Miscellaneous Control Register II (MISC2) .......... 51 VSYNC ...............................................................................12 0x2F – Miscellaneous Control III (MISC3) ........................ 52 FIELD ..................................................................................12 0x30 – Copy Protection Detection ..................................... 52 Closed Captioning and Extended Data Services .................12 0x31 – Chip STATUS II (CSTATUS2) .............................. 53 Two Wire Serial Bus Interface ...............................................14 0x32 – H Monitor (HFREF) ................................................ 53 Filter Curves ...........................................................................16 0x33 – CLAMP MODE(CLMD) ......................................... 54 Anti-alias filter .....................................................................16 0x34 – ID Detection Control (NSEN/SSEN/PSEN/WKTH)54 Decimation filter ..................................................................16 0x35 – Clamp Control (CLCNTL) ...................................... 55 Chroma Band Pass Filter Curves ......................................17 0x36 – De-interlacer Control .............................................. 55 Luma Notch Filter Curve for NTSC and PAL/SECAM ......17 0x37 – De-interlacer H Delay Control ............................... 55 Chrominance Low-Pass Filter Curve .................................18 0x38 – De-interlacer Sync Generation .............................. 56 Peaking Filter Curves .........................................................19 0x40 – WSS0 ..................................................................... 56 Pin Diagram ...............................................................................20 0x41 – WSS1 ..................................................................... 56 48 Pin QFN ............................................................................20 0x42 – WSS2 ..................................................................... 56 Pin Descriptions .....................................................................21 0x43 – CCEVENLINE ........................................................ 56 Power and Ground Pins .....................................................22 ADC/PLL Configuration Registers..................................... 57 Parametric Information ............................................................23 0xC0 – LLPLL Input Control Register ............................... 57 AC/DC Electrical Parameters ................................................23 0xC1 – LLPLL Input Detection Register ........................... 57 Output Timing .....................................................................26 0xC2 – LLPLL Control Register ........................................ 58 Serial Host Interface Timing ...............................................27 0xC3 – LLPLL Divider High Register ................................ 58 Serial Host Interface Timing Diagram ................................27 0xC4 – LLPLL Divider Low Register ................................. 58 Package Outline Drawing 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