ON-CHIP TOUCH SENSOR READOUT CIRCUIT USING PASSIVE SIGMA-DELTA
MODULATOR CAPACITANCE-TO-DIGITAL CONVERTER
A Thesis
Presented to
The Graduate Faculty of The University of Akron
In Partial Fulfillment
of the Requirements for the Degree
Master of Science
Bo Liu
December, 2016 ON-CHIP TOUCH SENSOR READOUT CIRCUIT USING PASSIVE SIGMA-DELTA
MODULATOR CAPACITANCE-TO-DIGITAL CONVERTER
Bo Liu
Thesis
Approved: Accepted:
______Advisor Interim Department Chair Dr. Kye-Shin Lee Dr. Joan Carletta
______Committee Member Interim Dean of the College Dr. Joan Carletta Dr. Donald P. Visco, Jr.
______Committee Member Dean of the Graduate School Dr. Robert Veillette Dr. Chand Midha
______Date
ii ABSTRACT
This work describes a capacitive touch sensor readout circuit using a passive sigma-delta modulator-based capacitance-to-digital converter. With the proposed approach, the panel condition (touched or un-touched) can be effectively converted into a binary signal by using the panel capacitance as the summing element of a first order passive sigma-delta modulator. In addition, the proposed touch sensor readout circuit does not require an analog-to-digital converter (ADC), since a digital output corresponding to the touch panel condition can be simply obtained by counting the number of modulator output pulses within the detection period. This along with the passive architecture leads to a compact and low power on-chip touch sensor readout circuitry. Furthermore, due to the noise shaping property of the sigma-delta modulator, it is possible to achieve a signal-to-noise ratio (SNR) and detection time that are comparable to those of other touch sensor readout circuits. The proposed touch sensor readout circuit is implemented using CMOS 0.35 µm technology and has a core area of
0.1 mm2. The operation of the sensor readout circuit is verified with a 10.4″ projective capacitance type touch panel, where the measured SNR is 31.4 dB and the measured power consumption is 65 µW.
iii DEDICATION
Dedicated to my parents and friends
iv ACKNOWLEDGEMENTS
I would like to thank my advisor Dr. Kye-shin Lee for guiding me throughout my
Master’s degree. Without his patience, his encouragement and the financial support for the prototype IC and PCB, it would not have been possible for me to present this thesis project.
I would like to acknowledge my thesis committee Dr. Joan Carletta and Dr.
Robert Veillette, for their technical input and support throughout my Master’s degree projects and research assistant work.
I would also like to express my sincere gratitude to the Electrical Engineering
Department of the University of Akron for giving me an opportunity to be in this program and supporting my degree through a research assistantship.
v TABLE OF CONTENTS
Page
LIST OF TABLES ...... viii
LIST OF FIGURES ...... ix
CHAPTER
I. INTRODUCTION ...... 1
1.1 Background and Motivation ...... 1
1.2 Goals of the Thesis ...... 2
1.3 Thesis Organization...... 3
II. LITERATURE REVIEW...... 4
2.1 Capacitive Touch Screen Types ...... 4
2.2 Conventional Capacitive Touch Sensor Readout Circuit Structures ...... 6
2.2.1 Readout Circuits Based on Relaxation Oscillators ...... 7
2.2.2 Readout Circuit Based on Charge Transfer ...... 10
2.2.3 Readout Circuit Based on Series Capacitance Voltage Division ...... 12
2.3 Most Recent Work Related to Capacitive Type Touch Sensor Readout Circuit ...... 13
2.4 Sigma-delta Modulator-Based Capacitance Sensors...... 17
III. PROPOSED TOUCH SENSOR READOUT CIRCUIT ...... 23
3.1 Sensor Readout Circuit Model ...... 23
vi 3.2 Passive Sigma-delta Modulator Based Capacitance-to-Digital Converter ...... 27
3.3 CDC System Level Analysis ...... 32
IV. EFEFECT OF NON-IDEALITIES...... 34
4.1 Parasitic Capacitance...... 35
4.2 Capacitor Error ...... 39
4.3 Comparator Offset ...... 41
4.4 Supply Sensitivity ...... 42
V. CIRCUIT IMPLEMENTATION ...... 44
5.1 Passive Sigma-delta Modulator ...... 44
5.2 Comparator ...... 45
5.3 Panel Capacitance (Channel) Selector ...... 48
VI. EXPERIMENTAL RESULTS ...... 49
VII. CONCLUSIONS AND FUTURE WORK ...... 58
BIBLIOGRAPHY ...... 60
vii LIST OF TABLES
Table Page
2.1 Switch S1, S2 and S3 Position with Comparator Output Level and Switch Control Clock Edge ...... 21
3.1 Cp Detection Range with Cs and M. (Unit: pF)...... 33
3.2 Cp Resolution with Cs (M = 33) ...... 33
4.1 Npulse with Cp for Different Cpx and Cpy ...... 39
4.2 Npulse with Cp for ±10% Cs Error ...... 40
4.3 Npulse with Cp for Comparator Offset Vos ...... 41
4.4 Npulse with Supply Ripple of Different Amplitude and Frequency (CP=20 pF) ...... 42
6.1 Performance Comparison with the State-of-the-art Capacitive Touch Sensor Readout Circuits ...... 56
viii LIST OF FIGURES
Figure Page
2.1 Capacitive Touch Screen Touch Sensing Scheme ...... 4
2.2 Projected Capacitance Touch Screens (a) Self-Capacitance Touch Screen; (b) Mutual Capacitance Touch Screen ...... 5
2.3 Relaxation Oscillator-Based Touch Sensor Circuit using Schmitt Trigger ...... 8
2.4 Schmitt Trigger Relaxation Oscillator-Based Touch Sensor Readout Circuit Timing Diagram (a) With Small Panel Capacitance; (b) With Large Panel Capacitance ...... 8
2.5 Relaxation Oscillator Touch Sensor Readout Circuit using Comparator ...... 9
2.6 Relaxation Oscillator-Based Touch Sensor Readout Circuit Timing Diagram ...... 10
2.7 Charge Transfer-Based Touch Sensor Readout Circuit ...... 11
2.8 Charge Transfer-Based Touch Sensor Readout Circuit Timing Diagram ...... 12
2.9 Series Capacitance Voltage Divider Based Touch Sensor Readout Circuit ...... 13
2.10 One C-VC Block with Time Interleaved Scheme [11] ...... 14
2.11 Charge Sensing Circuit Block Diagram [12] ...... 16
2.12 Charge Sensing Circuit Timing Diagram ...... 16
2.13 Conventional Sigma-delta Modulator Structure ...... 17
2.14 Differential Sigma-delta Modulator-Based CDC [4] ...... 19
2.15 Single-ended Sigma-delta Modulator-Based CDC [5] ...... 20
2.16 Equivalent Circuit Depending on VCOMP Level (a) Equivalent Circuit for VCOMP = “H”; (b) Equivalent Circuit for VCOMP = “L” ...... 21
3.1 Proposed Touch Sensor Readout Circuit ...... 24
ix 3.2 Proposed Readout Circuit Operation Timing ...... 25
3.3 Passive Sigma-delta Modulator Z-domain Model ...... 27
3.4 Proposed CDC Operation ...... 29
3.5 CDC Output Waveforms with Cs=0.75pF (a) Cp = 10pF. (b) Cp = 20pF ...... 31
3.6 Proposed CDC, Pulse Number Versus Panel Capacitance with Different Sampling Capacitor Values (M = 33) ...... 32
4.1 Proposed CDC with Non-idealities ...... 35
4.2 Z-domain Block Diagram of the Passive Sigma-delta Modulator with Parasitic Capacitance ...... 37
5.1 Transistor Level Circuit of the Proposed Passive Sigma-delta Modulator ...... 44
5.2 Comparator Circuit ...... 46
5.3 Comparator Offset Monte-Carlo Simulation Result ...... 47
6.1 Chip Micrograph (a) and Measurement Setup (b) ...... 50
6.2 Passive Sigma-delta Modulator Output Spectrum ...... 51
6.3 DNL and INL Plot of Decimated Sigma-delta Modulator Output ...... 52
6.4 Input-output Transfer Characteristic of Decimated Sigma-delta Modulator ...... 52
6.5 Three Different Touch Locations for the Panel ...... 53
6.6 CDC Output Waveforms Corresponding to Each Touch Location (a) Edge (b) Middle (c) Corner ...... 55
x CHAPTER I
INTRODUCTION
1.1 Background and Motivation
Due to the increased demand for user friendly interfaces, touch screens and touch panels are becoming essential components for most portable electronic devices such as smart phones, tablets, MP3 players, and eBook readers [1] – [3]. During the past two decades, the touch screen market has experienced a major transition from low cost resistive-type touch screens to capacitive-type touch panels that can easily support multi- touch features with improved accuracy, durability, and shorter detection time. Basically, the capacitive-type touch panel requires a touch sensor readout circuit that can detect the variation of the touch panel capacitance (usually with the variation between 10 pF and 50 pF). However, in order to be suitable for battery operated portable devices, touch panels require compact and low power sensor readout circuits with high detection accuracy.
One low-power approach for detection of changes in capacitance is the sigma- delta modulator (ΣΔM) based capacitance-to-digital converter (CDC). The sigma-delta modulator based CDC can achieve improved SNR due to the noise shaping property, where two different approaches have been proposed in [4] and [5]. The scheme in [5] is immune to environment noise, and insensitive to stray capacitance, but it is not
1 suitable for touch panel capacitance (that are basically single capacitance) detection due to the differential configuration. The scheme in [4] can be used for single capacitance detection, with a four phase control clocking scheme, but the on-chip implementation can be limited since the reference capacitor has to be larger than the touch panel capacitance, which can already be as large as 50 pF. In this thesis, a touch sensor readout circuit based on a passive sigma-delta modulator based capacitance-to-digital converter (CDC) is proposed. The proposed CDC uses the panel capacitance as the summing element of the passive sigma-delta modulator avoiding the need for a large reference capacitor, and does not require an ADC, since the digital output format can be obtained by counting the number of CDC pulses within the detection period. These two features both constitute advantages over the scheme in [4] and [5]. The passive sigma-delta modulator architecture used for the proposed touch sensor readout circuit is based on the applications from the previous works [6] – [8], where the benefits such as the wide input dynamic range and low power consumption are maintained. As a result, the silicon area and the power consumption can be significantly reduced, while maintaining a comparable
SNR and detection time with respect to other touch sensor readout schemes.
1.2 Goals of the Thesis
The goal of this thesis is to design an on-chip touch sensor readout circuit using a passive sigma-delta modulator based CDC, which can work with the most popular projected capacitive type touchscreen panels. To achieve this goal, the behavioral model development, circuit implementation, testing and characterization of the proposed touch sensor readout circuit have been done.
2 The following contents are the detailed steps that were carried out to complete the thesis. A discrete time model of the touch sensor readout circuit was constructed in
Simulink in order to verify the operation. The effect of various non-idealities is considered and analyzed to estimate the actual circuit performance. Each circuit block of the IC was designed and simulated using Cadence Virtuoso to verify the functionality.
The readout circuit layout was done and the IC was implemented using CMOS 0.35-µm technology. After the IC was fabricated, a PCB that can interface the IC with a 10.4” projected type capacitive touch panel was built. Using this test setup, the operation of the readout IC was verified and the performance was characterized.
1.3 Thesis Organization
The remaining part of this thesis is presented in six chapters. Chapter II presents the background information related to touch screen types, conventional and recent capacitive touch sensor readout circuits. Chapter III describes the proposed passive sigma-delta modulator based touch sensor readout circuit. Chapter IV discusses the effects of non-idealities, which includes parasitic capacitance, capacitor error, comparator offset and power supply sensitivity to show the robustness of the readout circuit. Chapter
V presents the circuit implementation divided into three parts, which are sigma-delta modulator, comparator, and panel capacitance selector. Chapter VI presents the experimental setup using an actual 10.4″ touch screen panel and the test results. Finally,
Chapter VII presents the conclusions.
3 CHAPTER II
LITERATURE REVIEW
2.1 Capacitive Touch Screen Types
A capacitive type touch panel consists of an insulator (glass plate) that is coated by a conductive material such as ITO (indium tin oxide). When a human finger approaches the surface of the screen, the distortion of the screen’s electrostatic field changes the capacitance between the sensing electrodes as shown in Figure 2.1 [9]. The most commonly used capacitive touch screens nowadays are projected capacitance touch screens.
Figure 2.1 Capacitive Touch Screen Touch Sensing Scheme
Projected capacitance touch (PCT) technologies detect touch by measuring the capacitance at each addressable electrode. When a finger approaches an electrode, it
4 disturbs the electromagnetic field and alters the capacitance. This capacitance variation can be measured by the readout circuits, and then converted into X-Y coordinates that the system can use to detect the touch. The value of the capacitance at each coordinate can vary from 10 pF to 50 pF. There are two touch screen types for the projected capacitance touch technology, which are self-capacitance and mutual capacitance where the electrode arrangements and the equivalent circuits are shown in Figure 2.2 (a), (b), (c) and (d).
Figure 2.2 Projected Capacitance Touch Screens (a) Self-Capacitance Touch Screen; (b) Mutual Capacitance Touch Screen
In the self-capacitance implementation, each row and column is an electrode independently as shown in Figure 2.2 (a), and the equivalent circuit is shown in Figure
2.2 (b), therefore rows and columns are individually addressed by the controller. Even
5 though the intersection of a row and column represents a unique coordinate pair, the electronic readout circuits are not able to measure each individual intersection as they can only measure each electrode. Self-capacitance technology has one capacitor for each row and one for each column. When a finger approaches the screen, the readout circuits scan through each electrode for capacitive load changes. By determining which row and column are closest to the touch location, the touch location can be determined by a microcontroller.
Mutual capacitance type is a common PCT approach that utilizes the fact that if two conductive objects are close together they can hold a charge. A mutual capacitance touch screen is shown in Figure 2.2 (c) and the equivalent circuit is shown in Figure 2.2
(d). Mutual capacitance touch screens intentionally create mutual capacitance between elements of columns and rows in the vicinity where each intersects the other. Every intersection of each row and column forms a mutual capacitor, and every capacitor is independent with each other. When a finger touches near an intersection, some of the electric field between the row and column is coupled to the finger, which reduces the capacitance at the intersection as measured by the system readout circuits. This reduced capacitance that crosses the “touch threshold” set by the electronics indicates a touch has occurred. Many products such as smart phones combine the mutual and self-capacitance types to realize the touch panel.
2.2 Conventional Capacitive Touch Sensor Readout Circuit Structures
There are several capacitive touch sensor readout circuits, which are realized based on relaxation oscillator, charge transfer and series capacitance voltage divider [10]
6 [11]. These readout circuits are used for the most commonly used projected mutual capacitance touch screens. They detect a touch event by measuring the change of capacitance at the nearest X-Y coordinates on the touch panel, and each independent capacitance is called panel capacitance. The three schemes are to be discussed in more detail below.
2.2.1 Readout Circuits Based on Relaxation Oscillators
Figure 2.3 shows a relaxation oscillator based touch sensor readout circuit realized using a Schmitt trigger and a feedback resistor. Assuming CP represents the capacitance at a certain touch screen location, the circuit detects the CP variation, where
CP changes with the panel condition - touched or untouched. X is the input of the Schmitt trigger, and Y is the inverting output. In this case, a different panel capacitance results in a different RC time constant, which changes the period of the Schmitt trigger.
Figure 2.4 shows the operation of the readout circuit. VTH-L and VTH-H are the low and high threshold of the Schmitt Trigger, respectively. Given an initial condition that VX is close to VTH-L but below VTH-L, so VY is “H” (high), then VY starts to charge CP through R. The time required to charge CP until VX reaches VTH-H is proportional to the time constant τ=R∙CP. When VX reaches VTH-H, VY becomes “L” (low), where CP begins to be discharged. The time required to discharge CP until VX reaches VTH-L is also proportional to τ. The sum of the charge and discharge time is denoted as T. Since different panel capacitance results in different τ, different panel conditions (touched or untouched) can be detected by measuring the duration of T. Figure 2.4 shows the waveforms at nodes X and Y with different panel capacitance, (a) small panel
7 capacitance, (b) large panel capacitance. As is shown, panel condition can be detected based on different oscillation periods T.
Figure 2.3 Relaxation Oscillator-Based Touch Sensor Circuit using Schmitt Trigger
Figure 2.4 Schmitt Trigger Relaxation Oscillator-Based Touch Sensor Readout Circuit Timing Diagram (a) With Small Panel Capacitance; (b) With Large Panel Capacitance
8 Figure 2.5 shows a relaxation oscillator based touch screen readout circuit that includes a reset switch and a comparator to detect the touch screen panel condition. The comparator output controls the reset switch. At the beginning, VY = “L” (low), and the switch is off, so the power supply VDD starts charging CP through R. Figure 2.6 shows the operation timing diagram, where VX keeps increasing as CP is being charged until it reaches the comparator threshold voltage VTH, then the comparator output VY changes from “L” to “H” (high). At this instant the switch is turned on to discharge the panel capacitance CP. Then as VX drops down below VTH, VY changes from H to L. The oscillation period T changes with panel capacitance variation, because different panel capacitance requires different charge and discharge time, i.e. smaller panel capacitance results in shorter T and larger panel capacitance results in longer T. Thus, by measuring the period of the output waveform T the panel condition can be detected.
Figure 2.5 Relaxation Oscillator-Based Touch Sensor Readout Circuit using Comparator
9 Figure 2.6 Relaxation Oscillator-Based Touch Sensor Readout Circuit Timing Diagram
2.2.2 Readout Circuit Based on Charge Transfer
Figure 2.7 shows a charge transfer based touch sensor readout circuit which can detect the touch screen panel condition. The operation is divided into three phases, sampling, summing and reset. The sampling and summing are controlled by a single pole double throw switch SW1 and the reset is enabled by SW2. In the sampling phase, SW1 is connected to position 1, and CP is charged by VDD while Csum retains the charge from last summing phase. In the summing phase, SW1 is connected to position 2, the charge in CP is shared between CP and Csum, resulting in an increase in VX. This circuit repeats the charge and discharge of CP by connecting SW1 to position 1 and 2, so the charge in Csum is accumulated. As a result, VX keeps increasing until it reaches the comparator threshold voltage VTH. The reset switch SW2 is open until the comparator output is high. Once VX reaches VTH, Vout changes from “L” to “H”, the reset phase begins and the reset switch
10 SW2 is turned on, so Csum is discharged. Switch SW2 is designed to have small enough on-resistance to allow Csum to be completely discharged before Vout becomes “L”.
The waveforms of VX and Vout are shown in Figure 2.8. The sampling and summing time of CP which is denoted as T or T’ is different for different panel capacitance. In Figure 2.8, T corresponds to a smaller CP, and T’ corresponds to a larger
CP. If CP is smaller, the charge in phase 1 is smaller, so the charge sharing between CP and Csum in phase 2 is smaller, which leads to a smaller increment in VX after each clock cycle. Therefore, it needs more cycles (longer time) for VX to reach the comparator threshold voltage VTH than when CP is bigger. Thus by measuring T the panel condition can be detected.
Figure 2.7 Charge Transfer-Based Touch Sensor Readout Circuit
11 Figure 2.8 Charge Transfer-Based Touch Sensor Readout Circuit Timing Diagram
2.2.3 Readout Circuit Based on Series Capacitance Voltage Division
Figure 2.9 shows a series capacitance voltage divider based touch sensor readout circuit. This circuit works in two phases, which are series capacitors charging and discharging, respectively. In Phase 1, SW1 is turned on, SW2 and SW3 are turned off, thus
CP and CREF are charged by the reference voltage VR. When CP and CREF are fully charged, since CP and CREF are connected in series, the node voltage VA can be written as
CREF VAR = V . (2.1) CP +C REF
As a result, panel capacitance CP variation will result in different VA levels. In Phase 2,
SW1 is turned off, SW2 and SW3 are turned on, thus CP and CREF are discharged and node voltage VA will be reset.
12 By setting a specific value of the comparator threshold based on CP and CREF values, the comparator output at the end of each Phase 1 will be logically different based on the touching condition; i. e. a small CP gives a “H” output and a large CP will lead to a
“L” output. Thus, by detecting the comparator output level, the panel condition can be detected.
Figure 2.9 Series Capacitance Voltage Divider Based Touch Sensor Readout Circuit
2.3 Most Recent Work Related to Capacitive Type Touch Sensor Readout Circuits
This section summarizes the two most recent capacitive type touch sensor readout circuits in the literature, which use switched capacitor based capacitance-to-voltage converter (C-VC) and capacitance-to-time conversion (CTC) approaches.
Work [12] proposes a switched-capacitor integrator-based capacitance-to-voltage converter (C-VC) with time-interleaved scheme. In this work, a 320 channel touch panel
13 with 20 row and 16 column electrodes is utilized, where one channel is the intersection of one row and one column electrode. The Y electrodes are divided into four groups and are connected to four C-VCs via four 4-to-1 Analog Multiplexers. Figure 2.10 shows one C-
VC block for simplicity. X electrodes [0:19] are sequentially driven column by column by non-overlapping clock generator and switches. The corresponding C-VC block senses the Y coordinate on the touch screen and the charge stored in each panel capacitance will be integrated, and the integrator output level will change based on different touch conditions. At the end of each channel detection, the reset switch RST will be turned on to reset the circuit to get ready for the next channel detection. Larger panel capacitance will result in higher C-VC output level and vice versa, thus the touch location can be detected by monitoring the C-VC output level. The four C-VC outputs are connected to the SAR ADC by a 4-to-1 Mux. The drawback of this approach is that it requires large size off-chip feedback capacitors CINT.
Figure 2.10 One C-VC Block with Time Interleaved Scheme [12]
14 Another touch sensor readout circuit that can effectively measure the panel capacitance variation using the capacitance-to-time conversion (CTC) method is presented in reference [13]. The core part of this design is the charge sensing circuit shown in Figure 2.11. The reference current Iref is generated from a current reference circuit and injected into the panel capacitor CP. The timing diagram is shown in Figure
2.12. Initially the comparator output is high since VC is lower than the comparator threshold level VTH. The time T required for the node voltage VC to reach VTH is derived as
VTH T=CP , (2.2) Iref where different panel capacitance results in different T for the comparator output to change from “H” to “L”. In this case, T is measured by an external microcontroller. The discharge switch SW2 is turned on when the comparator output changes to “L”, so that the panel capacitor could be discharged for the next sensing event. After a certain delay period, the switch SW1 is turned on and SW3 is turned off to prevent the reference current from flowing into CP when the panel capacitor is being discharged. SW1, SW2 and SW2 are all implemented with NMOS switches. An additional timing control block generates the control signals for the charge sensing circuit and the panel capacitance switch array to sequentially select the panel capacitance.
15 Figure 2.11 Charge Sensing Circuit Block Diagram [13]
Figure 2.12 Charge Sensing Circuit Timing Diagram
To sum up, the above capacitance-to-voltage and capacitance-to-time capacitive touch sensing schemes are both good works. However, reference [12] requires large off-chip integrating capacitors and power hungry ADC, and reference [13] needs a
16 CMOS current reference circuit for the current generator which adds to the circuit complexity. The proposed circuit shows an improvement from these aspects.
2.4 Sigma-delta Modulators in Capacitance Sensing Circuits
Sigma-delta modulation is a method for encoding analog signals into digital signals as found in an ADC. Sigma-delta modulator structures can be very useful in capacitive sensing circuits, since the output waveform changes with the variations in the capacitance used as a sampling or summing element of the sigma-delta modulator. The conventional sigma-delta modulator has the circuit structure shown in Figure 2.13. It includes the comparator and the integrator realized with four switches controlled by non-overlapping clocks Φ1 and Φ2, sampling capacitor CIN and integration capacitor CINT.
The comparator output is used as the feedback signal that is subtracted from the input VIN.
Figure 2.13 Conventional Sigma-delta Modulator Structure
Basically the sigma-delta modulator operates as follows. In Φ1, CIN samples the input voltage VIN. In Φ2, the charge stored in CIN during Φ1 is transferred to CINT. As time goes by, when the integrator (CINT and the amplifier) output voltage exceeds the comparator threshold voltage VTH, the comparator output changes its state from “L” to
“H”, thus the circuit feedback changes its state, which reduces the integrator output in the
17 next clock cycle. The comparator output is a pulse stream. CIN variation leads to charge variation in Φ1, so the charge transferred to CINT during Φ2 is different based on different
CIN; this results in the difference in integrator output increment value after each clock cycle. Therefore, the time required for the integrator output to reach the comparator threshold value is different, and so is the comparator output pulse length. Thus the time or the pulse numbers could be measured to detect the panel capacitance variation assuming the VIN is a constant voltage.
The sigma-delta modulator structure is widely used in CDC (Capacitance-to-
Digital Converter) circuits. The basic concept of the CDC is to generate a digital output, where the output value within a certain time interval is determined by the value of the capacitor. In reference [4], the capacitive sensor circuit using sigma-delta techniques implements a differential circuit structure, where only the integrator block is shown in
Figure 2.14. The reference and feedback circuitry and the comparator have been omitted for clarity. This structure has two input sensing capacitors CIN1 and CIN2, and two integrating capacitors that have the same value of CINT. By alternating the connection of
Φ1 and Φ2 switches to VREF+ and VREF-, the sampling and integrating occurs alternately.
In this case, the output can be described as
(CIN1 -C IN2 ) VOUT+ -V OUT- =- (VREF+ -V REF- ) . (2.3) CINT
As a result, the output is proportional to the difference between the two input capacitors (CIN1 - CIN2); if one capacitor is fixed as a reference capacitor, the other input capacitor can be used as the sensing capacitor. Thus the output pattern depends on the value of the input capacitors.
18 Figure 2.14 Differential Sigma-delta Modulator-Based CDC [4]
In reference [5], a single-ended sigma-delta modulator-based capacitance detector is proposed as shown in Figure 2.15. Similar to work [4], this circuit also uses two input sensing capacitors. However, this work only has one integrating capacitor to charge from the two input capacitors. In this circuit, the comparator output goes into a flip-flop whose output is VOUT. Switches S1, S2 and S3 are controlled by VOUT and the flip-flop’s clock through some logic gates as shown in Figure 2.15. Table 2.1 shows the switch position depending on VOUT level and clock edge. This circuit works in the following way.
Assuming the initial output level of the flip-flop is set to “H”, for the first clock cycle, S2 is set fixed to position 2. When the clock level is “H”, S1 and S3 are in position 1, and when the clock level is “L”, S1 and S3 are in position 2. The equivalent circuits for VOUT
= “H” is shown in Figure 2.16 (a). As a result, at the end of this clock cycle, the integrator output is increased by VREF∙(CIN1/CINT). This increase makes the integrator output positive, thus the comparator and flip-flop output will become “L”. Whenever
VOUT becomes “L”, at the next control clock cycle, S1 will be set fixed to position 2.
When the clock level is “H”, S2 will be at position 1 and S3 will be at position 2; when
19 the clock level is “L”, S2 will be at position 2 and S3 will be at position 1. The equivalent circuits for VOUT = “L” is shown in Figure 2.16 (b). For this case, the integrator output will be decreased by VREF∙(CIN2/CINT). If CIN1= CIN2, the integrator output will deduct the same amount of voltage which is added from last clock cycle, since VREF∙(CIN1/CINT) =
VREF∙(CIN2/CINT). Thus the integrator output will become negative, making the comparator output “H” again. As time goes by, there will be equal number of “H”s and
“L”s at the flip-flop output. However, if CIN1> CIN2, after one VOUT = “H” and one VOUT =
“L” controlled clock cycle, the integrator output decreases less than it increases in the previous clock cycle, so VOUT remains “L” for another clock cycle. This allows another
-VREF∙(CIN2/CINT) added to the comparator input. VOUT remains low until the integrator output decreases to below zero. Therefore there will be more “L”s than “H”s at VOUT for
CIN1> CIN2. On the contrary, if CIN1< CIN2, there will be fewer “L”s than “H”s at VOUT.
Thus, by fixing the value of one input capacitor as a reference, and detecting the number of the output “H”s and “L”s, the input capacitance variation can be detected.
Figure 2.15 Single-ended Sigma-delta Modulator-Based CDC [5]
20 Table 1.1 Switch S1, S2 and S3 Position with Comparator Output Level and Switch Control Clock Edge
Clock VOUT = “H” VOUT = “L” S1 - Pos. 1 S1 - Pos. 2 H S2 - Pos. 2 S2 - Pos. 1 S3 - Pos. 1 S3 - Pos. 2 S1 - Pos. 2 S1 - Pos. 2 L S2 - Pos. 2 S2 - Pos. 2 S3 - Pos. 2 S3 - Pos. 1
Figure 2.16 Equivalent Circuit Depending on VOUT Level (a) Equivalent Circuit for VCOMP = “H”; (b) Equivalent Circuit for VOUT = “L”
In this Chapter, the background information and the reviews of some conventional and recent circuit structures related to touch sensor readout circuits are presented, as well as the sigma-delta modulator-based capacitance sensors. Just as the conventional touch sensor readout circuits, the proposed readout circuit in this paper converts the panel capacitance change into some more easily detectable information. The proposed touch
21 sensor readout circuit implements the sigma-delta modulator technology. However, compared to the sigma-delta modulator structures introduced in Section 2.4, the proposed readout circuit uses a passive sigma-delta modulator structure. The reduction of capacitor numbers and the elimination of the active amplifier give advantages in terms of reduced power consumption, silicon area and circuit complexity compared to other touch sensor readout circuits. In the remaining chapters, the design and performance of the proposed touch sensor readout circuit will be presented.
22 CHAPTER III
PROPOSED TOUCH SENSOR READOUT CIRCUIT
3.1 Sensor Readout Circuit Model
The touch sensor readout circuit detects the touched location by scanning the capacitance value at each panel location. Generally, the capacitance value at a given panel location is converted into a voltage level or pulse width, and the touched location can be figured out by checking the capacitance variation pattern throughout the touch screen panel.
Figure 3.1 shows the proposed touch sensor readout circuit, which can detect the touch screen panel condition by converting the panel capacitance into pulse numbers. The readout circuit includes the first order passive sigma-delta modulator and the panel capacitance selector (SX1 ~ SXX and SY1 ~ SYY). The panel capacitance selector will be discussed in Chapter 5 in more detail. Vin represents the DC voltage applied to the sigma- delta modulator, which is connected to VDD for normal CDC operation. The passive sigma-delta modulator consists of the sampling capacitor Cs that can be adjusted to 0.25 pF, 0.5 pF, 0.75 pF, 1 pF, 1.25 pF or 1.5 pF, several switches and a comparator, where each panel capacitance CP is used as the summing capacitor. The adjustable Cs is to adapt the proposed readout circuit with different types of capacitive touch panels.
23 Figure 3.1 Proposed Touch Sensor Readout Circuit
The operation timing of the sensor readout circuit including the control clock waveforms are shown in Figure 3.2, where the START signal indicates the beginning of the frame. Each panel capacitance is connected to the readout circuit one at a time by the switches SX1 ~ SXi and SY1 ~ SYj. Once the panel capacitance is connected to node Vx, the reset signal RST will discharge the panel capacitance. After the reset, the passive sigma- delta modulator will repeat the charge sampling and charge summing operation, which will generate different output pulse patterns depending on the value of the touch panel capacitance. In this case, the panel condition (touched or untouched) can be detected by simply counting the number of output pulses within the channel detection period.
24 Figure 3.2 Proposed Readout Circuit Operation Timing
The operation of the passive sigma-delta modulator is divided into two phases. In the charge sampling phase (Φ1 = H), input voltage Vin is sampled in the sampling capacitor Cs. During the charge summing phase (Φ2 = H), Cs and CP are connected together, where charge sharing between Cs and CP will occur. As a result, the node voltage Vx will be set to a certain level depending on the size of Cs and CP that will be compared with the comparator threshold level VTH, in order to generate the sigma-delta modulator output level that is either “H” or “L”.
The equivalent z-domain model of the passive sigma-delta modulator for the proposed touch sensor readout circuit is derived using the following charge equations.
For the n-th operation cycle, the charge stored in Cs and CP is given by
QCs (n)=Cs [V in (n)-V(n)] o , (3.1)
25 QCp (n) CP V(n x 1/2) . (3.2)
For the (n + 1/2)-th operation cycle, due to the charge sharing between Cs and CP, the following relationship can be reached
[Cs C]V(n P x 1/2) QCs (n) QCp (n) . (3.3)
Furthermore, using the following relationship
V(n)xx V(n 1/2) , (3.4a)
Vxx (n+1)=V (n+1/2) , (3.4b)
Voo (n) = V (n - 1/2) , (3.4c)
with eq. (3.1) and eq. (3.2), the node voltage Vx can be rewritten as
Vx (n +1) = G1 [V in (n) - V o (n)] + G2 V x (n) , (3.5)
where coefficients G1 and G2 are given as
Cs G=1 , (3.6a) CsP + C
CP G=2 . (3.6b) CsP + C
26 As a result, the z-domain expression of node voltage Vx is given by
-1 -1 Vx (z) = z G1 [V in (z) - V o (z)] + z G2 V x (z) , (3.7) where based on eq. (3.7), the equivalent z-domain representation of the first order passive sigma-delta modulator based touch sensor readout circuit is shown in Figure 3.3. In this case, the sigma-delta modulator output pattern will depend on the value of the coefficients G1 and G2. By using the touch panel capacitance as the summing capacitor of the passive sigma-delta modulator, any change in panel capacitance due to a touch causes a change in the coefficients G1 and G2, which will change the output pattern of the sigma- delta modulator. In addition, since the output format of the sigma-delta modulator is digital, the sensor readout block does not require an ADC; simple pulse counting logic is enough, so the silicon area and the power consumption of the touch sensor readout circuitry is reduced over other approaches.
Figure 3.3 Passive Sigma-delta Modulator Z-domain Model
3.2 Passive Sigma-delta Modulator Based Capacitance-to-Digital Converter
The basic concept of the proposed CDC is to generate an output pulse sequence, where the number of pulses within a certain time interval (detection period) is determined
27 by the value of CP, since Cs will be set to a fixed capacitance. As a result, the value of CP can be estimated from the number of pulses within the detection period. Figure 3.4 describes the operation of the proposed CDC, where M is the total number of operation cycles in one detection period. Within each cycle n, there are two phases, charge sampling (Φ1 = H) and charge summing (Φ2 = H). In the first cycle (n = 1), the operation of the CDC starts with discharging CP (activated by the RST signal), which will make
Vx(1) = 0 V and sigma-delta modulator output Vo = L. Assuming Vin is a constant DC voltage, from the second cycle (n = 2), the level of Vx will gradually increase due to the charge sampling and summing operation of the sigma-delta modulator until it reaches the threshold level of the comparator VTH. In this case, the node voltage Vx after each cycle is given by
n Cs CP k V(n)=(Vx in V) L (1 where m denotes the operation cycle when Vx exceeds VTH. In addition, the increment of Vx for each cycle is given as n-1 CsP ×C ΔV(n)=(Vx in V) L n (1 Once Vx (n) exceeds VTH (for n ≥ m), the sigma-delta modulator output will become “H”. In the next cycle n = (m + 1), the Vx (n) level will be less than VTH, and for the following cycle n = (m + 2), the Vx(n) level will be greater than VTH again due to the negative feedback operation of the sigma-delta modulator. As a result, the sigma-delta modulator will generate an output pulse sequence for the remaining (M - m) cycles. The total 28 number of output pulses within (M – m) cycles can be written as Npulse = (M- m) / 2 . (3.10) Figure 3.4 Proposed CDC Operation Assuming the sigma-delta modulator has a constant input, once the integrator output reaches the threshold level of the comparator VTH, the comparator output will become “H”, which will subtract a certain amount of feedback voltage from the input in the next clock cycle, thus making the comparator output “L” again. However, in the next clock cycle, the feedback voltage will be added to the input, thus making the comparator output to “H”. This operation will repeat and the comparator output will be alternating between “H” and “L” for each clock cycle, and this will be always valid for the first order passive sigma-delta modulator regardless of the value of G1 and G2. However, the value of Npulse will be mainly determined by the relative difference between G2 and G1. That is for G2 >> G1 (CP >> Cs), Npulse will be a small integer, since the step size ΔVx(n) will be small, 29 and it will take more cycles for Vx to reach VTH. On the other hand, if G2 ≈ G1, yet G2 > G1 (CP ≈ Cs, CP > Cs), Npulse will be a large integer, since ΔVx(n) will be large, which enables Vx to reach VTH faster. Therefore, Npulse is inverse-proportional to the value of CP. Considering the general capacitive (projected capacitance type) touch panels, the value of CP can vary anywhere from 10 pF to 50 pF depending on the panel condition (touched or untouched). Therefore, the touch sensor readout circuit should effectively detect the capacitance variation within this range. The range of detectable panel capacitances depends on the value of the sampling capacitance Cs. Figure 3.5 illustrates why, by showing time domain waveforms for the voltage output for proposed CDC, operating with M = 33 and Cs = 0.75 pF, for two different panel capacitance values, 10 pF and 20 pF. For the larger panel capacitance, it takes a longer time for the voltage to rise to the threshold, and so fewer pulses are generated. The range of detectable panel capacitances is limited because panel capacitances larger than a certain size cause there to be no output pulses. The value of the sampling capacitance Cs also determines the CDC resolution, or smallest panel capacitance change that can be detected. Figure 3.6 shows the results of a simulation experiment to explore the trade-off between CDC resolution and range. It determines how the number of output pulses Npulse varies with the panel capacitance CP for different Cs values. The results are obtained as follows. The sampling capacitor Cs is set to 0.25 pF, 0.5 pF, 0.75 pF, 1.0 pF and 1.5 pF in turn, and for each Cs value, the output pulse numbers are recorded while varying the panel capacitance CP. Pulse numbers verses panel capacitance are then plotted for different Cs. For this case, the 30 sigma-delta modulator input Vin = VDD (3.3 V), the comparator threshold VTH = VDD/2, and the total operation cycles per touch pattern M is set to 33. As shown, Npulse decreases linearly with CP, with a slope that is steeper for smaller values of Cs; thus, the CDC’s range of detectable panel capacitances is inversely proportional to the sampling capacitance. For example, for the proposed CDC using M = 33, with Cs = 0.25 pF, the CDC resolution is about 0.5 pF, but panel capacitances CP in only a relatively small range of up to 11 pF can be detected. By using a larger sampling capacitor of Cs = 1.5 pF, the CDC resolution is reduced to 4 pF, but the range of detectable panel capacitances is increased to 70 pF. Figure 3.5 CDC Output Waveforms with Cs = 0.75pF (a) CP = 10pF. (b) CP = 20pF 31 Figure 3.6 Proposed CDC, Pulse Number Versus Panel Capacitance with Different Sampling Capacitor Values (M = 33) The advantage of the proposed CDC is the relative small size sampling capacitor Cs compared to the panel capacitance CP and the usage of the supply voltage VDD for the sigma-delta modulator input; because using a small Cs saves the silicon area of the IC, and using the supply voltage for the readout circuit input simplifies the circuit. 3.3 CDC System Level Analysis In order to investigate the system performance of the proposed CDC including trade-offs between CDC resolution and detection range, a system level analysis of the CDC has been performed. For this analysis, the total number of operation cycles M was varied; the values 33, 65, 129, and 257 were used. The reason why these values are selected for M is because 1 cycle is for the reset, and the remainders of 32, 64, 128 and 256 cycles can make the resolution of the CDC 4, 5, 6 and 7 bits, respectively; since Npulse can range 32 from 0 to (M-1)/2, the resolution is log2[(M-1)/2]. In addition, the detectable capacitance range is determined by the value of the sampling capacitor Cs. For the analysis, five different values were used. Based on Figure 3.5, Table 3.1 shows the CP detection range for the different combinations of Cs value and M. As Cs and M increase, the capacitance range is extended; however the detection time is increased while increasing M. The resolution is determined by the Cs value, due to the different step size of ΔVx. Table 3.2 shows the CP resolution with different Cs values, and this result applies for all M values. It is shown that the resolution improves by using smaller Cs values, however this will reduce the capacitance detection range as illustrated in Table 3.1. Table 3.2 CP Detection Range with Cs and M. (Unit: pF) Cs [ pF ] M 0.25 0.5 0.75 1 1.5 33 11 25 35 50 69 65 24 50 70 100 138 129 48 100 140 200 276 257 96 200 280 400 552 Table 3.3 CP Resolution with Cs (M = 33) Cs [ pF ] 0.25 0.5 0.75 1 1.5 Resolution [pF] 0.5 1 2 3 4 To sum up, there are trade-offs between detection time, detection range and CDC resolution. The detection range gets wider with the sacrifice of the detection time and detection resolution. The best values of M and Cs could be selected based on the system requirements that the touch screen readout circuit will be implemented on. 33 CHAPTER IV EFFECT OF NON-IDEALITIES So far, the proposed touch sensor readout circuit has been presented with ideal components and under ideal conditions. However, in reality, there are many non-ideal conditions which may affect the system performance. Some major non-idealities and the effects will be discussed in this chapter. The major non-idealities that can affect the performance of the proposed passive sigma-delta modulator based touch sensor readout circuit include parasitic capacitance, capacitor error, and comparator offset. In order to figure out the tolerable limit of the readout circuit, the effect of each non-ideality on circuit performance is analyzed. Furthermore, simulations are performed to investigate the effect of each non-ideality. Figure 4.1 shows the proposed CDC with the non-idealities, where Cpx, Cpy, and Cpz represent the parasitic capacitance at nodes x, y and z, respectively, and ε denotes the capacitor error and Vos denotes the comparator offset. 34 Figure 4.1 Proposed CDC with Non-idealities 4.1 Parasitic Capacitance The different parasitic capacitance at each node is due to switch S1 ~ S4 parasitic, top and bottom plate parasitic of Cs, the reset switch and the panel capacitance selection switch parasitic. In order to analyze the effect of parasitic capacitance, the passive sigma- delta modulator coefficients G1 and G2 are re-derived in the presence of Cpx, Cpy, and Cpz. During the sampling phase (where S1 and S2 are closed), the voltage across the parasitic Cpx, Cpy, and Cpz is Vx(n - 1/2), Vin(n), and Vo(n - 1/2), respectively, where Vx(n - 1/2) and Vo(n - 1/2) represent the previous phase Vx node and the sigma-delta modulator output voltage, respectively. In the summing phase (when S3 and S4 are closed), charge sharing among the capacitors will occur, however, since both sides of Cpz are connected to GND, the effect of parasitic Cpz is negligible. Considering the initial charge stored in each capacitor, the total change for the summing phase can be written as QT (n +1/2) = Cs V Cs (n) + Cpy V in (n) + [Cp +C px ] V x (n-1/2) , (4.1) 35 where the voltage across Cs is given by VCs (n) = [V in (n) - V o (n-1/2)] , (4.2) Furthermore, assuming Vo(n - 1/2) = Vo(n), Vx(n - 1/2) = Vx(n), and Vx(n + 1/2) = Vx(n + 1), the node voltage Vx can be expressed as QT (n +1/2) Vx (n +1) = , (4.3) Cs + C p + C px + C py and re-arranging eq. (4.3) after taking the z-transform, the z-domain expression for Vx including the parasitic capacitance is given as -1 -1 -1 V(z)=zGx p1 V(z)-zG in p2 V(z)+zG o p3 V(z) x , (4.4) where Cs + C py G=p1 , (4.5a) Cs + C p + C px + C py Cs G=p2 , (4.5b) Cs + C p + C px + C py Cp + C px G=p3 Cs + C p + C px + C py . (4.5c) 36 Figure 4.2 Z-domain Block Diagram of the Passive Sigma-delta Modulator with Parasitic Capacitance As a result, the z-domain block diagram of the passive sigma-delta modulator with the parasitic is shown in Figure 4.2, where the “reversed” Z shaped block between Vx and Vo represents a comparator. Without the parasitic capacitance, Gp1 and Gp2 are identical to G1 given in eq. (3.6a), and Gp3 is identical to G2 given in eq. (3.6b). It is clear that parasitic capacitance Cpx and Cpy can affect the performance of the CDC by changing the coefficients. In order to further investigate the effect of Cpx and Cpy, the expression for ΔVx(n) including the parasitic capacitance is obtained using eq. (3.9) and Figure 4.1. In Figure 4.1, noticing the CDC output voltage Vo = L for n < m, which is equivalent to connecting Cs to GND, Cpx will be connected in parallel with Cp, and Cpy will be connected in parallel with Cs, during the interval n < m. Therefore, the expression for ΔVx(n) with the parasitic capacitance can be derived by adding Cpx and Cpy to Cp and Cs, respectively. That is n-1 (Cs +C py )×(C p +C px ) ΔVx,p (n) = Vin n (1 < n < m) . (4.6) (Cs + C p +C px +C py ) 37 Furthermore, to see the effect of the parasitic capacitance, the ratio between ΔVx(n) and ΔVx,p(n) is obtained, which is n n-1 ΔV (n) C C +C C x = s 1+ px py p . (4.7) ΔVx,p (n) Cs +C py Cs +C p Cp +C px As shown, the ratio between ΔVx (n) and ΔVx,p (n) will be very close to 1, since Cpx , Cpy << Cs , Cp, and n > 1. This implies the parasitic capacitance will not change the output pattern of the CDC much. The actual ratio ∆Vx(n)/∆Vx,p(n) for the entire range of the panel capacitance (10 pF to 50 pF) considering the worst case parasitic capacitance of the CMOS 0.35 µm technology where Cpx is estimated to be 200 fF and Cpy to be 50 fF, is from 0.982 to 0.998. The result is as expected from eq. (4.7), which verifies the robustness of the proposed CDC to parasitic capacitance. Table 4.1 shows Npulse with Cp for different Cpx and Cpy values, where Cs is set to 0.75 pF, and all other non-idealities are neglected. The results are obtained from circuit simulations by adding a Cpx of different values shown in the table to CP of the nominal value and Cpy to CS. The values for Cpx and Cpy are set considering the actual circuit where Cpx will be greater than Cpy. As shown, Npulse does not change much for the worst case Cpx = 200 fF and Cpy = 50 fF, and slightly changes until Cpx reaches 500 fF and Cpy reaches125 fF. The last column where Cpx = 500 fF and Cpy = 125 fF is to show the limit of parasitic capacitance when the circuit output pulse patterns begins to slightly shift. 38 Table 4.4 Npulse with Cp for Different Cpx and Cpy Cp Cpx = 100f Cpx = 200f Cpx = 500f Ideal (pF) Cpy = 25f Cpy = 50f Cpy = 125f 1 15 15 15 15 3 14 14 14 13 5 14 14 14 13 7 13 13 12 11 9 12 12 11 10 11 11 11 10 10 13 10 10 10 9 15 9 9 9 9 17 8 8 8 8 19 7 7 8 7 21 6 6 7 7 23 5 5 5 6 25 4 5 4 5 27 3 4 4 4 29 2 3 3 3 31 2 2 2 2 33 1 1 1 2 35 0 0 0 1 37 0 0 0 1 39 0 0 0 0 4.2 Capacitor Error The sampling capacitor Cs is an important component that determines Npulse, depending on the value of the panel capacitance Cp. The CDC performance is analyzed by applying a ±10% variation in Cs from the nominal value. A 10% variation is considered the worst case capacitor error (difference between the absolute and actual value of Cs) because of the given technology [14]. 39 Table 4.5 Npulse with Cp for ±10% Cs Error Cp Ideal Cs = 0.675f Cs = 0.825f (pF) ( = -10%) ( = +10%) 1 15 15 15 3 14 14 15 5 14 13 14 7 13 12 13 9 12 11 12 11 11 10 11 13 10 9 10 15 9 8 10 17 8 7 9 19 7 6 8 21 6 5 7 23 5 4 6 25 4 3 5 27 3 2 4 29 2 1 4 31 2 0 3 33 1 0 2 35 0 0 1 37 0 0 0 39 0 0 0 Table 4.2 shows Npulse with Cp for ±10% Cs error, where the nominal value of Cs is set to 0.75 pF. The results show a slight shift in the Npulse with Cp, however the basic Npulse pattern with Cp does not significantly change. The panel capacitance difference between the untouched case and touched case is above 5 pF for most projected touch screen panels, which will leave a big enough “gap” between pulse numbers for the two cases. In other words, for example, if a touch screen panel has the untouched panel capacitance above 21 pF and the touched below 15 pF, from which the pulse numbers will be detected as below 6 and above 9 with nominal Cs, by setting a “threshold” of 7.5 between untouched and touched cases, even with the worst case capacitor error, a 15 pF panel capacitance will have 8 pulses instead of 9. But 8 is still above the threshold of 7.5, 40 thus it still will be detected as the touched case. This implies the proposed CDC can tolerate the worst case Cs error for the given technology. 4.3 Comparator Offset Table 4.6 Npulse with Cp for Comparator Offset Vos C V p Ideal os (pF) 50mV - 100mV -100mV 50mV 1 15 15 15 15 15 3 14 15 14 15 14 5 14 14 13 14 13 7 13 13 12 12 12 9 12 12 11 12 11 11 11 11 11 11 10 13 10 10 10 10 9 15 9 9 9 9 8 17 8 8 8 8 7 19 7 7 7 7 6 21 6 7 6 6 5 23 5 6 5 6 4 25 4 5 4 5 3 27 3 4 3 4 2 29 2 3 2 4 1 31 2 2 1 3 0 33 1 1 0 2 0 35 0 0 0 1 0 37 0 0 0 0 0 39 0 0 0 0 0 Comparator offset is another non-ideality that can degrade the CDC performance. Comparator offset acts as a constant DC voltage added at the input of the comparator. Table 4.3 shows Npulse with Cp for different offset values, where Cs is set to 0.75 pF. Results show the output pattern of the CDC remains almost the same with offset up to ±50mV, however for offset of 100mV, a shift in the output pattern is observed. Results 41 show the positive offset has the similar effect as the positive capacitor Cs mismatch +s where the output pattern shifts to the same direction, and the negative offset has the similar effect as –s. This is because positive offset and positive capacitor Cs mismatch both reduce the effective VTH level of the comparator, and vice versa. 4.4 Supply Sensitivity Power line interference (50 Hz or 60 Hz) and SMPS noise (up to 300 kHz) can intrude into the touch panel by adding ripples on the supply voltage [15]. To investigate the supply sensitivity of the proposed CDC through circuit level simulations, a ripple is added to the supply voltage VDD, and the pulse numbers are measured with different ripples. The ripple is a sinewave ripple with amplitudes between 0 to 100 mV at the frequencies of 1 kHz, 10 kHz, 50 kHz, 100 kHz and 500 kHz. Table 4.7 Npulse with Supply Ripple of Different Amplitude and Frequency (CP=20 pF) Amp. Frequency (mV) 1 kHz 10 kHz 50 kHz 100 kHz 500 kHz 0 6 6 6 6 6 10 6 6 6 6 6 20 6 6 6 6 6 35 6 6 6 6 6 50 6 6 6 6 6 70 6 7 6 6 6 85 6 8 7 7 6 100 6 8 8 7 7 Table 4.4 shows Npulse with supply ripple for Cs = 0.75 pF, Cp = 20 pF (this is assuming the un-touched panel condition) and M = 33. The ideal Npulse without supply 42 ripple is 6. Results show the proposed CDC can tolerate supply ripple up to 50 mV for most of the frequency ranges. However, for ripple amplitude larger than 50 mV, the CDC performance is most critically affected when the ripple frequency is near the detection frequency fs/M, where fs is the sampling rate of the CDC (set to 1 MHz). This is the worst case where the CDC experiences the maximum supply voltage fluctuation within the detection period. Not much degradation is observed for other frequency ranges for the untouched case to be detected as touched or vice versa. With the worst case ripple frequency, the 6 pulse output under nominal conditions will be detected as 8 pulses, as explained in Section 4.2, the un-touched panel can be detected as touched. However, as shown in reference [16] and [17] due to the advance in CMOS switching regulator technology of using a Switching Noise Robust Charge-pump, the supply ripples can be easily suppressed within the 50 mV range [16], [17]. 43 CHAPTER V CIRCUIT IMPLEMENTATION This chapter presents the implementation of each part of the proposed touch sensor readout circuit. The design details of the passive sigma-delta modulator, the comparator and the panel capacitance selector are presented. Some simulation results of the comparator are also discussed in this chapter as the comparator is an important and independent component which may affect the overall readout circuit performance. 5.1 Passive Sigma-delta Modulator Figure 5.1 Transistor Level Circuit of the Proposed Passive Sigma-delta Modulator 44 The key component of the proposed touch readout sensor circuit is the passive sigma-delta modulator based CDC which consists of the sampling capacitor Cs, the touch panel capacitor Cp (used as the summing capacitor), switches, and the comparator. The transistor level passive sigma-delta modulator is shown in Figure 5.1. The sampling capacitor that is adjustable from 0.25 pF to 1.5 pF is realized with inter-digitized layout using a unit capacitor of 125 fF to improve the matching, where Figure 5.2 just shows Cs of 0.75 pF for simplicity. The four sampling switches S1~S4 are realized using CMOS transmission gates with PMOS (W/L)p = (4µ/0.35µ) and NMOS (W/L)n = (2µ/0.35µ), where the maximum on-resistance is set to 800 Ω. Considering the maximum Cp of 50 pF and operation clock period Ts of 1 µs (fs = 1 MHz), this leads to the RC time constant τ = 40 ns, which is less than Ts/2. This enables sufficient time for the Vx node voltage to settle within half of the sampling period. The reset switch S5 that discharges Cs and Cp is realized using an NMOS with (W/L)n = (20µ/0.35µ). 5.2 Comparator The details of the comparator which is between Vx and Vo from Figure 5.1 are discussed in this section. Figure 5.2 shows the comparator, where the pre-amp and the positive feedback is effectively combined in the input stage [18]. The comparator output is valid when clock VCK is “H”, and enters the reset mode when VCK is “L”. As a result, clock Φ1 is used for VCK, since the comparator has to operate when Vx node is completely settled at the end of the charge summing phase. In order to design the comparator with minimum power consumption, the comparator bias current IBias was first set to 10 µA with VCK clock frequency of 1 MHz which is the nominal operation frequency. Then IBias 45 was reduced until the comparator malfunctioned. Based on this experiment, the minimum IBias that still enables the comparator to properly function was 1 µA. Thus, by reducing IBias to 1 µA, the total power consumption of the comparator was reduced to 14.5 µW without degrading the comparator performance. Figure 5.2 Comparator Circuit Simulations of the comparator have been completed in the Cadence® Virtuoso® to show the comparator’s performance. The input offset and propagation delay are obtained from circuit simulations. Figure 5.3 shows the comparator input-offset results from Monte-Carlo simulations of 200 runs. The widths of the top four PMOS are generated from an online Monte-Carlo sequence generator for 200 sets, and each set of widths are used in the comparator circuit to run a simulation for a corresponding input-offset. Each input-offset voltage is obtained in simulation by holding the inverting input at 1.65V and applying a slow ramp from 20mV below to 20mV above the inverting voltage for 1ms to the non- 46 inverting input. The input-offset is the differential input voltage at the time when the comparator output is 1.65V. The 200 simulation results of the input-offset voltage are then summarized into the bar chart in Figure 5.3, from which the average deviation of 100μV and a standard deviation of 3.9mV are obtained, and they are both far away from the 50mV limit that the CDC output pattern just begins to shift as in Table 4.3. These results show that the comparator can produce the required comparator input-offset accuracy for the readout circuit. Figure 5.3 Comparator Offset Monte-Carlo Simulation Result In addition, the propagation delay of the comparator is also measured in Monte Carlo simulations. Each simulation is done by holding the inverting input at 1.65V and stepping the non-inverting input voltage from 10mV (worst case input-offset) below to 10mV above the inverting input for a rising edge step response. The step input is a 20mV step with a rise time of 1ns. The results show that the worst case propagation delay is 1.86ns, which is quite within the time that the comparator clock VCK remains “H” (0.5μs) in one cycle. Therefore, the CDC clock phase Φ1 will allow sufficient time for the comparator output to settle. 47 5.3 Panel Capacitance (Channel) Selector This block generates the control signals for the touch panel channel selection switches that connect each panel capacitance to the readout circuit. In order to cover the entire 10.4″ touch panel with 21 rows and 29 columns, each row selection switch is sequentially activated while the column selection switch is on. This operation is repeated with the next column switch until all the columns are scanned. The on-period of each row selection signals is equal to the detection period M, and the duration of the column selection signal is 29·M, where M can be adjusted to 33, 65, 129, and 257 clock cycles. However, to indicate the starting of the frame, the START signal will be generated when the first column and the first row switch is selected. In addition, the RST signal will be generated at the beginning of each row selection, to discharge the panel capacitance. The channel selection, START, and RST signals are realized with counters and digital logic. 48 CHAPTER VI EXPERIMENTAL RESULTS The proposed touch sensor readout circuit is implemented using CMOS 0.35 µm technology (4-metal, 2-poly) with supply voltage of 3.3 V. Figure 6.1(a) shows the chip micrograph, where common centroid and inter digitized layout techniques are used with dummy devices to improve the matching. In addition, analog and digital power lines are separated in order to eliminate the digital switching noise, and major analog signals such 2 as the integrator output Vx is shielded. The core area of the proposed circuit is 0.1 mm . Figure 6.1(b) shows the test setup including the test board and the touch panel. The test board is a 4 layer PCB, where the top and bottom plates are used for power supplies, clocks, CDC input/output signals with separate analog and digital domains. In addition, the intermediate layers are used for row and column panel capacitance selection lines. The comparator threshold voltage VTH is externally supplied from a DC power supply through a low noise amplifier (AD797, Analog Device), and the reference clock is provided from a clock generator. The touch panel is a 10.4″ projected mutual capacitance type. 49 Figure 6.3 Chip Micrograph (a) and Measurement Setup (b) The basic characteristics of the passive sigma-delta modulator including frequency spectrum, decimated output Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) plots, and offset error are measured. For this case in order to evaluate the sigma-delta modulator itself, M is set to 65, Cs is set to 0.75 pF and Cp is fixed to 1 pF, which makes the output pulse number 31 in one detection period of 65 clock cycles. By varying the input voltage Vin from 0 to 3.3 V, the output pulse number will change linearly with Vin, therefore the sigma-delta modulator is equivalent to a 5-bit ADC. Figure 6.2 shows the frequency spectrum of the passive sigma-delta modulator. A –6 dB sine wave with frequency of 1.0681 kHz is used as the input voltage. Although the 2nd and 3rd harmonic tones are present, the spectrum shows a first order noise shaping behavior. 50 Figure 6.4 Passive Sigma-delta Modulator Output Spectrum Figure 6.3 shows the decimated output DNL and INL plot. For an ideal n-bit ADC the output is divided into 2n uniform steps, and each step has the same fixed width. Any deviation from the ideal step width is defined as the DNL, and DNL errors accumulate to produce a total INL. To measure the DNL and INL, the input voltage range from 0 to 3.3V is divided into 32 equal levels with each level of 103mV corresponding to the 0 to 31 output pulse numbers, and each 103mV is again split into 4 intervals of equal width with each interval representing 0.25LSB. The pulse numbers are measured for each interval in each 103mV, the difference between the measured step width and ideal for one input level is the DNL for the corresponding digital output value as shown in Figure 6.3. The INL of each digital output value is obtained by accumulating the DNL values before that point. The results show that the maximum DNL and INL are 0.5 LSB and -0.75 LSB, respectively. 51 Figure 6.5 DNL and INL Plot of Decimated Sigma-delta Modulator Output Figure 6.6 Input-output Transfer Characteristic of Decimated Sigma-delta Modulator Furthermore, the offset error of the decimated sigma-delta modulator output is obtained. The offset error of an ADC is defined as the difference between the actual input value and the ideal input value of the starting points of the input-output transfer characteristic. To measure the offset error, the input voltages at which the digital output code increments by 1 are measured, and marked in the input-output coordinate as the transition points. By drawing a straight line which makes the transition points distributed 52 evenly along the line, the actual input-output characteristic is obtained. Figure 6.4 shows the measured and ideal input-output transfer characteristic, and only lower levels are shown for clarity. The offset error is measured to be 3.82 mV. Figure 6.7 Three Different Touch Locations for the Panel The operation of the sensor readout circuit is verified by monitoring the output waveform with different panel conditions (touched and un-touched) at different panel locations. Furthermore, in order to accurately capture the output waveform corresponding to each touch panel location, the RST and START signals are applied to the data acquisition unit (NI, DAQ USB 6361) that generates a trigger signal for the oscilloscope. The DAQ is pre-programmed to generate the trigger signal which enables the oscilloscope to capture the output waveform corresponding to arbitrary panel locations by counting the number of RST signals synchronized with the START signal. Figure 6.5 shows the three different panel locations (edge, middle and corner), where the panel is touched and untouched with a finger. The CDC operation is verified with different panel locations, since the panel capacitance variation can be different depending on the location [19]. Figure 6.6(a), (b), and (c) show the proposed CDC output waveform for the panel 53 edge, middle, and corner with touched and untouched condition. In this case, the sampling capacitor Cs is set to 1 pF with M = 33 for all cases. The yellow and blue waveforms represent the RST signal and the CDC output, respectively. The Npluse for edge, middle, and corner (un-touched : touched) are (8 : 11), (9 : 12), and (9 : 11), respectively. Based on Figure 3.5, this indicates the panel capacitance including the pad parasitic (1 pF to 2pF) and the PCB parasitic is around 22 pF to 27 pF for the un-touched condition, and changes to around 12 pF to 18 pF for the touched condition. The panel edge shows slightly larger capacitance than the middle or corner. However, the above results are for a specific touch panel. Other touch panels have different panel capacitance values, which may require different M and Cs values to accurately detect the panel condition. In addition, the touch sensor readout circuit total power is obtained from measuring the average currents from the analog and digital power supplies to the circuit using a multi-meter. The total power of the proposed touch sensor readout circuit is 65 µW, which is the product of the supply voltage of 3.3 V and the measured total current of 19.6 µA. 25 µW is consumed in the passive sigma-delta modulator and 40 µW is consumed in the panel capacitance selection block. 54 Figure 6.8 CDC Output Waveforms Corresponding to Each Touch Location (a) Edge (b) Middle (c) Corner The SNR of the proposed CDC is 31.4 dB, where the SNR is obtained using the touch strength and RMS touch noise collected from 100 different touch panel locations that are evenly distributed. The SNR measurement is based on the following equations [3], 55 SNR(dB)=20log(TouchStrength/NoiseTouchedRMS100 ), (6.1) TouchStrength=SignalTouchedAVG100 -SignalUntouchedAVG100 , (6.2) n=99 2 (Signal[n]-SignalTouchedAVG100 ) NoiseTouched = n=0 , (6.3) RMS100 100 where AVG100 means the simple numeric average of 100 data points and RMS100 means the root-mean-square of 100 data points. Although only the single touch has been demonstrated for simplicity, the proposed readout circuit can support multi-touch, since the panel capacitance variation for each row and column are scanned, and sent to the signal processing block such as the external microcontroller which can detect multiple touched locations on the panel based on the capacitance value of each row and column. Table 6.8 Performance Comparison with the State-of-the-art Capacitive Touch Sensor Readout Circuits This Ref. [ 12 ] [ 13 ] [ 15 ] [ 19 ] [ 20 ] [ 21 ] [ 22 ] work CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Technology 0.18µm 0.18µm 0.18µm 0.35µm 90nm 0.35µm 0.35µm 0.35µm # of 20 × 16 12 × 12 30 × 24 37 20 × 16 54 × 32 43 × 27 29 × 21 channels Scan rate 65Hz - 240Hz - 120Hz 60Hz 120Hz 50Hz SNR 24dB - 55dB - 30dB 38dB 39dB 31.4dB Core area 4mm2 0.26mm2 14.8mm2 2.5mm2 3.5mm2 13mm2 10.4mm2 0.1mm2 Power 19mW 108µW 52.8mW 1.15mW 12mW 26mW 18.7mW 65µW 56 Table 6.1 shows the performance summary of the proposed touch sensor readout circuit compared with the state-of-the art capacitive touch sensor readout circuits. The number of channels indicates the number of touch sensing patterns for the touch panel that are used with the sensor readout circuit. It is shown that the proposed circuit has the smallest area and lowest power consumption with comparable SNR. This is due to the compact CDC architecture based on the passive sigma-delta modulator that does not require active amplifiers and ADCs. Since the output of the sensor readout block is a sequence of pulses, where the panel capacitance is directly related to the number of the pulses within the detection period M, the panel capacitance can be detected by simply counting the pulses using an on-chip counter or an external micro-controller. The SNR can be improved by increasing the detection period M, since this will enable a higher CDC resolution, however this will have a trade off with the detection time (scan rate). Although the scan rate of the proposed readout circuit is relatively low compared to other works, it exceeds the maximum human finger movement frequency, which is around 10 Hz. This will make the proposed scheme still viable for portable touch panels. However, the scan rate can be increased by increasing the CDC sampling rate fs to be applicable for large size touch panels. 57 CHAPTER VII CONCLUSIONS AND FUTURE WORK In this thesis, a touch sensor readout circuit based on passive sigma-delta modulator CDC is proposed. By effectively using the touch panel capacitance as the summing element of the passive sigma-delta modulator, a compact and low power on- chip touch sensor readout block can be realized. Due to the passive sigma-delta modulator architecture, the proposed CDC does not require active amplifiers or an ADC, since the variation of the panel capacitance can directly be converted into the digital format by counting the number of output pulses within the detection period. Furthermore, using the supply voltage VDD as the sigma-delta modulator input simplifies the on-chip implementation as well. In addition, the effect of major circuit non-idealities including parasitic capacitance, capacitor errors, comparator offset and power supply sensitivity on the CDC performance are investigated. Results show the proposed CDC can tolerate parasitic capacitance up to 500 fF and sampling capacitor Cs error of ±10%, and is insensitive to comparator offset up to ±50 mV; it can also tolerate supply ripple up to 50 mV. The proposed CDC circuit is implemented with CMOS 0.35 µm technology with core area of 0.1 mm2. The operation is verified using a 10.4″ projective type capacitance touch panel with 29 × 21 channels; in experiments verifying the implemented design, the design achieves a SNR of 31.4 dB and a power consumption of 65 µW. Overall, the proposed scheme can be a good solution for portable mobile touch panel controllers due 58 to the compact architecture and low power consumption compared to other touch sensor readout circuit. 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