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Design, Fabrication and Testing of a Capacitive Sensor Using Delta-Sigma Modulation Charikleia Tsagkari University of Nevada, Las Vegas, [email protected]

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Design, Fabrication and Testing of a Capacitive Sensor Using Delta-Sigma Modulation Charikleia Tsagkari University of Nevada, Las Vegas, Clairetsagari0@Gmail.Com UNLV Theses, Dissertations, Professional Papers, and Capstones 5-1-2017 Design, Fabrication and Testing of a Capacitive Sensor Using Delta-Sigma Modulation Charikleia Tsagkari University of Nevada, Las Vegas, [email protected] Follow this and additional works at: https://digitalscholarship.unlv.edu/thesesdissertations Part of the Electrical and Computer Engineering Commons Repository Citation Tsagkari, Charikleia, "Design, Fabrication and Testing of a Capacitive Sensor Using Delta-Sigma Modulation" (2017). UNLV Theses, Dissertations, Professional Papers, and Capstones. 3049. https://digitalscholarship.unlv.edu/thesesdissertations/3049 This Thesis is brought to you for free and open access by Digital Scholarship@UNLV. It has been accepted for inclusion in UNLV Theses, Dissertations, Professional Papers, and Capstones by an authorized administrator of Digital Scholarship@UNLV. For more information, please contact [email protected]. DESIGN, FABRICATION AND TESTING OF A CAPACITIVE SENSOR USING DELTA- SIGMA MODULATION By Charikleia Tsagkari Bachelor of Science in Electrical and Computer Engineering National Technical University of Athens 2009 A thesis submitted in partial fulfillment of the requirements for the Master of Science in Engineering – Electrical Engineering Department of Electrical and Computer Engineering Howard R. Hughes College of Engineering The Graduate College University of Nevada, Las Vegas May 2017 Copyright 2017 by Charikleia Tsagkari All Rights Reserved Thesis Approval The Graduate College The University of Nevada, Las Vegas May 1, 2017 This thesis prepared by Charikleia Tsagkari entitled DESIGN, FABRICATION AND TESTING OF A CAPACITIVE SENSOR USING DELTA-SIGMA MODULATION is approved in partial fulfillment of the requirements for the degree of Master of Science in Engineering – Electrical Engineering Department of Electrical and Computer Engineering R. Jacob Baker, Ph.D. Kathryn Hausbeck Korgan, Ph.D. Examination Committee Chair Graduate College Interim Dean Peter Stubberud, Ph.D. Examination Committee Member Yahia Baghzouz, Ph.D. Examination Committee Member Evangelos Yfantis, Ph.D. Graduate College Faculty Representative ii ABSTRACT Capacitive sensing is a popular technology employed in billions of products and millions of applications. This Thesis details the design, layout and characterization of an Integrated Circuit (IC) that employs Delta-Sigma Modulation (DSM) for sensing capacitance. The chip, measuring 1.5 mm x 1.5 mm, was designed in On Semiconductor’s C5 process and was manufactured by MOSIS. The sensing circuit links linearly the ratio of a “test” to a “reference” capacitance to the output of a Delta-Sigma Modulator. The equations that describe the operation of the sensing circuit are derived. Besides the sensing circuit, there is a non-overlapping clock generator that provides the necessary clock signals for the circuit’s operation. There is also some peripheral circuitry that translates the digital output of the sensing circuit to an 8-bit binary number that can be used to calculate “test” capacitance and is immune to power supply voltage variations. The chip can sense any capacitance with an error as little as 0.07 % for some values in the pico-Farad and nano-Farad range by adjusting the reference capacitor and the input clock signal (30 kHz and 30 Hz respectively). The circuit operates on a nominal power supply voltage of 5 V and the maximum power dissipation of the entire circuit is 750 μW. The chip is also used for two applications, water level sensing and soil moisture content measurement. The capacitive sensor used for these applications is made on PCB and its capacitance is linearly related to water level and moisture content. iii ACKNOWLEDGEMENTS I would like to express my sincere gratitude and respect to my advisor Dr. R Jacob Baker, whose extensive knowledge, wise guidance and continued support helped me during my studies at UNLV. I greatly appreciate his contribution of time, ideas, and funding that made my MS degree a very productive and fulfilling experience. I am especially grateful for the excellent example he has provided me as a successful professional and a great professor. I would also like to thank the members of my thesis committee, Dr Peter Stubberud, Dr Yahia Baghzouz and Dr Evangelos Yfantis, for their encouragement and genuine support throughout my studies. iv For my husband, Kostas and my daughter, Fey. My strength, my inspiration, my life. Thank you. v TABLE OF CONTENTS ABSTRACT ................................................................................................................................... iii ACKNOWLEDGEMENTS ........................................................................................................... iv TABLE OF CONTENTS ............................................................................................................... vi LIST OF TABLES ......................................................................................................................... ix LIST OF FIGURES ........................................................................................................................ x CHAPTER 1: INTRODUCTION ................................................................................................... 1 CHAPTER 2: CIRCUIT DESIGN AND LAYOUT ...................................................................... 3 2.1 THE SENSING CIRCUIT .................................................................................................... 3 2.1.1 CLOCKED COMPARATOR OR SENSE AMPLIFIER .............................................. 5 2.1.2 SWITCHED-CAPACITOR CIRCUITS ...................................................................... 10 2.1.3 THE EQUATIONS FOR DELTA-SIGMA SENSING ............................................... 11 2.1.4 INCOMPLETE SETTLING ........................................................................................ 13 2.2 THE CLOCK GENERATOR ............................................................................................. 15 2.3 PERIPHERAL CIRCUITRY .............................................................................................. 17 2.3.1 THE D-FF .................................................................................................................... 19 2.3.2 THE COUNTER .......................................................................................................... 22 2.3.3 THE DAC .................................................................................................................... 23 vi CHAPTER 3: THE CHIP ............................................................................................................. 27 CHAPTER 4: SIMULATIONS .................................................................................................... 31 4.1 SIMULATING THE ENTIRE CIRCUIT ........................................................................... 31 4.2 SIMULATING THE SENSING CIRCUIT (WITHOUT PERIPHERAL CIRCUITRY) .. 34 4.3 SENSING LARGER CAPACITORS ................................................................................. 36 4.4 POWER DISSIPATION ..................................................................................................... 39 4.5 POWER SUPPLY VOLTAGE (VDD) VARIATIONS ..................................................... 41 CHAPTER 5: TEST RESULTS ................................................................................................... 44 5.1 CAPACITORS IN THE pF RANGE .................................................................................. 45 5.2 CAPACITORS IN THE nF RANGE .................................................................................. 47 5.3 POWER DISSIPATION ..................................................................................................... 49 5.4 POWER SUPPLY VOLTAGE (VDD) VARIATIONS ..................................................... 50 CHAPTER 6: DESIGN DISCUSSION ........................................................................................ 52 6.1 VOLTAGE AT THE “BUCKET” CAPACITOR (VBUCKET) ............................................. 52 6.2 COMPARATOR ................................................................................................................. 53 6.3 SWITCHED CAPACITORS .............................................................................................. 53 6.4 INPUT CLOCK SIGNAL................................................................................................... 54 6.5 COUNTER .......................................................................................................................... 55 6.6 POWER DISSIPATION ..................................................................................................... 55 CHAPTER 7: APPLICATIONS ................................................................................................... 58 vii 7.1 CAPACITIVE WATER LEVEL SENSOR........................................................................ 59 7.2 CAPACITIVE SOIL MOISTURE SENSOR ..................................................................... 61 7.3 APPLICATIONS DISCUSSION........................................................................................ 63 CHAPTER 8: CONCLUSION ..................................................................................................... 65 APPENDIX − SCHEMATICS AND LAYOUTS ........................................................................ 67 REFERENCES ............................................................................................................................
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