An Embedded Core for Sub-Picosecond Timing Measurements

AN EMBEDDED CORE FOR SUB-PICOSECOND TIMING MEASUREMENTS

Sassan Tabatabaei André Ivanov Vector 12 Corp. The University of British Columbia [email protected] [email protected]

Abstract equally difficult to verify in characterization stages and to guarantee in volume production stages of The continued market demand for GHz processors product development [9]. Typically, a sophisticated and high-capacity communication systems results in and expensive external instrument-based test setup is an increasing number of low-cost high volume ICs used to verify such timing specifications. However, with multi-GHz clocks and/or multi-Gb/s serial such setup is often difficult to integrate within communication interfaces. For such devices, timing production test environment and require large test specifications, e.g., jitter and skew, in the range of time. Alternatively, some chips exploit certain on-chip few picoseconds (RMS and/or p-p) are common. We functional testing capability, e.g., loop-back describe an embedded core that allows such techniques [6]. Unfortunately such techniques tend measurements. The core is small, functionally non- to be inadequate for direct measurement and test of intrusive, and easily scalable for testing multiple certain key device performance parameters. circuits and signals on the chip. To reach the required sub-picosecond accuracy, we present a In [7], we reviewed major techniques for timing novel measurement and data processing technique, measurement, introduced the concept of embedded based on noise scaling. The core has a standard timing analysis (ETA) for SoCs, and described a low-speed serial interface. circuit core able to perform key timing specification measurements. We also described the general 1. Introduction architecture of an embedded timing processor (ETP) that allows for the measurement of critical SoC timing This paper focuses on testing timing specifications of signals. A key circuit of this core is an embedded time multi-GHz clock rate ICs and multi-Gb/s to digital converter (ETDC). In this paper, we communication ICs. The continued market demand introduce a new technique developed to reach sub-ps for GHz processors and high-capacity communication RMS jitter measurement accuracy in less time as systems results in an increasing number of low-cost compared to the technique in [7]. We illustrate the high volume ICs clocked at GHz rates and beyond core’s use for jitter specifications testing and present and/or equipped with multi-Gb/s serial interfaces. For simulation results. example, the production of SONET OC-192 (10 Gb/s) CMOS ICs has recently been announced [1][2]. 1.1. Overview of Techniques for Testing Circuits to generate and distribute the timing signals Timing Specifications for multi-GHz regimes also currently capture much attention [3][4][5]. The circuits achieving such clock Techniques proposed for measuring timing and/or data rates are characterized by very stringent specifications in digital applications, e.g., frequency, timing specifications, often dictated by governing jitter, skew, delay, and timing variations, can be standards (e.g., SDH, SONET, ATM) in the case of grouped into two main categories: communication ICs. Signal sampling and frequency domain techniques Jitter and skew are types of important timing These techniques are based on sampling the signal specifications that are specified in many serial with high resolution and performing time-domain or communication standards. For GHz and gigabit frequency domain analysis to extract phase communication ICs, jitter specifications in the range information. Many sampling oscilloscopes perform of few picoseconds (ps) RMS and/or peak-to-peak are timing measurements by estimating the signal common. Such timing specifications are not only threshold crossings from the collected samples. The extremely challenging to meet in design but are well-known eye-diagram [11] method falls in this

category. Frequency domain analysis also provides allowing for robust and programmable on-chip information about phase or frequency modulation implementation. However, our main contribution lies components of a signal, which relate to the signal primarily in having introduced special features to this timing specifications [12]. Indirect sampling methods basic technique to overcome the accuracy limitations have also been used to estimate the jitter using ADCs arising from various noise sources while reducing the [15]. Such techniques are difficult to use as the basis measurement time as compared to the technique in [7]. for embedded timing measurements because of the That is, we developed novel circuit features and need for on-chip high-resolution high-speed ADCs. measurement data processing to estimate and subsequently cancel the oscillator noise jitter based Time domain techniques on a new noise scaling technique. We refer to this These techniques use only a select set of signal capability of exceeding noise barrier limitations as threshold crossings to estimate timing specifications. noise floor tunneling. The new EDTC achieves a high This feature makes them more suitable for on-chip accuracy measurement capability in the presence of implementation, and particularly attractive for low- on-chip noise, while still using practical and easily voltage process technologies, i.e., those typically realizable circuit techniques. used for high-speed devices. Examples of time domain techniques include frequency meters and counters, The remainder of this paper is organized as follows. phase detectors, time interval analyzers (TIAs), time- Section 2 describes the core circuits and their to-digital converters (TDCs), jitter samplers, delay operation. Section 3 focuses on the analysis of the estimators, and logic samplers (for statistical jitter noise that affects the accuracy of the ETDC. Then we measurement) [8][13][14][16][17][18][23][24]. illustrate how the noise floor limitations can be overcome (noise floor tunneling) using RMS jitter One class of such techniques is referred to as Vernier measurements as an example application. Section 4 Oscillator. These techniques use the difference presents simulation results when applying our ETDC between the periods (or frequency) of two oscillators to jitter testing. Finally, Section 5 concludes. to quantize a time interval. A number of different implementations based on this technique have been 2. Embedded Time to digital Converter disclosed that use two, three, or more oscillators (ETDC) Core [20—24]. A recent US patent [24] discloses a jitter Figure 1 illustrates the block diagram of our time to testing technique based on measuring periods of a digital converter (ETDC) circuit core. The ETDC PLL output and using a histogram to estimate the measures a time interval T : peak-to-peak and RMS jitter. This technique is d relatively easy to integrate on-chip if ring oscillators Td=-ttSTOPSTART (1) are used. However, the accumulation of period jitter

in the free-running oscillators will limit the achievable where tSTART and tSTOP are the time instances at which accuracy. Placing the oscillators in close proximity the rising edges of STOP and START signals occur, can attenuate the effects of power supply and respectively. The Double-Resolution Time Quantizer substrate noise-induced jitter. However, the remaining (DTQ) block quantizes time with a resolution of TDf , relative jitter between the oscillators will typically which is set by the Resolution Adjustment (RA) prevent achieving the accuracy required for block to a value less than a programmable threshold. measuring timing specifications associated with GHz The three counters connected to the DTQ hold three ICs. In [7], we introduced a novel TIA architecture numbers upon completion of an interval measurement: that achieves high-accuracy timing and jitter fine, coarse and noise-floor numbers. These numbers measurement through noise estimation and contain information to estimate the input interval and cancellation. The noise cancellation relies on a new also characterize the noise-floor on the ETDC. Since technique that we refer to as noise scaling. the DTQ maximum measurement range is limited, the The remainder of this paper describes a new Range Extender (RE) block is used to extend the embedded time to digital converter (ETDC), which capability of the DTQ for measuring longer time enables embedded time analysis with unprecedented intervals. The Calibration Controller calibrates the accuracy in standard CMOS technology. This ETDC DTQ using a reference clock to provide a precise

core is scalable to support multiple test points and its estimate of TDf . The TDC Controller controls the performance and functionality can be traded-off communication and sequence of operation of the between off-chip and on-chip processing. Like the different blocks. circuit in [7], this circuit employs two ring oscillators

Paper 5.3 130

also reduce noise effects. The block diagram of our TDC Range new DTQ and associated waveforms appear in Controller Extender (RE) Figures 2(a) and (b). Ref STOP

START Trigger Ring STOP Double-resolution clkB b[k:0] Oscillator B Calibration Time Quantizer (OscB) Controller (DTQ) rst Resolution Coincidence Coincidence Adjustment Switching CRS_flag Detector 1 Detector 2 inputs Controller Noise- Fine coarse floor START NF_flag counter counter Resolution counter EOC_flag Adjustment Trigger Fine/Crs rst Ring clkA Controller (RA) a[k:0] Oscillator A Coarse Fine Counter Noise-floor N Nc Nnf (OscA) f Counter (CounterFine) Counter (CountrCRS) (CounterNF) Enable Enable Enable Figure 1: Block diagram of the ETDC circuit CRS_flag CRS_flag EOC_flag (a)

START Coarse Fine 2.1. Notation and Definitions counter counter stops stops The notation and definitions used in the remainder of STOP Noise-floor this paper follows. Note that any variable denoted by counter stops t refers to an instant in time, T refers to a time clkA interval, and t refers to a time delay associated with a physical structure in the circuit, e.g., gates, routing, clkB etc. Fine resolution · tSTART : time instance when the START signal is CRS_flag Coarse set HIGH EOC_flag resolution

· tSTOP : time instance when the STOP signal is set NF_flag HIGH

· Td=-ttSTOPSTART : time interval to be measured (b) · clkA: output signal of oscillator A (OscA) Figure 2: DTQ: (a) block diagram, (b) waveforms · clkB: output signal of oscillator B (OscB) · T ( T ): clkA (clkB) period A B The DTQ is comprised of two oscillators: OscA,

· t Xi(): time instance when the i -th rising edge of triggered by a START edge; and OscB, triggered by a clkX ( XA= or B ) occurs. STOP edge. The oscillator periods are initially different by approximately 2% to 10% (typically, 40 - · TDf : DTQ fine resolution. 200 ps). This corresponds to the coarse resolution. · T : DTQ coarse resolution Dc After both oscillators begin oscillating, their · N f : fine counter number respective i -th edges start getting closer to each

· Nc : coarse counter number other, until they finally coincide for some value of i . Some time before the coincidence occurs, the period · N nf : noise floor counter number of one of the oscillator switches to fine resolution · MM(): output state of the k-bit counter AB such that the difference between the oscillator CntrA(CntrB) in RE circuit periods is of the order of 0.1% to 0.5% of the OscA period (typically, 2 – 10 ps). OscA output is 2.2. Double -Resolution Time Quantizer connected to three counters: fine counter that counts (DTQ) the clkA cycles from the start of the oscillation to the As in [7], we use a DTQ instead of a single-resolution time when the oscillation period is switched, the time quantizer to accelerate the measurements and coarse counter that counts the oscillation cycles from this time to the first coincidence time, and noise-floor

Paper 5.3 131

counter that counts clkA cycles from first coincidence time to the second coincidence time. The fine and

coarse counters are sufficient for measuring the input clkB interval, but the noise-floor counter is used to provide additional information required for estimating the rst NF_flag Stop ETDC noise floor, as will be shown in Section 3.1. clkA

Figure 3 shows a particular DTQ implementation. Ring rst CRS_flag NF_flag Start oscillator architecture is used for OscA and OscB, clkB SET SET SET CRS_flag and Triple D flip-flops are used as phase detectors [7]. clkA D Q D Q D Q EN OUT Coarse Q Q Q counter D1 CLR CLR CLR The delay element D1 in Figure 3 contributes a delay rst EOC_flag SET SET SET of t between the i -th edges of clkA and clkB. D Q D Q D Q EN OUT fine Fine counter

CLR Q CLR Q CLR Q Such delay ensures that CRS_flag is set LOW before D2 rst NF_flag the EOC detector is activated, switching the SET SET SET D Q D Q D Q EN OUT NF resolution from coarse to fine. The counters counter Q Q Q CLR CLR CLR rst CounterCRS, CounterFine, and CounterNF hold the rstb_DFF

coarse (Nc ), fine (N f ), and noise floor (N nf ) rstb_cntr measurement numbers, respectively. Figure 3: DTQ implementation The delay D2 in clkB path is used to generate a second coincidence event, resulting in the

accumulation of the number N nf in the noise-floor 2.4. Measurement Range Extension counter. From the waveforms in Figure 2(b), if TTDT, where is the duty cycle of clkB, At the end of each measurement sample, the TDC d>AB-* D generates three numbers: coarse, fine, and noise-floor EOC_DFF will sample a HIGH at the second rising edge of clkA, erroneously signaling an end-of- numbers, which are related to Td as follow: conversion. Also, if TTdC< , the first rising edge of Td=+NcTDDcNfTTTTfCQR--+11 (2a) clkA will sample a HIGH regardless of the value of Td . Therefore, the valid measurement range of T for this Td=NcTDDc++()NfNTnff d (2b) circuit is -<

where T is a constant offset time, T and T are A Range Extender (RE) circuit, shown in Figure 4, C Q 1 Q 2 extends this range. The RE generates a flag signal the quantization errors, and TR1 and TR2 are random (RE_Flag) when -TC<-ttB(i)A()i

number in CntrA (i.e., M A ) remains larger than the 2.3. Measurement Time number in CntrB (i.e., M B ) as long as tt->T-*DT. The “Comp & Latch” block To estimate the DTQ measurement time (Tmeas ), B(i)A()iAB assume that the error terms in Eqn. 2b are negligible. contains a comparator and a latch. When ttTDT, for a short duration Then TdC+T+t D2 =NcTDDc++()NfNTnff. Since it B(i)-A()i<-*AB , causing the comparator to generate a takes NNNN=++cfnf cycles of clkA to perform a MMAB= time interval measurement, the measurement time is: pulse that becomes wider at the subsequent clkB rising edges. This pulse, when sufficiently wide, TT+-+ttt T=+(NN+N)TT=+()dCfinefineD2 activates a latch to set the RE_Flag, allowing the meascfnfAA(3) TTDDcf valid EOC_flag to pass through. We used time- diversity sampling within the “Comp and Latch” block

Paper 5.3 132 to avoid the risk of erroneous RE flag due to glitches TTd(,2)i= 2 ref and ttfine= fine1 . generated by asynchronous counter output switchings. More details regarding the RE’s operation TTd(,3)i= 4 ref and ttfine= fine1 . is found in [25]. These measurements are repeated for iM= 1, ..., cal

clkA and each set is averaged over Mcal samples. This Counter yields the three following equations: t re (CntrA) M A clkA_re NF_flag Ncf(1)TDD(cfC)+N(1)TT()=d(1)+T++TTQR(1)(1) Comp RE_flag & Latch Ncf(2)T+N(2)TT=d(2)+T++TTQR(2)(2) Counter DD(cfC)()

(CntrA) M B clkB Nc (3) TDD(cfC)+Nf (3)TT()=d(3)+T++TTQR(3)(3) END_flag

(a) where X represents the average value of X . For

sufficiently large Mcal , the noises due to TR and TQ M A, MB

M A terms, and also the jitter in the reference clock are reduced to negligible values due to noise averaging M B [25]. The selection of two different values of t fine1 and

t fine2 for calibration ensures a non-singular characteristic determinant for the above system of equations, which is essential for reliable calibration. The resulting equations can be solved to compute

TDc , TDf and TC . Assuming 50 ps RMS jitter in RefClk, and 30 ps jitter in the oscillators A and B, this

scheme estimates TDc and TDf to within 1% accuracy

M A = M B with Mcal = 5000 samples [25]. RE_flag END_flag 2.6. Automatic Resolution Adjustment (b) (RA)

The circuit in Figure 3(a) provides a high resolution, Figure 4: Range Extender (RE), (a) block diagram, (b) i.e., a small TDf , by generating a small difference waveforms between the loop-around delays of OscA and OscB. However, any mismatch between the gate delays and 2.5. DTQ Calibration interconnect wiring in the OscA and OscB can cause

a significant increase TDf , resulting in resolution In practice, TDc and TDf will vary from one cycle of clkA and clkB to the next due to jitter in OscA and degradation and increased quantization noise. The OscB. In Eqn. 2a, the oscillator noise effects are mismatch can also result in TTAB< , causing a lumped into the term TR1 . Hence, TDc and TDf are in measurement error. fact average values of fine and coarse resolution. For To overcome the effects of mismatch, we use an accurate calibration, we replace the delay D1 in the automatic resolution adjustment technique. Using this DTQ with a delay element whose delay can be technique, TA and TB are controlled digitally to switched between two different values, t fine1 and ensure 0 <

Tref to perform Mcal sets of calibration replacing a number of the delay elements in OscA and measurements. The i -th set includes the following OscB with controllable delay elements (CDE), which three calibration measurements: increase TA or TB when activated.

TTd(,1)i= ref and ttfine= fine2 .

Paper 5.3 133

Assume that some CDEs are activated. The resolution supply and substrate noise in each of OscA and adjustment circuit measures two known time intervals, OscB. However, for common mode noise sources due

e.g., Tref and 2Tref , with a single resolution of TDf to to power supply and substrate noise, the differential yield two numbers. The difference N between the architecture of the DTQ will attenuate such noise D significantly. Typically, the differential structure of two resulting counts is then determined. Assuming the DTQ reduces the effect of power supply and the measurement error is negligible, N and T are D Df substrate noise by a factor of 8 to 10 [25].

related by Treff= NTDD. Since Tref is constant, a

larger ND indicates a smaller TDf . A controller circuit 3.1. Example ETDC Application: RMS Jitter Measurement monitors ND and adjusts the CDEs to achieve a

desired TDf . An important specification of many timing circuits, such as PLLs and DLLs is RMS jitter. In the following, Different adjustment algorithms are possible [25]. We we illustrate the use of our ETDC to measure RMS refer to one such algorithm as incremental step delay jitter accurately. adjustment. In this scheme, the CDEs are designed We define RMS jitter in the time interval Td time such that tAA= xt , where t A is the delay CDEiiCDE -1 CDEi intervals as follows: added to the total ring oscillator loop delay when A 1 M CDEi is activated, and 12<

3. Noise Performance Analysis and RMS is the average of the Tdi()'s. Jitter Measurement From Eqns. 2a and 6, for sufficiently large values of From Eqn. 2a, one of the major sources of 2 M , J RMS is estimated from the following equation measurement error is T , which arises from different R1 [7][25]: noise sources in the DTQ. Assuming random noise 2222 sources within OscA and OscB as the major error JRMS=TTRMS--DfR/12 s 1 (7)

sources [7], the variance of TR1 is given by: 1 M where TT22=-()NN. 22 RMSfiD å i-1 ssRg1 = 4NM (4) M

In Eqn. 7, TDf is known from calibration. The RMS where NNN=+cf is the total number of clkA cycles for measuring an interval, M is the number of error of this estimation is: 222 gates in the ring oscillator A or B, and s g is the ss2 =+2/(MTDfR/12)1 (8) J RMS standard deviation of noise for each gate in OscA and OscB. Similarly, the following yields the standard This error can be very small by making M large (e.g., range from 1000 to 100,000). From Eqn. 7, the accuracy deviation of TR2 : of RMS jitter measurement does not depend on the 22 (5) ssRg22= 4NM resolution TDf because this value can be estimated 2 accurately through calibration. Since, reducing s R1 where NNNN2 =++cfnf . implies a difficult design challenge, we use a special Eqn. 4 and 5illustrate the noise accumulation problem 2 technique to estimate s R1 accurately and perform in ring oscillators as it shows how the RMS noise is specific computations to effectively overcome its directly proportional to the number of transitions in effects, and achieve what we refer to as noise floor the ring oscillator. In Sec. 3.1, we describe a novel tunneling. This technique is less limited by design noise scaling technique where we exploit this quality, and therefore scales much more readily to accumulation behavior to estimate and subsequently different chips and processes. achieve increased accuracy. The independence assumption may not necessarily hold for power

Paper 5.3 134

As evident from Eqn. 7, it is possible to estimate the JTAG TAP is used to transfer data for off-chip input jitter accurately if the internal jitter of the ETDC processing. is known. The general form of Eqn. 7 is: START 222 Start ssstot=+ip int (9) High STOP D Q D Q Stop 2 where s tot is the variance of the jitter estimated from DFF1 DFF2 TDC 2 IN1 2 clk clk rst the raw measurements, and s ip and s int are the rst SCLK clk variances due to the ETDC input (signal under test) Ref RefClk jitter and due to the EDTC’s internal component (e.g., oscillators, gates) jitters, respectively. We next Nc, Nf, Nnf describe how our new EDTC uses noise scaling [7] to next_sample To accurately estimate the input jitter. SCLK Main JTAG Controller TAP Eqns. 4 and 5 indicate that the variance of the internal jitter increases with the number of OscA cycles necessary to complete the measurement. After Figure 5: Edge sampler (ES) for period jitter calibration, From Eqns. 2a and 2b, we form Eqns. 10a measurement and 10b, respectively: 4. ETDC Simulation Results s2=+ss22 (10a) tot(1)1ipR We simulated our circuits to evaluate the effectiveness of noise tunneling technique. To s2=+ss22 (10b) tot(2)2ipR accelerate the simulations, a C model was developed

2 2 for the circuits to simulate the jitter measurement where s and s are the total jitter measured tot(1) tot(2) process. The plots in Figure 6 illustrate how our noise with and without considering N nf . From Eqns. 4 and estimation and cancellation technique is essential for 2 2 accurate measurement. 5, s R1 and s R 2 are related with a scaling factor a =+(NNcf++Nnfcf)/()NN, hence the term The plots illustrate the measurement accuracy results noise scaling. from simulations at 1 GHz for several values of the 2 input signal jitter (s in ), and ETDC internal jitter s R1 Under a random noise assumption, it is possible to (s 2 is expressed as RMS period independent random achieve arbitrarily high measurement accuracy using R1 this technique by making M sufficiently large, period jitter in OscA and OscB). As evident from regardless of the input or internal noise distribution. these plots, our noise cancellation scheme provides For example, measuring RMS jitter in a 10 GHz signal accurate estimates of input jitter by estimating and with 0.1ps accuracy can be achieved using canceling the ETDC internal noises. Plot (a) and (b) in approximately M = 80,000 samples in a noisy Figure 6 show that accuracy increases with an environment. This implementation of noise scaling increase in the number of samples, while this would scheme provides the same accuracy with not occur without using the noise tunneling approximately half the number of samples than the algorithms (plot (c)). These plots indicate an increase scheme in [7]. This is because, effectively, the of accuracy by a factor of 1.5 to 2 as compared with intervals used for normal and noise floor samples are the results in [7] for the same total number of period the same, as opposed to coming from different sample samples. The apparent saturation of accuracy for low s 2 values is due to quantization noise effects. sets of a statistical superset. Also, this method R1 reduces test time due to reduced number of samples. Table 1 reports the number of samples and An application of the ETDC is to measure RMS period measurement time required for measuring RMS jitter jitter, as shown in Figure 5 [7]. The current version of for different signal frequencies [26]. Typically, the our design allows for test controller to pass two measurement time increase significantly at higher consecutive edges of IN1 to the ETDC. This speeds because of the need for higher accuracy. procedure can be repeated until a predetermined However, even for the very high accuracy required at number of samples of the input signal periods are high speed, the measurement can be completed in 80 measured allowing for variance and peak-to-peak jitter ms or less. The measurement time, include sample to be computed, easily either on-chip or off-chip. A

Paper 5.3 135

measurements, data transfer to off-chip, and Table 1: Total measurement time for RMS processing on a host computer. jitter measurement

Frequency RMS RMS # of Total (MHz) jitter accuracy samples measu- under desired required rement test (ps) time (ps) (ms) 500 20 2 1,000 3 1,000 10 1 2,000 8 2,000 5 0.5 5,000 8 5,000 2 0.3 40,000 28 10,000 1 0.2 80,000 60

5. Conclusions We presented a novel embedded circuit core aimed at performing high-resolution/high-accuracy timing measurements. The accuracy can be of the order of sub-picoseconds in standard CMOS. This capability is particularly useful for testing critical timing specifications of rapidly emerging GHz and Gb/s ICs and SoCs. The circuit is particularly attractive since it amounts to small area. The main contributions of this paper are the added circuit and data processing techniques and features aimed at achieving accuracy not otherwise possible due to oscillator noise limitations. The high accuracy performance is achieved by exploiting a novel noise estimation and cancellation technique based on noise scaling that allows for the measurement accuracy to exceed that otherwise dictated by the chip noise floor, what we refer to here as noise floor tunneling. The attractive feature of our noise floor tunneling is that it requires only simple computation and therefore can easily be performed off-chip by a standard processor or performed on-chip on a simple dedicated processor. Trade-offs in test time and accuracy are possible giving the circuits and associated techniques further flexibility. This EDTC can be used within the scalable embedded time interval analysis (ETIA) architecture described in [7] to satisfy practical implementation requirements, such as closeness to test points, support of multiple test points, and better digital noise immunity.

Figure 6: RMS jitter measurement accuracy (f = 1 The extensions of our work aim at the accurate GHz), (a) 20,000 period samples with noise measurement of many other specification such as tunneling, (b) 100,000 period samples with noise long term jitter, cycle-to-cycle jitter, jitter harmonics, tunneling, (c) 20,000 and 100,000 period samples jitter transfer, pattern dependent jitter, frequency, without noise tunneling period, skew, delay, PLL/DLL lock time, PLL frequency response, PLL step response, rise/fall time, etc. We are also developing techniques and algorithm

Paper 5.3 136 to maintain high accuracy in the case periodic noise [14] L. D. Smith and Norman E., “On-chip PLL phase sources due to different clock sources on the chip. and jitter self-test circuit,'' US Patent #5889435 assigned to Sun Microsystems Corp., March

1999. References [15] S. Cherubal and A. Chatterjee, “A high-resolution jitter measurement technique using ADC [1] M. Green et al.,“OC-192 Transmitter in Standard sampling,” Proc. of Int. Test Conf., pp. 838-847, 0.18mm CMOS”, Digest of Technical Papers of 2001. the IEEE ISSCC, San Francisco, CA, Feb. 2002, [16] Dan Porat, “Review of sub-nanosecond time- pp. 248-249. interval measurements,” IEEE Trans. on Nuclear [2] J. Cao et al.,“OC-192 Receiver in Standard 0.18mm Sciences, vol. Ns-20, pp. 36-51, October 1976. CMOS”, Digest of Technical Papers of the IEEE [17] D. M. Santos, “A CMOS delay locked and sub- ISSCC, San Francisco, CA, Feb. 2002, pp. 250- nanosecond time-to-digital converter chip,” IEEE 251. Trans. on Nuclear Science, vol. 43, pp.1717-1719, [3] I. Hwang et al., “A Self-Regulating VCO with June 1996. Supply Sensitivity of <0.15%-Delay/1% Supply”, [18] J. Kalisz, R. Szplet, J. Pasierbinski, and A. Digest of Technical Papers of the IEEE ISSCC, Poniecki, “Field-programmable-gate-array-based San Francisco, CA, Feb. 2002, pp. 140—141. time-to-digital converter with 200-ps resolution,” [4] C. Kim et al., “Low-Power Small-Area ±7.28 ps IEEE Trans. on Instrumentation and Jitter 1 GHz DLL-Based Clock Generator”, Digest Measurement, vol. 46, pp. 51-55, February 1997. of Technical Papers of the IEEE ISSCC, San [19] C. Kimsal and J. B. Wilstrup, “Time interval Francisco, CA, Feb. 2002, pp. 142 – 143. measurement system incorporating a linear ramp [5] P. Restle et al., “The Clock Distribution of the generation circuit,'' US Patent #6,194,925 Power4 Microprocessor”, Digest of Technical assigned to Wavecrest Corporation, February 27 Papers of the IEEE ISSCC, San Francisco, CA, 2001. Feb. 2002, pp. 144-145. [20] Z. Tarczy-Hornoch and P. Young, “Interpolating [6] Y. Cai, B. Laquai, and K. Luehman, “Jitter Testing time interval counter with course count ambiguity for Gigabit Serial Communication Transceivers”, elminating means,” US Patent #3,505,594 IEEE Design and Test, Vol. 19, No. 1, Jan./Feb. assigned to W. K. Rosenberry, April 7 1970. 2002, pp. 66 – 76. [21] Walter Curtice, “Time interval measurement,” US [7] S. Tabatabaei and A. Ivanov, “Embedded Timing Patent #4,165,459 assigned to RCA Analysis: A SOC Infrastructure”, IEEE Design Corporation, August 21 1979. and Test of Computers, vol. 19, No. 3, pp 24-36, [22] David Chu, “Double vernier time interval May-June. 2002. measurement using triggered phase-locked [8] B. Nadeau-Dostie, “Design For At-Speed Test, oscillators,” US Patent #4164648 assigned to Diagnosis And Measurement”, Kluwer Academic Hewlett-Packard Company, August 14 1979. Publishers, 2000 [23] A. Chan and G. Roberts, “A synthesizable, fast [9] International Technology Roadmap for and high-resolution timing measurement device Semiconductors, 2001 Edition. using a component-invariant vernier delay line,” [10] U. Shankar, “Test challenges for SONET/SDH Proc. of Int. Test Conf., pp. 858-867, 2001. physical layer OC3 devices and beyond,” Intl. [24] A. Frisch and T. Rinderknecht, “Jitter Test Conf., pp. 502-511, 2001. measurement system and method,” US Patent [11] M. Lauterbach, “Getting more out of eye #6,295,315 assigned to Fluence Technologies, diagrams,” IEEE Spectrum, pp. 60--63, March September 25 2001. 1997. [25] S. Tabatabaei, Embedded Test Circuits and [12] T. Yamaguchi and M. Soma, “A method for Methodologies for Mixed-Signal ICs. PhD measuring the cycle-to-cycle period jitter of high- thesis, The University of British Columbia, April frequency clock signals,” IEEE VLSI Test 2000. Symposium, pp 102-110, 2001 [26] S. Tabatabaei, “Timing Specification Built-In Self- [13] R. Kelkar, I. Novof, and S. D. Wyatt, “Integrated Test Circuits and Methodologies”, Internal circuit chip having built-in self measurement for Report, Vector 12 Corp., February 2001. PLL jitter and phase error,” US Patent #5663991 assigned to IBM Corp., Sept. 1997.

Paper 5.3 137