AN EMBEDDED CORE FOR SUB-PICOSECOND TIMING MEASUREMENTS Sassan Tabatabaei André Ivanov Vector 12 Corp. The University of British Columbia [email protected] [email protected] Abstract equally difficult to verify in characterization stages and to guarantee in volume production stages of The continued market demand for GHz processors product development [9]. Typically, a sophisticated and high-capacity communication systems results in and expensive external instrument-based test setup is an increasing number of low-cost high volume ICs used to verify such timing specifications. However, with multi-GHz clocks and/or multi-Gb/s serial such setup is often difficult to integrate within communication interfaces. For such devices, timing production test environment and require large test specifications, e.g., jitter and skew, in the range of time. Alternatively, some chips exploit certain on-chip few picoseconds (RMS and/or p-p) are common. We functional testing capability, e.g., loop-back describe an embedded core that allows such techniques [6]. Unfortunately such techniques tend measurements. The core is small, functionally non- to be inadequate for direct measurement and test of intrusive, and easily scalable for testing multiple certain key device performance parameters. circuits and signals on the chip. To reach the required sub-picosecond accuracy, we present a In [7], we reviewed major techniques for timing novel measurement and data processing technique, measurement, introduced the concept of embedded based on noise scaling. The core has a standard timing analysis (ETA) for SoCs, and described a low-speed serial interface. circuit core able to perform key timing specification measurements. We also described the general 1. Introduction architecture of an embedded timing processor (ETP) that allows for the measurement of critical SoC timing This paper focuses on testing timing specifications of signals. A key circuit of this core is an embedded time multi-GHz clock rate ICs and multi-Gb/s to digital converter (ETDC). In this paper, we communication ICs. The continued market demand introduce a new technique developed to reach sub-ps for GHz processors and high-capacity communication RMS jitter measurement accuracy in less time as systems results in an increasing number of low-cost compared to the technique in [7]. We illustrate the high volume ICs clocked at GHz rates and beyond core’s use for jitter specifications testing and present and/or equipped with multi-Gb/s serial interfaces. For simulation results. example, the production of SONET OC-192 (10 Gb/s) CMOS ICs has recently been announced [1][2]. 1.1. Overview of Techniques for Testing Circuits to generate and distribute the timing signals Timing Specifications for multi-GHz regimes also currently capture much attention [3][4][5]. The circuits achieving such clock Techniques proposed for measuring timing and/or data rates are characterized by very stringent specifications in digital applications, e.g., frequency, timing specifications, often dictated by governing jitter, skew, delay, and timing variations, can be standards (e.g., SDH, SONET, ATM) in the case of grouped into two main categories: communication ICs. Signal sampling and frequency domain techniques Jitter and skew are types of important timing These techniques are based on sampling the signal specifications that are specified in many serial with high resolution and performing time-domain or communication standards. For GHz and gigabit frequency domain analysis to extract phase communication ICs, jitter specifications in the range information. Many sampling oscilloscopes perform of few picoseconds (ps) RMS and/or peak-to-peak are timing measurements by estimating the signal common. Such timing specifications are not only threshold crossings from the collected samples. The extremely challenging to meet in design but are well-known eye-diagram [11] method falls in this ITC INTERNATIONAL TEST CONFERENCE Paper 5.3 0-7803-7542-4/02 $17.00 © 2002 IEEE 129 category. Frequency domain analysis also provides allowing for robust and programmable on-chip information about phase or frequency modulation implementation. However, our main contribution lies components of a signal, which relate to the signal primarily in having introduced special features to this timing specifications [12]. Indirect sampling methods basic technique to overcome the accuracy limitations have also been used to estimate the jitter using ADCs arising from various noise sources while reducing the [15]. Such techniques are difficult to use as the basis measurement time as compared to the technique in [7]. for embedded timing measurements because of the That is, we developed novel circuit features and need for on-chip high-resolution high-speed ADCs. measurement data processing to estimate and subsequently cancel the oscillator noise jitter based Time domain techniques on a new noise scaling technique. We refer to this These techniques use only a select set of signal capability of exceeding noise barrier limitations as threshold crossings to estimate timing specifications. noise floor tunneling. The new EDTC achieves a high This feature makes them more suitable for on-chip accuracy measurement capability in the presence of implementation, and particularly attractive for low- on-chip noise, while still using practical and easily voltage process technologies, i.e., those typically realizable circuit techniques. used for high-speed devices. Examples of time domain techniques include frequency meters and counters, The remainder of this paper is organized as follows. phase detectors, time interval analyzers (TIAs), time- Section 2 describes the core circuits and their to-digital converters (TDCs), jitter samplers, delay operation. Section 3 focuses on the analysis of the estimators, and logic samplers (for statistical jitter noise that affects the accuracy of the ETDC. Then we measurement) [8][13][14][16][17][18][23][24]. illustrate how the noise floor limitations can be overcome (noise floor tunneling) using RMS jitter One class of such techniques is referred to as Vernier measurements as an example application. Section 4 Oscillator. These techniques use the difference presents simulation results when applying our ETDC between the periods (or frequency) of two oscillators to jitter testing. Finally, Section 5 concludes. to quantize a time interval. A number of different implementations based on this technique have been 2. Embedded Time to digital Converter disclosed that use two, three, or more oscillators (ETDC) Core [20—24]. A recent US patent [24] discloses a jitter Figure 1 illustrates the block diagram of our time to testing technique based on measuring periods of a digital converter (ETDC) circuit core. The ETDC PLL output and using a histogram to estimate the measures a time interval T : peak-to-peak and RMS jitter. This technique is d relatively easy to integrate on-chip if ring oscillators Td=-ttSTOPSTART (1) are used. However, the accumulation of period jitter in the free-running oscillators will limit the achievable where tSTART and tSTOP are the time instances at which accuracy. Placing the oscillators in close proximity the rising edges of STOP and START signals occur, can attenuate the effects of power supply and respectively. The Double-Resolution Time Quantizer substrate noise-induced jitter. However, the remaining (DTQ) block quantizes time with a resolution of TDf , relative jitter between the oscillators will typically which is set by the Resolution Adjustment (RA) prevent achieving the accuracy required for block to a value less than a programmable threshold. measuring timing specifications associated with GHz The three counters connected to the DTQ hold three ICs. In [7], we introduced a novel TIA architecture numbers upon completion of an interval measurement: that achieves high-accuracy timing and jitter fine, coarse and noise-floor numbers. These numbers measurement through noise estimation and contain information to estimate the input interval and cancellation. The noise cancellation relies on a new also characterize the noise-floor on the ETDC. Since technique that we refer to as noise scaling. the DTQ maximum measurement range is limited, the The remainder of this paper describes a new Range Extender (RE) block is used to extend the embedded time to digital converter (ETDC), which capability of the DTQ for measuring longer time enables embedded time analysis with unprecedented intervals. The Calibration Controller calibrates the accuracy in standard CMOS technology. This ETDC DTQ using a reference clock to provide a precise core is scalable to support multiple test points and its estimate of TDf . The TDC Controller controls the performance and functionality can be traded-off communication and sequence of operation of the between off-chip and on-chip processing. Like the different blocks. circuit in [7], this circuit employs two ring oscillators Paper 5.3 130 also reduce noise effects. The block diagram of our TDC Range new DTQ and associated waveforms appear in Controller Extender (RE) Figures 2(a) and (b). Ref STOP START Trigger Ring STOP Double-resolution clkB b[k:0] Oscillator B Calibration Time Quantizer (OscB) Controller (DTQ) rst Resolution Coincidence Coincidence Adjustment Switching CRS_flag Detector 1 Detector 2 inputs Controller Noise- Fine coarse floor START NF_flag counter counter Resolution counter EOC_flag Adjustment Trigger Fine/Crs rst Ring clkA Controller (RA) a[k:0] Oscillator A Coarse Fine Counter