How Open Source and Collaboration aid Innovation in VLSI CAD
Gilda Garretón
Sun Microsystems Laboratories February 2010
Agenda
• Collaboration in a research lab • VLSI circuit research • VLSI CAD research • VLSI design process • CAD projects in multithreading • Conclusions
2 Garretón Sun Microsystems Laboratories @ 2010 Copyrights A Research Lab
• Applied research aligned with company business • Expert in n engineering fields, but knowledgeable in m (where m > n) • Communicate and collaborate with colleagues • Collaborate with universities • Contribute to open-source and standards initiatives • “Innovate, Demonstrate, Transfer”
3 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Technology Changes the World
Fortress Sun SPOT Darkstar Digital Rights
Tools for Demand Search Solaris on Honeycomb Elliptic Curve Forecasting Power PC Cryptography
UltraSPARC® V9 Electric Sun Cluster Sun Ray Developed in Sun Labs, transferred to Sun products and to the outside world 4 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Projects Clustering
System System Network System Science Hardware Software Clients
5 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Projects Clustering
System System Network System Science Hardware Software Clients
6 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Research
Research Cloud VLSI Circuit Optics/photonics Research Research VLSI CAD Datacenter Research Switch Research
Proximity CAD Tools Packaging Communication Prototype
Test Chips Switch Prototype 7 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Overview
Research Cloud VLSI Circuit Optics/photonics Research Research VLSI CAD Datacenter Research Switch Research
Proximity CAD Tools Packaging Communication Prototype
Test Chips Switch Prototype 8 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Research Interaction
Research Cloud VLSI Circuit Optics/photonics Research Research VLSI CAD Datacenter Research Switch Research
Proximity CAD Tools Packaging Communication Prototype
Test Chips
Switch * VLSI = “Very Large Scale Integration” Prototype CAD = “Computer Aided Design” 9 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Usual Interaction Model
Company A Company B Circuit CAD Design Development
10 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Usual Interaction Model
Sales
Company A Company B Circuit !#@! CAD Design Development
11 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit and CAD Research Group
• Diverse group (~23) > Hardware (19) Moscow > Software (3) > Both (1) • Education > BS, MS, PhD • Rank > 1 PE, 4 DEs and 1 Sun Fellow • 13% female (2 HW, 1SW)
12 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit Research
Research Cloud VLSI Circuit Optics/photonics Research Research VLSI CAD Datacenter Research Switch Research
Proximity CAD Tools Packaging Communication Prototype
Test Chips
Switch * VLSI = “Very Large Scale Integration” Prototype CAD = “Computer Aided Design” 13 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit Research
• Design circuits to enable novel architectures • Low-power circuits • High-speed circuits • Communication Links • Asynchronous circuits
14 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit Research: Proximity Communication (1/4) • What is a capacitor?
> Parallel metal plates form a capacitor 1 > Change in voltage on one side results in corresponding 2 change on the other side > Can only communicate changes, not real values
15 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit Research: Proximity Communication (2/4)
=
16 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit Research: Proximity Communication (3/4)
Chip2 Chip1
Transmit Receive
Receive Transmit
17 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit Research: Proximity Communication (4/4) Huge Bandwidth Gain Comparison of Scale
2 10 Tbps per mm Proximity Communication
4000 2 m
m 15 400 μm r Proxim- e
p ity I/O
s 40 Area Area Ball Bonding e
n Ball a l 4 Bonding O / I 0.4 2003 2005 2007 2009 120 Year μm
18 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit Research
Research Cloud VLSI Circuit Optics/photonics Research Research VLSI CAD Datacenter Research Switch Research
Proximity CAD Tools Packaging Communication Prototype
Test Chips
Switch * VLSI = “Very Large Scale Integration” Prototype CAD = “Computer Aided Design” 19 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI CAD Research
• Challenges > Design sizes > Acceptable performance > Hierarchical representation > Shrinking technologies • Research topics > Handling of large data set > Geometric algorithms > Visualization > Collaboration > Parallization/multiprocessing
Collaboration with Harvey Mudd College 20 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI CAD Research
• In-House > Third-party integration • CAD Tools > Transistor sizing > Analysis tools Stipple Patterns Java3D Transparency > Route and placement • Software Research > Client/server model > 2D/3D visualization > Multithreading > Area coverage Metal Cage Structure 21 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI CAD Research Platform
• Electric VLSI Design SystemTM • Benefits for HW/SW research • Java development platform • External/Open source community > www.staticfreesoft.com > OpenSparc > Google VLSI forum • Dynamic development cycle > Bug tracking system > Source control > Verification Electric Framework 22 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Benefits of Research Platform
• Prototype innovative solutions/flows > Reduce third party dependency > Avoid integration overhead > Rapid access to solutions
• Open source sandbox > Academia > Internships > Collaborators
Fleet Architecture Marina 2009
23 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit Research
Research Cloud VLSI Circuit Optics/photonics Research Research VLSI CAD Datacenter Research Switch Research
Proximity CAD Tools Packaging Communication Prototype
Test Chips
Switch * VLSI = “Very Large Scale Integration” Prototype CAD = “Computer Aided Design” 24 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Making Test Chips: Custom VLSI Chip Design Flow
Chip Building Process
CAD Testing Process
25 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Making Test Chips: Custom VLSI Chip Design Flow
1.Schematic Entry and Transistor Sizing > Logical Effort support
26 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Making Test Chips: Custom VLSI Chip Design Flow
1.Schematic Entry and Transistor Sizing 2.Simulation > Interface to CAD Tools of Our Choice > Waveform Viewer and Cross-Probing
27 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Making Test Chips: Custom VLSI Chip Design Flow
1.Schematic Entry and Transistor Sizing 2.Simulation 3.Layout > Network Consistency Checker (NCC, LVS) > Design Rules Checker (DRC) > Automatic fill generator > Placement, routing, auto stitching tool
28 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Making Test Chips: Custom VLSI Chip Design Flow
1.Schematic Entry and Transistor Sizing 2.Simulation 3.Layout 4.Fabrication
Foundry Input Foundry Output 29 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Making Test Chips: Custom VLSI Chip Design Flow
1.Schematic Entry and Transistor Sizing 2.Simulation 3.Layout 4.Fabrication 5.Testing
PxIO Testing Board 30 Garretón Sun Microsystems Laboratories @ 2010 Copyrights VLSI Circuit Research
Research Cloud VLSI Circuit Optics/photonics Research Research VLSI CAD Datacenter Research Switch Research
Proximity CAD Tools Packaging Communication Prototype
Test Chips
Switch * VLSI = “Very Large Scale Integration” Prototype CAD = “Computer Aided Design” 31 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Research Application: Switch Prototype
Research Lab VLSI Circuit Research
Datacenter VLSI CAD Switch Research Research
Proximity Communication CAD Tools Packaging Research
Test Chips Switch Prototype
32 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Research Application: Switch Prototype
Line Card 1 Line Card 3 Line Card 2 Line Card 4
Line Card Line Card Switch Line Card Line Card
RTM RTM RTM RTM FPGA FPGA FPGA FPGA
Backplane
Scalable Switch for Data Centers
Baseboard
33 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Multi-Threading in VLSI CAD
• How to split tasks? • How to merge sub results? • How to communicate between threads? > Interprocess communication • How to access share objects? > Lock contention, race conditions, deadlock • How to minimize overhead?
34 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Multi-Threading in Electric
• In schematics/layout phases > Routing tool > Analysis tools > Placement tool • Multi-threading projects > Using directly JDK threading classes: routing tool > Using built-in Electric's capabilities: DRC tool > Lab at University of Karlsruhe: placement tool • Available in GNU release: Feb 2010 > www.staticfreesoft.com
35 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Multi-Threading a Routing Tool • Routing using cost functions > Based on Dijkstra search > Two parallel techniques > Tech 1: two directions (A<->B) > Tech 2: multiple routes • Implementation > Runtime.getRuntime().availableProcessors() > Class RouteInThread extends Thread > Class Semaphore > acquireUninterruptibly() > release()
36 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Multi-Threaded Routing Results
Example: 682 segments to route
2-direction Tech. Multiple Routes Tech.
1000 1000 900 900 800 800 700 700 ) ) s s 600 600 ( (
2-CPU box 2-CPU box
e e 500 4-CPU box 500 4-CPU box m m 8-CPU box 8-CPU box i i T T 400 400 300 300 200 200 100 100
0 0 1 CPU 2 CPUs 1 CPU Max. # CPUs # CPUs # CPUs
37 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Multi-Threading a DRC Tool Jobs • Electric's core snapshots > Snapshots database > Immutable/mutable elements • Jobs Manager > Pools of jobs JobManager > Java threads • Client/server model > Serializable interface Threads > ByteArrayOutputStream > ObjectInputStream • Class MultiTaskJob
38 Garretón Sun Microsystems Laboratories @ 2010 Copyrights g n i
DRC 101 c a
p enclosure s width extension • Verify correctness > Recommended rules area h > Geometrical conditions t g n e >w(l1), f(l1, l1), g(l1,l2) l • Single-Threaded (STD) recursive algorithms
39 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Single-Threaded DRC Results
Time consuming in layouts
DRC Execution Time* (min.) # Transistors in Electric 14:24 2500000
Test A 12:00 Test B 2000000 Test C
09:36 Test A 1500000 Test B Test C 07:12
1000000 04:48
500000 02:24
0 00:00
* AMD64, 2.8GHZ, 16GB
40 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Multi-Threaded DRC: Approach 1
• Simplest approach due to STD code > Multithread at for statement for layers > Less than 1 week to implement • Best results in N2 with 16T and in Sun Fire with 4T DRCMTD Time Time in Sun in Sun Fire Fire(min.) DRCMTD Time Time in in N2 Sun (min.) Fire
02:5202:52 09:3602:52
08:24 Sun Fire X4600, SPARC Enter- 02:2402:24 Sun Fire X4600, 02:24 Sun Fire X4600, 44 CPUs, CPUs, 2.6GHz,2.6GHz, prise4 CPUs, T5220 2.6GHz, 6GB6GB 07:12 64GB,6GB N2 SunSun Fire Fire X2100, X2100, 1.4Ghz,Sun Fire 8 X2100, CPUs 01:5501:55 4CPUs,4CPUs, 2.6GHz, 2.6GHz, 01:55 4CPUs, 2.6GHz, 16GB16GB 06:00 16GB
01:2601:26 04:4801:26
03:36 00:5700:57 00:57 02:24 00:2800:28 00:28 01:12
00:0000:00 00:0000:00 11 22 44 1616 3232 6464 11 22 44 1616 3232 6464
41 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Multi-Threaded DRC: Approach 2
• Sweep-line algorithm > Reduces 2D orthogonal rectangle intersection search to 1D interval search > O(N log N) and O(R log N) complexity > http://www.cs.princeton.edu/~rs/AlgsDS07/17GeometricSearch.pdf • 2009 Internship
Overlap
Geometries Interval Tree 42 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Multi-Threaded Placement
• Project with Karlsruhe Institute of Technology (KIT), Germany • Electric as part of the course "Multicore Programming in Practice: Tools, Models, and Languages" > Leader/instructor: Dr. Victor Pankratius > 6 teams with no previous experience in Electric > Nov 2009 → Feb 2010 • Algorithms > Force-directed > Generic > Simulated-annealing 43 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Lessons Learned (1/2)
• Applications will require changes to utilize multi- threading > Changes need not be significant > More than one way to multi-thread • Porting to MTD Java is feasible > Application-specific multi-threading strategies • Software infrastructure matters! > Multi-threading using existing job mechanism > Profiling tools understand results >SunStudio Collect/Analyzer
44 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Lessons Learned (2/2)
• MTD Routing Tool > Speedup of over 4X on an 8-CPU machine • MTD DRC Tool > Results per layer >Up to 41% in Sun Fire X4600 >Up to 37% in N2 with 16 threads > Pending analysis with sweep-line approach • MTD Placement Tool > Promising results
45 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Conclusions
• Collaboration across research areas • Teamwork and communication important • Opportunities for people from different backgrounds • Often solving “real-world” problems • Easier path to productization • Research is fun! • For more information: > http://research.sun.com > Ivan Sutherland's video on leadership (88's Turing award on computing graphics)
46 Garretón Sun Microsystems Laboratories @ 2010 Copyrights Thank You!
Gilda Garretón [email protected] Technology Transfer Leadership
Technology Tools • RADAR Demand Forecasting • Honeycomb to Network Storage Tool Set to WWOPS • Elliptic Curve Cryptography libraries to Java • Electric CAE Design Tool Enterprise Server products • IC CAD tools • FreeTTS, Sphinx IV to Solaris, Accessibility • System Performance modeling and analysis • Conceptual Indexing Search to Java App Server and Java Web Server • Async technology to USIIIi • JavaTM • SPARC V9 Architecture Specification Code TM TM • Sun RayTM 1, Wide Area • Java and Java KVM Sun Ray technology • Hot Spot • Concurrent GC to Java SW • Java Speech API • Liberty architecture • Parallel Garbage Collection • Sun ClusterTM 3.0 • Java make Utility to Netbeans • Awarenex • Secure KVM to Java SW • JINITM • Jackpot JavaDoc extensions to JDK
Open Source Standards and Protocols • Elliptic Curve Cryptography • Digital Rights Management - DReaM to Open SSL, Mozilla • Java Real-time extensions, JSR1 • Jackpot metrics to Netbeans • Service Location Protocol • JFluid • Electric • Darkstar/Wonderland