Wide I/O DRAM Architecture Utilizing Proximity Communication

by Qawi Harvard Thesis Defense – October 8th, 2009 Introduction

Bandwidth and power consumption of dynamic random access memory stifles computer performance scaling  Background  Status of Proximity Communication  DRAM Market Analysis  4 Gb DRAM Architecture  Wide I/O DRAM Architecture Utilizing Proximity Communication

Qawi Harvard – Oct. 8th,2009 Thesis Defense 2 Background

 Memory Gap  Main memory does not scale with processor performance  Power  Current consumption is rising  Bandwidth increases power  Voltage scaling masks the issue  Density  Memory channel loading  Limits bandwidth  Proximity Communication  Proposed by Ivan Sutherland – US Patent #6,500,696  Promises to reduce power and increase bandwidth

Qawi Harvard – Oct. 8th,2009 Thesis Defense 3 Proximity Communication

Chip 1

Chip 2

Transmit Receive Chip 1

Chip 2

Receive Transmit

 Capacitive Coupled Proximity Communication  Top metal forms the parallel plates  Chip-to-chip communication through coupling capacitor

Ref:[1]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 4 Proximity Communication

 Benefits  Increased I/O density  Avoids on/off chip wires  Eases chip replacement at the system level  Enhances system level testability  Enables smaller chip sizes  Removes the need for ESD protection  Challenges  Mechanical misalignment  Applying power to the chips  Thermal solution

Ref:[1-5]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 5 Proximity Communication

 Parallel Plate Capacitance  A 0 aF C    8.9 m d 0 2  10 pF/mm 4000

2 1000  Chip-to-chip separation Proximity Communication  d = 1 µm Area Ball Bonding 100

 One channel I/O Density per per mm Density I/O

 50 fF 10 2 2003 2004 2005 2006 2007 2008 2009 2010  200 signals/mm [1]

Ref:[1]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 6 Proximity Communication

 Mechanical Misalignment  Six axis  Multiple sources

θx θy

Separation Tilt

θz

y x

Translation Rotation

Ref:[5]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 7 Proximity Communication

 Electronic Sensors  Chip-to-chip separation sensors (0.2 µm resolution)  Vernier scale incorporated on chip (1.0 µm resolution)

1.0  Electrical Re-Alignment 0.9 0.8  Receive array 0.7 0.6 0.5  Micro-transmit array 0.4 0.3  Electronic steering circuit 0.2 0.1

Normalized Received SignalReceived Normalized 0 0 20 40 60 80 100 120 Misalignment (µm)

Transmit Chip Inactive Transmit Pad 1 0 1 0 1 0 1 0 1 0 1 Active Transmit Pad Receiver Pad

Ref:[1-5] 1 0 1 0 1 ?? 0 1 0 1 Receive Chip Qawi Harvard – Oct. 8th,2009 Thesis Defense 8 DRAM Market Analysis

 Revisit the Memory Gap  “Performance” becomes a relative term  Dichotomy in scaling  Why Density?  Why Not Latency?

100000 100000

10000 10000 Processor IPS DRAM Density 1000 1000

100 100 Processor IPS

10 DRAM Latency 10 Relative Performance (%) Performance Relative Relative Performance (%) Performance Relative 1 1 1980 1985 1990 1995 2000 2005 2010 1980 1985 1990 1995 2000 2005 2010 Ref:[6]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 9 DRAM Market Analysis

 Moore’s Law  41% increase in transistor count per year  Selling Price  36% historic decline per year

 Putting it into Perspective 1 0 0 0 . 0 0 0 0 100,000.00

1 0 0 . 0 0 0 0 1 9 71975 9 Historically the price per bit has  1 Gb 2009 → $2.00 1977 10,000.00 1974 1980 1979 declined by 9% every quarter 1976 1 0 . 0 0 0 0 1981 1981 1984 (1974 – 2008). 1978 1983  2 Gb 2011 → $1.64 1,000.00 1 9 8 2 19801 9 8 3 1988 1985 1987 19821985 1989 1 . 0 0 0 0 1984 1989 100.00 19901993 1 9 8 6 1 9 8 7 1 9 9 5 H i s t o r i c a l 1991 1993  Density or Bust!! 1986 19881991 1994 1995 price•per•bit decline has 1 9 9 6 0 . 1 0 0 0 1992 averaged 35.5% 1990 10.00 1992 19941 9 9 7 (1978 - 2002) 1997 2 0 0 0

Price per Bit (Millicents) 1998 0 . 0 1 0 0 1996 1999 1.00 1 9 9 9 2 0 0 3

Price per Bit (Milicents) 1998 2 0 0 1 20012 0 0 4 F 2000 22003 0 0 5 F 2002 2 02005 0 6 F 0 .0.10 0 0 1 0 20022 0 0 7 F 2 0 0 8 F 2004

0 .0.01 0 0 0 1

100 1 0 , 0 0 0

Cumulative Bit Volume (10 ) 1 , 0 0 0 , 0 0 0 Ref:[7-8] 100,000,000

Qawi Harvard – Oct. 8th,2009 Thesis Defense 10 DRAM Market Analysis

 Cost

 Low cost manufacturing process Generations o 3 metal layers Features

• Increased usage of each level PM Simple RAS/CAS o Small chip size FPM Fast CAS Access • Limits I/O count Latched Output  Moore’s Law EDO Programmable Burst & Synchronous w/Clock SDR Latency Multi-Bank  41% scaling per year LVTTL Interface

o Wordline cross sectional area DDR Data Clocked on Both Clock Data Strobe Edges SSTL 2.5 Interface o Tight metal pitch DDR2 ODT Posted CAS o Contact resistance OCD SSTL 1.8 Interface DDR3 Standard Low Voltage Option Drive/ODT Calibration  Physics of Scaling Dynamic ODT Write Leveling DDR4 Faster  Latency must increase Lower Power Ref:[7-8,13]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 11 DRAM Market Analysis

700 )

 Home PC 600 mA  Plugged into a wall 500 400 ♦ DDR ● DDR4 ▲ DDR3  Mobile 300 Projections ■ DDR2  Battery life 200

100 Current Consumption ( Consumption Current  Server 0 266 333 400 533 666 800 1066 1333 1600 2133 2666 3200  Power consumption Data Rate (MHz)

 Cooling Memory Mezzanine Tray (Sun SPARC Enterprise T5240 Server Only)  Trending Up  Poor Efficiency UltraSPARC UltraSPARC  Bandwidth Driven

Ref:[14-17]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 12 DRAM Market Analysis

4000

 Interface versus Core 3500 SDR DDR DDR2 DDR3 DDR4 (1n) (2n) (4n) (8n) (16n) 3000  Interface bares the burden 2666 2666  Core cycles 2500 ■ Interface 2133 2000 ● Core 1600 1600  DRAM Pre-fetch 1500 1333

Frequency (MHz) Frequency 800 1000 1066  Doubles at each generation 667 667 400 533 333 500 267 100 200 200  Density limited by 67 67 100 133 167 167 200 133 167 133 167 167 bandwidth 0 133 167200  SSTL loading in memory channel  Increase chip count per

module Channel DIMMS or Devices per per Devices or DIMMS

400 800 1066 1333 1600 Ref:[14-17] Data Rate (MHz)

Qawi Harvard – Oct. 8th,2009 Thesis Defense 13 4 Gb DRAM Architecture

 Possible Architecture  Compared to ITRS  2012 Production Release  74 mm2  56 % Array Efficiency COLUMN  40 nm SPINE ROW

Ref:[10,12,20-24]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 14 4 Gb DRAM Architecture

 6F2 Memory Cell 6 F 2

 Feature Size = 40 nm F Gate Isolation 2  Cell Area = 0.0096 µm UNITCELL  3F Pitch per Wordline Bitline Memory Wordline  2F Pitch per Bitline Capacitor  256 kb Array Macro  Core Array  512 bitlines ≈ 43.6 µm

 512 wordlines ≈ 65.4 µm UNITCELL UNITCELL

 Periphery Circuitry UNITCELL  4 µm space allocated

Ref:[24]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 15 4 Gb DRAM Architecture

Ref:[25]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 16 4 Gb DRAM Architecture

3.5 mm  256 Mb Array 1.9 mm  32 x 32 256 kb macros 1.6 mm

32  43 .6 m  4 m   1.532 mm

256M Array 256M Array

2.3 mm 2.3 ROW

 1 Gb Array mm 2.5  Multiple implementations

COLUMN COLUMN 4.9 mm 4.9

256M Array 256M Array ROW

GLOBAL CORNER COLUMN

Qawi Harvard – Oct. 8th,2009 Thesis Defense 17 4 Gb DRAM Architecture

Chip Size = 71.4 mm2  ITRS Array Efficiency = 57.7%  74 mm2 7.0 mm  56% Array Efficiency

256M 256M 256M 256M Row Row  Wide I/O Architecture Array Array Array Array

 Moving the pads Column Column Column Column

 Centralized Row 256M 256M 256M 256M Row Row Array Array Array Array  Centralized Column

SPINE 0.4 mm 10.2 mm 10.2

256M 256M 256M 256M Row Row Array Array Array Array

Column Column Column Column

256M 256M 256M 256M Row Row Array Array Array Array Ref:[29]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 18 Wide I/O Chip Architecture

 64 Bytes per Chip Chip Size = 67.0 mm2  6.2% Chip Size Reduction Array Efficiency = 61.5% 6.7 mm  6.6% Increase in Array RO 256M Array W 256M Array Efficiency 256M 256M 256M 256M

Array Array RORow Array Array  Challenges 256M Array W 256M Array RO

W 256M Array mm 4.6  Routing from the edge 256M 256M 256M 256M

Array Array RORow Array Array  Array I/O route increase W 256M Array

o 2.3 mm → 4.6 mm RO 256M Array W 256M Array 10.0 mm 10.0 256M 256M 256M 256M

 Additional row decode Array Array RORow Array Array 256M Array W 256M Array  Create Eight Internal Banks 256M Array 256M 256M 256M 256M Array Array RORow Array Array W 256M Array

Proximity Interface

Qawi Harvard – Oct. 8th,2009 Thesis Defense 19 4 Gb DRAM Architecture

 1 mm Allocation for Proximity Chip Size = 69.68 mm2 Array Efficiency = 59.2% Channel 6.7 mm  Buffers at the Center 3.2 mm  Increase global I/O metal usage

512M Bank 512M Bank ROW  Array I/O Routing Reduced to mm 2.3 2.3 mm 512M Bank 512M Bank  Architecture NOT Efficient for ROW Proximity Communication

10.4 mm 10.4 512M Bank 512M Bank ROW

 6.7 mm versus 10.4 mm mm 7.0  Buffers required

512M Bank 512M Bank  Large metal usage ROW

Proximity Interface

Qawi Harvard – Oct. 8th,2009 Thesis Defense 20 4 Gb DRAM Architecture

 Multiple Bank Architectures

 Page Size 8-8k Pages ≈ 6.1 mm  Standard size = 8k D 512M Bank

 Energy efficiency Rows 8k ≈ 1.1 mm 1.1 ≈

 Global Row Routing 512M

Bank ≈ 8.9 mm 8.9 ≈  ~20 ns latency Rows 64k 512M Bank

512M ≈ 2.3 mm 2.3 ≈

 Global Column Routing Bank C Rows 16k

≈ 4.5 mm 4.5 ≈ 32k Rows Rows 32k  ~5 ns latency 4-8k Pages  D – Architecture A B ≈ 3.0 mm

 Page decode 1-8k Page ≈ 2-8k Pages 0.8 mm ≈ 1.5 mm

Ref:[13,16,27,30,]

Qawi Harvard – Oct. 8th,2009 Thesis Defense 21 Wide I/O Chip Architecture

 Chip Size = 68.88 mm2, Array Efficiency = 59.9%  Centralized row & column  Buffers not required  12.3 mm for proximity communication  Enables two levels of metal 12.3 mm 6.0 mm

512M Bank 512M Bank ROW

512M Bank 512M Bank 2.4 mm 2.4

COLUMN COLUMN

512M Bank 512M Bank

5.6 mm 5.6 ROW 512M Bank 512M Bank

Proximity Interface

Qawi Harvard – Oct. 8th,2009 Thesis Defense 22 Wide I/O DRAM Architecture

 Split Bank Architecture  64 bytes = 512 signals  6 mm / 256 ≈ 43 µm per signal  0.4 µm pitch < 1 % metal usage

RAS & Address Local Wordline Global Wordline

Half-Bank<7> ROW Half-Bank<7> Half-Bank<6> ROW Half-Bank<6>

Half-Bank<5> ROW Half-Bank<5>

Half-Bank<4> ROW Half-Bank<4> COLUMN COLUMN Half-Bank<3> ROW Half-Bank<3>

Half-Bank<2> ROW Half-Bank<2>

Half-Bank<0> Half-Bank<0>

Proximity Interface

Qawi Harvard – Oct. 8th,2009 Thesis Defense 23 Wide I/O DRAM Architecture

 Split Page Architecture  8k page keeps current relative  Page decode required  32 differential signals per macro  Local I/O Routing  Space limited BLSA

 Increase space? 32 LIO 256 BL  Increase page size? 256 BL 32 LIO BLSA

DQ<64:61> Region DQ<60:57> Region DQ<3:0> Region

800 µm Ref:[12,20-24,26,28] Half-Bank

Qawi Harvard – Oct. 8th,2009 Thesis Defense 24 Wide I/O DRAM Architecture

 New Column Routing  Global I/O operates at higher frequency  Protocol allows for insertion of data

Half-Bank<7> BUSY Wordline Fires

Half-Bank<6> FREE Half-Bank<6> Data Latched & Inserted on Global I/O Bus

Half-Bank<5> FREE Half-Bank<5>

Half-Bank<4> BUSY Next Wordline Fires

FREE Half-Bank<3> Half-Bank<3> Data Latched & Inserted on First Available Slot of the Global I/O Bus Half-Bank<2> FREE Half-Bank<2>

Half-Bank<1> FREE Half-Bank<1> Global I/O Bus Half-Bank<0> FREE Half-Bank<0>

Proximity Interface

Qawi Harvard – Oct. 8th,2009 Thesis Defense 25 Wide I/O DRAM Architecture

 Slice Architecture

 Ease of design

ADDRESS

CONTROL

GIO<7:0> ADDRESS o Uniformity, speed, verification CONTROL

Command Address

50 µm Power Serves 4 DQ

Buffers Buffers RoutingMetal Address RD/WR Drivers Latch (De)Serializer Refresh ROW

Half-Bank<0> (Pre)Decode toLeft Buffers

Control toRight Buffers Latches Logic ROW ADD/CMD Command Half-Bank<6> Control Rx Decode ROW Redundancy Clock Rx Fuses Half-Bank<5> Power Half-Bank<4> ROW

COLUMN x4 x4

Half-Bank<3> ROW x24

Interface

Proximity Proximity

Interface Proximity Proximity Half-Bank<2> ROW

Half-Bank<1> ROW SLICE

Half-Bank<0> ROW

SLICE SLICE

CLOCK DQ<3:0>

Proximity Interface ADDRESS

CONTROL

DATA CONTROL DATA Data SLICE Control SLICE

Qawi Harvard – Oct. 8th,2009 Thesis Defense 26 Wide I/O DRAM Architecture

 64 Bytes per Chip  Significant bandwidth increase  Power Consumption  Standard 8k page size  Split bank, split page  Cost Performance  Two metals enabled for 4 Gb  Smaller chip size, higher array efficiency

Qawi Harvard – Oct. 8th,2009 Thesis Defense 27 Wide I/O DRAM Architecture

 Power Consumption

100

30 Relative Energy Energy [%] Relative

DDR3 PxCDRAM x16 PxCDRAM x32 PxCDRAM x64

Qawi Harvard – Oct. 8th,2009 Thesis Defense 28 Wide I/O DRAM Architecture

 Bandwidth

225 PxCDRAM x64 200

175

150

125 PxCDRAM x32

100

75 PxCDRAM x16 DDR5

50 DDR4 DDR3

Module Bandwidth Bandwidth Module [GB/s] 25

0 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019

Qawi Harvard – Oct. 8th,2009 Thesis Defense 29 Future Work

 Applying Proximity Communication to New Memory Technologies  “High” density  Chalcogenide  Slice architecture  Circuit design techniques  Local I/O Routing  New column global I/O structure  Through bitline routing  Novel local I/O latch

Qawi Harvard – Oct. 8th,2009 Thesis Defense 30 Acknowledgments

 Dr. Jake Baker  Dr. Kris Campbell  Dr. Robert Drost  Dr. Sin Ming Loo  Dr. Thad Welch  Ms. Donna Welch  Family support

Questions?

Qawi Harvard – Oct. 8th,2009 Thesis Defense 31 References

[1] R. Drost, R. Hopkins, I. Sutherland, “Proximity Communication,” Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, vol. 39, issue 9, pp. 469-472, September 2003. [2] D. Salzman, T. Knight, “Capacitively Coupled Multichip Modules,” Multichip Module Conference Proceedings, pp. 487- 494, April 1994. [3] R. Drost, R. Ho, R. Hopkins, I. Sutherland, “Electronic Alignment for Proximity Communication,” IEEE International Solid State Circuits Conference, vol. 1, pp. 144-145, February 2004. [4] D. Hopkins, A. Chow, R. Bosnyak, J. Ebergen, S. Fairbanks, J. Gainsley, R. Ho, J. Lexau, F. Liu, T. Ono, J. Schauer, I. Sutherland, R. Drost, “Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication,” IEEE International Solid State Circuits Conference, pp. 368-369, pp. 609, February 2007. [5] A. Chow, D. Hopkins, R. Ho, R. Drost, “Measuring 6D Chip Alignment in Multi-Chip Packages,” Proceedings of IEEE Sensors, pp. 1307-1310, October 2007. [6] J. Hennessy, D. Patterson, Computer Architecture A Quantitative Approach, 4th ed., Morgan Kaufmann Publishers, San Francisco, 2007. ISBN 978-0-12-370490-0 [7] G. Moore, “Cramming more components onto integrated circuits,” Electronics Magazine, pp. 4-6, April 1965. [8] D. Klein, “The Future of Memory and Storage: Closing the Gap,” Microsoft WinHEC 2007, May 2007. [9] B. Pang, Caris & Company http://www.semi.org/cms/groups/public/documents/web_content/p043628.pdf, March 2008. [10] K. Kim, G. Jeong, “Memory Technologies for sub-40nm Node,” IEEE International Electron Device Meeting, pp. 27-30, December 2007. [11] J. Burnim, “On the Scaling of Electronic Charge-Storing Memory Down to the Size of Molecules,” The MITRE Corporation, November 2001. [12] Y. Park, S. Lee, J.W. Lee, J.Y. Lee, S. Han, E. Lee, S. Kim, J. Han, J. Sung, Y. Cho, J. Jun, D. Lee, K. Kim, D. Kim, S. Yang, B. Song, Y. Sung, H. Byun, W. Yang, K. Lee, S. Park, C. Hwang, T. Chung, W. Lee, “Fully Integrated 56 nm DRAM Technology for 1Gb DRAM,” IEEE Symposium on VLSI Technology, pp. 190-191, June 2007. [13] D. Rhosen, “The Evolution of DDR,” VIA Technology Forum, 2005. [14] SUN Microsystems, “SUN SPARC Enterprise T5120, T5220, T5140, T5240, Server Architecture,” http://www.sun.com/servers/coolthreads/t5140/wp.pdf, April 2008. [15] Micron Technology Inc., “TN-41-01: Calculating Memory System Power for DDR3 Introduction,” http://www.micron.com/support/part_info/powercalc.aspx, 2007. [16] Micron Technology Inc. Various Datasheets: http://www.micron.com/products/dram/

Qawi Harvard – Oct. 8th,2009 Thesis Defense 32 References

[17] Rambus, “Challenges and Solutions for Future Main Memory,” http://www.rambus.com/assets/documents/products/future_main_memory_whitepaper.pdf, May 2009. [18] P. Chiang, M. Fung, “Dual-edge extended data out memory,” US PATENT 5,950,223, September 1999. [19] R. Barth, “2007 Test and Test Equipment,” 2007 ITRS December Conference, December 2007. [20] H. Fujisawa, M. Nakamura, Y. Takai, Y. Koshikawa, T. Matano, S. Narui, N. Usuki, C. Dono, S. Miyatake, M. Morino, K. Arai, S. Kubouchi, I. Fujii, H. Yoko, T. Adachi, “1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 Compatibly Designed 1Gb SDRAM With Dual Clock Input Latch Scheme and Hybrid Multi-Oxide Output Buffer,” IEEE International Solid-State Circuits Conference, pp. 862-869, April 2005. [21] C. Yoo, K. Kyung, G. Han, K. Lim, H. Lee, J. Chai, N. Heo, G. Byun, D. Lee, H. Choi, H.C. Choi, C. Kim, S. Cho, “A 1.8 V 700 Mb/s/pin 512 DDR-II SDRAM with on-die termination and off-chip calibration,” IEEE International Solid-State Circuits Conference,” Vol. 1, pp. 312-496, February 2003. [22] C. Park, H. Chung, Y. Lee, J. Kim, J. Lee, M. Chae, D. Jung, S. Choi, S. Seo, T. Park, J. Shin, J. Cho, S. Lee, K. Kim, J. Lee, C. Kim.

S. Cho, “A 512 Mbit, 1.6 Gbps/pin DDR3 SDRAM prototype with CIO minimization and self-calibration techniques,” Symposium on VLSI Circuits, pp. 370-373, June 2005. [23] Y. Moon, Y. Cho, H. Lee, B. Jeong, S. Hyun, B. Kim, I. Jeong, S. Seo, J. Shin, S. Choi, H. Song, J. Choi, K. Kyung, Y. Jun, K. Kim, “1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture,” IEEE International Solid-State Circuits Conference, pp. 128-129,129a, February 2009. [24] F. Fishburn, B. Bush, J. Dale, D. Hwang, R. Lane, T. McDaniel, S. Southwick, R. Turi, H. Wang, L. Tran, “A 78nm 6F2 DRAM technology for multigigabit densities,” Symposium on VLSI Technology, pp. 28-29, June 2004. [25] C. Wintgens, “The 50-nm DRAM battle rages on: An overview of Micron’s technology,” http://www.eetimes.com, March 2009. [26] H. Lee, D. Kim, B. Choi, G. Cho, S. Chung, W. Kim, M. Change, Y. Kim, J. Kim, T. Kim, H. Kim, H. Lee, H. Song, S. Park, J. Kim, S. Hong, S. Park, “Fully integrated and functioned 44nm DRAM technology for 1GB DRAM,” Symposium on VLSI Technology, pp. 86-87. [27] K. Kilbuck, “Main Memory Technology Direction,” Microsoft WinHEC 2007, May 2007. [28] B. Keeth, R.J. Baker, B. Johnson, F. Lin, DRAM Circuit Design: Fundamental and High-Speed Topics, Second Edition, Wiley-IEEE, 2008. ISBN 978-0-470-18475-2 [29] International Technology Roadmap for Semiconductor, 2007 Edition, http://www.itrs.net/Links/2007ITRS/Home2007.htm, 2007. [30] Samsung Semiconductor Inc. Various Datasheets: http://www.samsung.com/global/business/semiconductor/productList.do?fmly_id=690 [31] J. Handy, “Where Silicon is Headed and Why You Need to Know,” Objective Analysis: http://www.media-tech.net/usa-09.html [32] S. Kadivar, “New Memory Technologies: Evolving Toward Greener Solutions,” Samsung Semiconductor Inc.: http://www.samsung.com/us/business/semiconductor/news/downloads/Green_Media_Event_SKadivar.pdf, March 2009.

Qawi Harvard – Oct. 8th,2009 Thesis Defense 33 References

[33] Hewlett-Packard, “Memory technology evolution: an overview of system memory technologies, technology brief, 8th edition,”: http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf, April 2009. [34] T. Jung, “Memory Technology and Solutions Roadmap,” Samsung ANALYST DAY, 2005. [35] R.J. Baker, CMOS: Circuit Design, Layout, and Simulation, Revised Second Edition, Wiley-IEEE, 2008. ISBN 978-0-470-22941-5 [36] L. Luo, J. Wilson, S. Mick, J. Xu, L. Zhang, P. Franzon, “3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver,” IEEE Journal of Solid-State Circuits, vol. 41, Issue:1, pp. 287-296, January 2006.

Qawi Harvard – Oct. 8th,2009 Thesis Defense 34