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Tightly-Coupled and Fault-Tolerant Communication in Parallel Systems

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Tightly-Coupled and Fault-Tolerant Communication in Parallel Systems Tightly-Coupled and Fault-Tolerant Communication in Parallel Systems Inauguraldissertation zur Erlangung des akademischen Grades eines Doktors der Naturwissenschaften der Universität Mannheim vorgelegt von Dipl.-Inf. David Christoph Slogsnat aus Heidelberg Mannheim, 2008 Dekan: Prof. Dr. Matthias Krause, Universität Mannheim Referent: Prof. Dr. Ulrich Brüning, Universität Heidelberg Koreferent: Prof. Dr. Reinhard Männer, Universität Heidelberg Tag der mündlichen Prüfung: 4. August 2008 Abstract The demand for processing power is increasing steadily. In the past, single processor archi- tectures clearly dominated the markets. As instruction level parallelism is limited in most applications, significant performance can only be achieved in the future by exploiting par- allelism at the higher levels of thread or process parallelism. As a consequence, modern “processors” incorporate multiple processor cores that form a single shared memory multi- processor. In such systems, high performance devices like network interface controllers are connected to processors and memory like every other input/output device over a hierarchy of periph- eral interconnects. Thus, one target must be to couple coprocessors physically closer to main memory and to the processors of a computing node. This removes the overhead of today’s peripheral interconnect structures. Such a step is the direct connection of Hyper- Transport (HT) devices to Opteron processors, which is presented in this thesis. Also, this work analyzes how communication from a device to processors can be optimized on the protocol level. As today’s computing nodes are shared memory systems, the cache coherence protocol is the central protocol for data exchange between processors and devices. Consequently, the analysis extends to classes of devices that are cache coherence protocol aware. Also, the concept of a transfer cache is proposed in this thesis, which reduces latency significantly even for non-coherent devices. The trend to the exploitation of process and thread level parallelism leads to a steady increase of system sizes. Networks that are used in such large systems are very susceptible to both hard and transient faults. Most transient fault rates are constant per bit that is stored or transmitted. With increasing system sizes and higher clock frequencies, the number of faults in time increases drastically. In the end, the error rate may rise at a level where high level error recovery becomes too costly if lower layers do not perform error correction that is transparent to the layers above. The second part of this thesis describes a direct intercon- nection network that provides a reliable transport service even without the use of end-to- end protocols. Also, a novel hardware based solution for intermediate routing is developed in this thesis, which allows an efficient, deadlock free routing around faulty links. Zusammenfassung Der Bedarf an Rechenkraft von Computer-System wächst ständig. Insbesondere auf dem Massenmarkt wurde dieser in der Vergangenheit vor allem durch Einprozessorsysteme gedeckt. Die parallele Abarbeitung von Operationen ist dabei ein wesentlicher Faktor zur Geschwindigkeitssteigerung. Da die Parallelität auf Instruktionsebene in den meisten Anwendungen sehr beschränkt ist, sind weitere Leistungssteigerungen nur möglich, wenn auch die Parallelität auf Prozess- und Thread-Ebene genutzt wird. Daher bestehen heutige Prozessor-Chips meist aus mehreren Prozessor-Kernen, die einen gemeinsamen Speicher mit einem globalen Adressraum nutzen. In solchen Systemen sind hochperformante Netzwerkschnittstellen genauso über eine Hier- archie von Verbindungsnetzwerken und Bussen mit dem System verbunden wie klassische Eingabe/Ausgabe Geräte. Um die Kommunikationsleistung zwischen Prozessor und Netzwerkschnittstelle zu verbessern, ist es erforderlich diese Verbindungsstruktur zu opti- mieren. Ein solcher Ansatz ist die Entwicklung von Geräten, die über das HyperTransport Protokoll direkt mit dem Prozessorchip verbunden werden können. Eine Umsetzung dieses Konzeptes wird in dieser Arbeit vorgestellt. Darüber hinaus werden in dieser Arbeit weitere Möglichkeiten zur Verbesserung der Kom- munikation untersucht. In heutigen Computersystemen ist das Cache-Kohärenz Protokoll das zentrale Protokoll, welches den Datenaustausch zwischen den Kernkomponenten des Rechners regelt. In dieser Arbeit werden Klassen von Geräten vorgestellt, die direkt als Kommunikationspartner an diesem Protokoll teilnehmen. Als bedeutende Neuerung wird außerdem das Konzept des Transfer Caches in dieser Arbeit entwickelt und vorgestellt, welches die Kommunikationslatenz zwischen Gerät und Prozessor bedeutend verbessert. Die bessere Ausnutzung der Parallelität auf der Ebene von Prozessen und Threads führt außerdem zu ständig komplexer werdenden Systemen. In Netzwerken, die solche Systeme verbinden, muss mit dem häufigen Auftreten von statischen und transienten Fehler gerech- net werden. In einem solchen System können die Fehlerraten dabei auf ein solches Maß steigen, dass eine ausschließlich in höheren Softwareebenen erfolgende Fehlerbehandlung sehr ineffizient wird. Mit einer Fehlerbehandlung direkt in Hardware kann dieses Problem umgangen werden. In diesem Sinne beschreibt der zweite Teil dieser Arbeit ein fehlertol- erantes Verbindungsnetzwerk, welches eine fehlertolerante Übertragung auf der Ebene 8b/ 10b kodierter serieller Links sicherstellt. Eine weitere Komponente des Protokolls ist ein neuartiger hardwarebasierter Mechanismus, der über ein "intermediate routing" eine effi- ziente und blockierungsfreie Lösung darstellt, um Pakete um fehlerhafte Komponenten herumzuleiten. I Contents CHAPTER 1 Introduction 1 1.1 The Extoll Project . .4 1.2 Physical Implementation . .6 1.3 Graphical Representations. .7 1.4 Methodologies . .9 1.5 A Theoretical Model for cHT/HT Performance . .11 CHAPTER 2 Communication in Parallel Computers 13 2.1 Caches . .13 2.2 Parallel Computing Architectures . .15 2.2.1 Communication Paradigms . .20 2.2.2 Remote Load/Store . .21 2.2.3 Put/Get . .22 2.2.4 Send-Receive . .23 2.3 Device Integration Design Space . .24 2.3.1 Process-Device Interaction . .26 2.3.2 Device Virtualization. .30 2.4 Cache Coherence for Shared Memory Systems . .32 2.4.1 Consistency Models for Shared Memory . .33 2.4.2 Cache Coherence Protocols . .35 2.4.3 Broadcast Protocols . .37 2.4.3.1 MOESI. .39 2.4.3.2 MESIF . .42 2.4.4 Directory-Based Protocols. .45 2.4.5 Serialization of Conflicting Accesses . .49 2.5 Introduction to x86 Systems . .54 2.5.1 Intel Xeon Architecture . .54 2.5.2 AMD . .57 2.6 Examples of Parallel Systems . .58 2.6.1 Sun UltraSPARC T2 . .58 2.6.2 Cray T3E . .60 2.6.3 Cray XT3 and XT4 . .61 2.6.4 IBM BlueGene/L . .63 II 2.6.5 NIs on Standardized Peripheral Interfaces . 64 CHAPTER 3 Improving Device to Processor Communication 65 3.1 HyperTransport Devices and Accelerators . 66 3.1.1 The HyperTransport Protocol . 67 3.1.2 I/O in HTX Systems . 70 3.1.3 Ordering in PIO. .71 3.1.4 Ordering PIO Write Requests . 73 3.1.5 Ordering PIO Read Requests . 76 3.1.6 Potential Incremental Solutions . 76 3.2 The Space of Analysis . .76 3.2.1 Latency-Sensitive Data . 76 3.2.2 Buffering . 78 3.2.3 Feasible Solutions . .80 3.3 Memory and Interconnect Bottlenecks . 81 3.3.1 Influence of the Cache Coherence Protocol . 85 3.3.2 Summary . 87 3.4 Devices at the Coherent Interconnect . 88 3.4.1 Devices with Coherent Caches . 89 3.5 The Performance of Coherent Transfers. 92 3.5.1 Devices with Coherent Caches . 94 3.5.1.1 Off-SOC Devices . 98 3.5.1.2 Devices with Caches in SOCs. 100 3.5.2 Devices with a Coherent Memory Controller . 101 3.6 Transfer Cache . 103 3.7 Results. ..
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