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May 1986 023-2040 Rev. A CROMEMCO, Inc. P.O. Box 7400 Copyright © 1986 . 280 Bernardo Avenue CROMEMCO, Inc. Mountain View, CA 94039 All Rights Reserved This manual was produced using a Cromemco System One computer running under the Cromemco Cromix-Plus Operating System. The text was edited with the Cromemco Cromix-Plus Screen Editor. The edited text was proofread by the Cromemco SpellMaster Program and formatted by the Cromemco Word Processing System Formatter II. Camera-ready copy was printed on a Cromemco 3355B printer.

The following are registered trademarks of Cromemco, Inc. C-Net Cromemco Cromix FontMaster SlideMaster SpellMaster System Zero System Two System Three WriteMaster The .follow~are trademarks 'of Cromemco, Inc. C-IO GalcMaster DiskMaster Maximizer System One TeleMaster System 400 TABLE OF CONTENTS

INTRODUCTION 1

SET UP AND INSTALLATION 3

System Configuration 3 Jumper Selectable Options 3 Variable Capacitor Adjustment 3 Cabling 4

THEORY OF OPERATION

S-100 Bus Operation 4 Cache Description 4 Flushing the Cache 5 MC68020 Space Mapping 5 Operation With the XMU 7 LED 7

.LIST OF· TABLES (

Table 1-1: XXU Specifications 2 Table 1-2: XXU Mapping 6

LIST OF ILLUSTRATIONS

Figure 1-1: Jumper and adjustable capacitor Locations 3 on the XXU

LIST OF APPENDICES

Appendix A: Port Assignments on the XXU 8 Appendix B: Schematic and Part List 10

Cromemco XXV Board Manual

INTRODUCTION

Cromemco's XXU processor board provides a bold leap in microcomputer processing power, exceeding previously offered microcomputer speed by a factor of three or more. By integrating a 16.7 MHz MC68020 microprocessor, a 16.7 MHz MC68881 floating-point coprocessor and a 16 KByte two-set associative data and instruction cache onto one 8-100/IEEE-696 card, the XXU offers performance heretofore unavailable in a general purpose microcomputer. Using Cromemco's 2048KZ memory boards, which feature Cromemco's exclusive double-word transfer extension to the 8-100/IEEE-696 bus, data can be moved on the bus at rates as great as 8.33 megabytes per second. This is more than double the transfer rate of previous Cromemco products.

The XXV ~lso provides a real-time clock/calendar with battery backUp and a diagnostic/boot ROM. The clock has an accuracy adjustable to within seconds per month. The combination of battery backUp and high degree of accuracy eliminates the tedium of entering time and date every time the system is booted. The diagnostic/boot ROM makes it possible to test the basic system hardware prior to booting. This enables configuration or hardware problems to be detected and signaled to the user. .

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1 Cromemco XXU Board Manual

Table 1-1: XXU SPECIFICATIONS

Processor: MC68020 - 16.7 MHz Coprocessor: MC68881 - 16.7 MHz (jumper- option present to utilize faster coprocessors when available) Cache Configurations: 256 byte internal instruction cache (on-ehip) 16 Kbyte 2-set , associative instruction/data cache (on-board)

Cache Operating Mode: Zero wait state read Two wait state write-through ("quick write")

Memor~ Address Span: 16 Megabytes I/O Address Spari: 16 Megabytes Memory and I/O .Access: Dynamic bus sizing permits access to slave device of any width -

Power-on or Reset: Diagnostic/bootstrap ROM permits direct boot to many devices

LED Fault Indicator: Encodes catastrophic hardware problems (See 68020 Cromix-Plus Manual, 68020 UNIX Manual or System 400/20 Manual) Time-of-Day Clock: Accurate to seconds per month. Backup battery life approximately 5 years (with power off)

Power Requirements: +16 Volts at 1.8 Amps Operating Environment: o to 55 Degrees C

2 Cromemco XXU Board MWlUal

SETUP AND INSTALLATION

Switch Settings

There are no switches on the XXU.

Jumper Selectable Options The XXU board has three jumper locations as shown in Figure 1-1. Jumper JP1 selects the clock source for the MC68881 coprocessor. As shipped, the MC68881 clock input is the same 16.7 MHz signal used by the MC68020. When available, a higher speed coprocessor can be used by cutting the trace between pads 2 and 3 of JP1 and installing a jumper between pads 1 and 2. Then install the auxiliary oscillator at location IC23 and replace the 16.7 MHz MC68881 with the higher speed version.

Jumpers JP2 and JP3 are for test purposes only Wld should be left open. Variable Capacitor Adjustment

C2 is a variable capacitor for adjusting the accuracy of the real-time clock. If an adjustment is necessary, locate the arrow on the adjusting screw of C2. To slow down the clock, turn the screw so that the arrow is moved closer to the maximum capacitance position (arrow pointing toward the battery). To speed up the clock, turn the arrow away from the battery. Move the screw only Ii small amount, approximately a tenth of a turn at a time. Wait at least several hours to see if additional adjustment is nec essary• r I C2 JPI

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Figure 1-1. JUMPER AND ADJUSTABLE CAPACITOR LOCATIONS ON THE XXU

3 Cromemco XXU Board Manual

Cabling

If an XMU is being used in the system, connect the 34-conductor ribbon cable provided between the XXU and the XMU. Be sure that the red cable stripe is oriented correctly to the cable stripe arrow on the board.

Battery Replacement

When XIXl3 reports that the system clock has failed or when battery voltage falls below about2.8V, it is time to replace the battery. Be certain to use an identical lithium battery as some manufacturers use a cathode material that results in an initial battery voltage exceeding the maximum voltage specification of the initial real-time clock chip.

4 Cromemco XXU Board Manual

THEORY OF OPERATION

&-100 Bus Operation The XXU is designed to be compatible with most of the existing Cromemco 8-100 boards. Bus timing constraints are actually slightly relaxed when compared to the XPU.

The XXU supports the use of an extension to the 8-100 protocol in which a 32-bit word can be transferred in one bus cycle. Two new bus signals: sMURQ* and MUAK*, form a "handshaking" scheme which allows the XXU to make 32-bit requests and transfer long words with acknowleeging slave devices. The XXU supports only vertical memory configuration. The 8-100 signal PHANTOM * (also known as MEM_DISABLE*) is grounded on the XXU, thereby disabling 64KZ memories and forcing 256KZ memories to work only in the vertical mode.

The state machine on the XXU automatically compensates for MC68020 data requests for data widths greater than the addressed slave device can transfer. If a long word transfer is attempted with a word-wide device, the state machine causes two word-wide bus cycles to take place. Four bus cycles would be performed for byte-wide slave devices. Thus a programmer need not be concerned with the width of the. slave device being addressed. The XXU periodically (about every 16 microseconds) provides an opportunity for dynamic memory cards to refresh their data. The XXU performs a pseudo-opcode fetch cycle (a read cycle with sM1 asserted) and pauses briefly thereafter, allowing these memory cards to perform a refresh cycle on their RAMs. . .

Cache Description

Because the MC68020 requires data at a much faster rate than a bus based system can provide, it is imperative to provide a zero wait-state storehouse of locally available data. In order to achieve highest performance, this local storage area (cache) must contain instructions and data that the processor is likely to reuse. The cache is filled automatically as the program executes. By tracking the data's source location in main memory, it is possible to load the cache with instructions and data from many different places in main memory. This enables cache operation to be completely transparent to the user, except for the dramatic increase in processor performance. The XXU board can load main memory long words into cache at one of two different places or sets. The logical address from the MC68020 is divided into two parts. Address bits A12-2 are used to address in parallel, two RAM arrays known as Tag RAMS. A12-2 also address two sets of cache RAMs that hold the data or instructions for the processor.

The Tag RAMs store the address bits A23-13 and Function Code FC2 of any main memory lOGation previously loaded into the cache. These RAMs are known as Tag RAMs since they contain a marker or tag for the location in main memory where this cache entry is located. Since there are two RAM arrays, two tags are output. If

5 Cromemco XXU Board Manual

either one of these tags matches the bits A23-13 and FC2 of the current processor read cycle, then the data in the set associated with that tag is the operand or instruction that the processor is requesting. It can then be provided to the processor without incurring any wait states. A match as described above is known as a cache read "hit". If neither tag matches, a read "miss" occurs and the data must be fetched from main memory and loaded into the cache. .

Writes are handled in a slightly different manner, although the matching mechanism is as described above. If a write hit occurs, the byte or bytes being written out by the processor are updated in the cache and also written out to main memory. This technique of keeping main memory current is known as "write through". Write misses are performed to main memory without involving the cache. Once the cache is updated, the XXU employs the quick-write feature. The address and data for this particular write cycle are stored in registers external to the processor. The processor is then informed that the cycle is complete. This permits the MC68020 to continue operating from its internal or external cache if the next instuctions or operands are found there. At the same time the XXU state machine completes.the write cycle on the 8-100 bus. This overlap of operation can permit the processor to complete up to ten or more instructions while the state machine finishes the write cycle to the slave device. Such overlap is especially effective when performing graphics operations, as the two-port memories frequently request many wait states.

Flushing the Cache Certain system operations, such as DMA transfers from hard disk, can change main memory without updating the cache. When this occurs, the cache must be cleared or "flushed" so that it will be reloaded from main memory. Two resetable RAM chips .. called. Valid RAMs, track which cache entries correspond to main memory and are therefore valid. Two RAMs are used so that supervisor and user information can be tracked separately. Either or both of these Valid RAMS may be cleared under software control by the operating system, or by the hardware when a DMA write is detected. In the case where it is known that a DMA device always writes to only supervisor or user space, an unnecessary flush of the space not involved can be avoided. Consult the description of the Flush Control bit in Appendix A for details.

It should be noted that during DMA the MC68020 can continue executing out of cache. The quick-write feature permits the processor to continue during DMA until a read miss occurs or a second write cycle is requested.

MC68020 Address Space Mapping

The XXU uses Function Codes FC2-0, A31 and A30 to determine whether a cycle is one of the following: - Memory - Internal I/O - External I/O - Interrupt acknowlecge

6 Cromemco XXU Board Manual

( - Coprocessor - Special

If an XMU is present and active, it also affects the space of each cycle.

Table 1-2 describes how this mapping is performed. External I/O indicates cycles that are performed on the 8-100 bus to I/O devices. Internal I/O cycles are those to the ports on the XXU; no 8-100 control signals are issued during these cycles. Internal I/O port assignments are described in Appendix A.

3 XMU Not Active XMU Active fC=Z,3,5 or 6 Super User Super User L091C.J Address A31,A30 XMU seys: 11 Ext. I/O Ext. I/O Memory I/O XMU 1

M.mcry /RCM2 Ext. I/O

10 Int. I/O Ext. I/O In1. I/O XMU 1

XMU seys: 2 Memory/ROM Memory Memory I/O XMU 1 "Access mapped to user" M.mOrY:/ROM 21Ext. I/O ( Access me pped to use r

XMUS8YS: 2 00 Memory/ROM Memory Memory I/O XMU 1

M.mor'l/RCM2 Ext. I/O

Notes: 1. "XMU n means XMU determines if access is to memory or external I/O. 2. "Memory/ROM" means: a. Al6=O ROM_ON software control bit is O. b. A16;=1 Memory 3. If FC = 0, 3, or 4, the cycle is aborted 4. When A31 & 30 = 01, a supervisor access is mapped into user space, for example, the external cache and the XMU behave as though FC2 = O.

Table 1-2: XXU MAPPING

7 Cromemco XXV Board Manual

The MC68881 Floating-point Coprocessor is assigned coprocessor ID number 1. All other coprocessor cycles are aborted with BERR*. MC68020 Breakpoint and Access Level Control cycles are also aborted.

MC68020 Interrupt Acknowledge cycles at level 1 are performed on the S-100 bus. All interrupt acknowleqse cycles above level 1 are autovectored. The XXU does not provide translation for the interrupt vectors as did the XPU and DPU. For this reason the system administrator must take care not to address any interrupting devices with fixed vectot assignments (eg. the TO-ART, and PRJ) at locations where they will generate interrupt vectors outside of the MC68020 user defined area. Only vectors above 40H should be used.

Operation with the XMU

An XMU can be connected to the XXV to provide mapping and protection for 68020 Cromix-Plus or UNIX. The XXU state machine automatically adjusts the operation of the XXV when the XMU is active. Such adjustments include waiting for XMU approval before performing quick-writes and not interrupting XMU table walks with refresh cycles.

LED

The XXV contains a red LED. The LED is used by the XXV Resident Operating System (XDOS) to signal, via a flashing code, problems encountered during its power-on diagnostic tests. Please consult the sections devoted to Xrx::s in the .aa.Q.2.D QrQmi4::.f.lus...sys.~~!LQu~, the ..Intr.~.n..tQ....D:.IDx...~m_Y..2or the .s~4.QDj2.U...l'dan.ualfor details.

8 Cromemco XXU Board Manual

Appendix A

PORT ASSIGNMENTS ON THE XXU

Internal I/O Port Characteristics

Internal I/O ports may be accessed only when the MC68020 is in supervisor mode. Any attempt by user mode operations to access internal I/O are mapped to external I/O space. .(See Table 1-2.) All internal I/O ports are byte wide, but may be referenced with longer operands as the MC68020 dynamic bus sizing will automatically read or write as many bytes as necessary.

An internal I/O port address is as follows: Aa..l MD. Ali::A1 Ai=AO 1 0 xxx port# xxx are lldon't carell bits, but should be o. The following description of the ports gives bit assignments for read and write operations.

Porti

00 Out: Control (At Power On or reset, this port is cleared all zeroes.) .

D7-D5 Unused. Always write as zeroes.

04 SEPARATE SUPEa and USER. 04=0 causes all external cache entries to be loaded into supervisor space. 04=1 separates the external cache into supervisor and user spaces. (See Cache Description.)

D3 ROM ON*. D3=0 enables the Diagnostic/bootstrap ROM. (see Table 1-2.)

D2 CACHE ON. 02=1 turns on the external cache.

D1 FREEZE CACHE. D1=1 prohibits any new entries from being loaded into the external cache. Any entries already loaded will be used if the cache is on. Flushing occurs normally.

DO DMA FLUSH CON'IROL. When DO=O both supervisor and user spaces of the external cache are flushed, whenever a DMA write occurs. If DO=1, no automatic cache flUshing occurs.

9 Cromemco XXU Board Manual

00 In: Status

D7-DO These bits read back as written above.

01 O1t; Flush

D7-D2 Unused. Alway s write as zeroes.

Dl FLUSH SUPERVISCR. Writing a 1 in this bit flushes the supervisor space of the external cache.

DO FLUSH USER. Writing a 1 in this bit flushes the user space of the external cache. 01 In: unused

02 OUt: Clear NMI latch

D7-DO Don't care. A write to this port clears the NMI latch. 02 In: unused

03 Out: LED Control

D7-D1 Unused. Always write as zeroes.

DO LED ON. DO=1 turns on the LED Diagnostic light.

20-3F In/01t: Real-Time Clock

Consult Intersil's technical literature for the ICM7170 Real-TIme Clock for the port assigments of this chip.

10 Cromemco XXU Board Manual

r APPENDIX B

SCHEMATIC AND PART LIST

Part list for XXU 020-0176 List by Part Number

R3 75 001-0006 QTY. 1 R8,9 180 001-0009 . QTY. 2 R6,7 330 001-0012 QTY. 2 R2 560 001-0015 QTY. 1 RI 1K 001-0018 QTY. 1 R120 RES 20 ,3W, WI REWOUND 001-0046 QTY. 1 R4,5 2K 001-0054 QTY. 2 R115 RES 16.9K .2SP 001-0158 QTY. 1 RI18 RES 3.9 1/2W 001-0192 QTY. 1 RI19 RES .05,3W WIREWOUND 001"'0232 QTY. 1 R101 RES 820 .2SP 001-2182 QTY. 1 Rl14 RES 3.3K .2SP 001-2233 QTY. 1 RN1,2,3,4,5,6 1K 003-0011 QTY. 6 RN7 10K 003-0024 QTY. 1 RN102 RNET CUSTOM 7P,SIP 003-0076 QTY. 1 RN101 RNET CUSTOM 10P,SIP . 003-0077 QTY. 1 C107 CAP .0 22UF,50V 004-0036 QTY. 1 CAP DECUP 004-0061 QTY. 28 C112 CAP .047,50V .2SP 004-0061 QTY. 1 C101,102,103 CAP AL 470,6.3V 004-0091 QTY. 3 C4 47uF 004-0111 QTY•. . 1 ClIO,111 CAP PYCB, 3UF ,50V 004-0130 QTY. 2 Cl14 CAP CRDC 100PF,50V 004-0137 QTY. 1 C106,113 CAP CRDC 220PF 004-0138 QTY. 2 C109 CAP .001UF,50V 004-0141 QTY. 1 C5 O.luF 004-0143 QTY. 1 C105,115 CAP CRDC .1UF,10 V 004-0143 QTY. 2 ( C108 CAP CRDC 1UF,50V 004-0147 QTY. 1 C6 47pF 004-0152 QTY. 1 C104 CAP .01UF,25V 004-0153 QTY. 1 C2 CAP 5-30 PF 004-0160 QTY. 1 C3 18pF 004-0169 QTY. 1 C1 220pF 004-0180 QTY. 1 L101 IND 22UR 007-0000 QTY. 1 L103 INn 3500 007-0024 QTY. 1 L102 IND 30UR 007-0025 QTY. 1 D102,105 DIODE IN523lB 008-0006 QTY. 2 D1 IN5225 008-0014 QTY. 1 D3 TIL209 008-0019 QTY. 1 ( ". D2 IN5711 008-0033 QTY. 1 D101 DIODE IN752,5.6 008-0056 QTY. 1 (,," D103 DIODE UES 1002 008-0071 QTY. 1 D104 DIODE IR10TQ040 008-0072 QTY. 1 Q103 '!RANS 2N 3904 " 009-0001 QTY. 1

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Q102,104 TRANS 2N3906 009-0002 QTY. 2 Q105 TRANS D45VH10 009-0035 QTY. 1 Q106 TRANS D44VH10 009-0047 QTY. 1 Q101 TRANS SCRS2600 009-0048 QTY. 1 IC60 74J.S279 010-0039 QTY. 1 IC34 74LS74 . 010-0055 QTY• 1 IC35 74J.S14 010-0061 QTY. 1 IC67 74LSl48 010-0189 QTY. 1 IC101 SG3524 010-0326 QTY. 1 IC40,53 74F74 010-0337 QTY. 2' IC41 ,74F04 010-0374 QTY. 1 IC70,71 74F251 010-0389 QTY. 2 IC61 74AS760 010-0446 QTY. 1 IC1 ,6 ,13 ,18 74F521 010-0447 QTY. 4 IC3,8,15,63 74AJ.S541 010-0448 QTY. 4 rC46 74LS592 010-0449 QTY. 1 IC68 74AJ.S873 010-0450 QTY. 1 rC44,57,64,69 74ALS646 010-0451 QTY. 4 rC9 74AS573 010-0452 QTY. 1 IC62,66 74ALS573 010-0453 QTY. 2 IC54 74F169 010-0454 QTY. 1 IC29 74AS843 010-0455 QTY. 1 IC4 74AS841 010-0456 QTY. 1 IC47 74F174 010-0477 QTY. 1 IC72 74AJ.S35 010-0478 QTY. 1 IC21 74ALS996 010-0481 QTY. 1 IC11 7170 011-0121 QTY. 1 IC27,28,30,31 7C168 ....35 011-0123 QTY. 8 . IC37,38,42,43 IC2,7 ,14 ,19 7C128_25 011-·0124 QTY. 4 IC25,26 9150_25 011-0125 QTY. 2 IC32 MC68881 011-0139 QTY. 1 IC36 MC68020 011-0127 QTY. 1 SC4 4-40X1/4 PAN HD SLOT CAD SCREW 015-0076 QTY. 1 STDF1 4-40X3/16X7/16 HX THRDED STDF 015-0083 QTY. 1 SC1,2,3 SCREW 6-32X3/8,NYL/STEEL 015-0183 QTY. 3 NTI NUTPLATE 016-0300 QTY. 1 HTSK XXU 016-0398 QTY. 1 SCKT 8 PIN 017-0000 QTY. 12 24,33,39~5~0~2~8~5 SCKT 16 PIN 017-0002 QTY. 12 24,33,39,45,50,52,58,65 SCKT 20 PIN 017-0004 QTY. 11 5,12,16,17 20,22,48,49 ,51~5 ,56 SCKT 11 24 PIN 017-0005 QTY. 1 SCKT 10 28 PIN 017-0071 QTY. 1 SCKT 23,59 COMP LEAD SCKT 017-0327 QTY. 4 J2 XMM 017-0091 QTY. 1 SCKT 32 SCKT PGA 68 017-0361 QTY. 1 SCKT 36 SCKT PGA 114 017-0426 QTY. 1 F101 FUSE 7A,125V,AXIAL 018-0039 QTY. 1 SLPD SILPAD, 3 REG 021-0185 QTY. 1

12 Cromemco XXU Board Manual

MNT1 TO 5 MNT. PAD 021-0186 QTY. 1 IC59 16.667MHZ 026-0046 QTY. 1 Y1 32.768KHZ 026-0044 QTY. 1 B1 3V 101-0006 QTY. 1

Programmable ICs

IC16 CPU_SPACE PAL16L8_15 502-0159 010-0445 QTY. 1 IC17 VALID PAL16R4 502-0160 010-0419 QTY. 1 IC56 RTC_SEL PAL16R4_15 502-0161 010-0443 QTY. 1 IC48 FLUSH PAL16L8 502-0162 010-0422 QTY. 1 IC49 IODE CODE PAL16L8 502-0163 010-0422 QTY. 1 IC51 D\TA PAL16L8_15 502-0164 010-0445 QTY. 1 IC55 DMA PAL16R4 502-0165 010-0419 QTY. 1 IC5 TAG_CTL PAL16L8_15 502-0166 010-0445 QTY. 1 IC12 HIT PAL16L8_15 502-0167 010-0445 QTY. 1 IC22 D\TA_CTL PAL16L8J5 502-0168 010-0445 QTY. 1 IC20 CYCLES PAL16L8_15 502-0169 010-0445 QTY. 1 IC10 XlJCS XlJCS 502-0170 011-0140 QTY. 1 IC24 STARTER PAL22V10A 502-0171 010-0480 QTY. 1 IC50 SIZER PAL22V10A 502-0172 010-0480 QTY. 1 IC33 XXU ST.MAC H.O 502-0214 010-0417 QTY. 1 IC39 XXU ST.MACH.1 502-0215 010-0417 QTY. 1 IC45 XXU ST.MAC H.2 502-0216 010-0417 QTY. 1 IC52 XXU ST.MACH.3 502-0217 010-0417 QTY. 1 IC58 XXU ST.MAC H.4 502-0218 010-0417 QTY. 1 IC65 XXU ST.MACH.5 502-0219 010-0417 QTY. 1

13 Cromemco XXU Board Manual Index

Battery replacement, 4

Cabling, 4 Cache description, 5

Flushing the cache, 6

Internal I/O port characteristics, 9

Jumper selectable Options, 3

LED, 8

MC68020 address space mapping, 6 •

Operation with the XMU, 8

Programmable ICs, 13

S-100 bus operation, 5 Shematic. and part list,ll Switch settings, 3

Variable capacitator adjustment, 3

XOOS, 4 XXU specificaitons, 2

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74"'7.1 f{), lUI IIlL.II,,'" (IILU ARE EHAILtl) • J"- . 'OC... I &LAyE-CLlt.... '",. I 1'••-1 ·• , ~ .VOLn ,YOl" P- .. "vaLtI ·16'10LtI HRDY -!2 •• xRay IftD HIII"- 4 m trMmI !. IUVE_Cl'" • J'- I v,... i m 'IJlQ .. v,... I J'- v,.... m 1IIlT ¥, v,.... Tm • Jot: v, .... •I m ii _xu... m IllTIIlI '11\1"- 2 ,. v,.... " 'Alt II•mAl. u .nn..... , J'- v,.... m JTllTA v, .... VT7 Ate " 'AU ... 11... 1 II!-! ,'- ""I'" ART lIlill U '''1' n PAZI INr... I ,. fDIn1[ 111.1: U 'AU ~ TRU AU ["ROIt- PAl' '2 Ai. Nltcr It ·,'- 'Al' II Ii "1M...... "URIC.... II,. 17 "., RUn 'AI' "11 PJOOITDM US..... II " no tmltT 1h .. CI..... II IIllJJlI 7t .tWaa- .1 no 71 'Nil CHD MUY I. , ,IVHC HIt,. II...." • AIl'~ ~ ~71 , ..... ,RIY 2 1'- DD..... un 'R'V 11 HIT...... on JIlT PHOL .... ,4L1•• 14 'HOl...... ""HZ I P.,y~... •• '"1 fRG[1 15 Run.. PHLII,. I ' ..... • .. m9lI[" Il1rl ·I 'Il ~i • lell p~"... .. JI • JIl 8KTlo-- 1 'Il Ncr' UXTtt-o I Jk AD...... • lk PHlI.. l' 'IVHC cas .... II ,. •• 'HLDlit "YH<: n , ...... g • ru 'DR "H' ~ ItfU '11iN 7. '"IN .1 l' 'AI ••• AS '" II PAl .D...... , #114 Al • Jk ••• •• I. 'AI ... .. 8D...... I 'AUI AJ "' .. Ptlll , • ••13 AI' "' 11 '1'7 'AI' All A7 "H' If 'AI ~ ••• .. At "• IS "12 D" •• DOl AU ••• .. 110' AU " 'AI" ." 'AI' .. AI'. AU .". 'All II 101 I Jk ,• , D" D04 IOl .. 1O,Il I .. II' D., It '01 .. »OS .oa ~~' Ik • D" D.I ,. "01 .. 10' .07 ... • 'k II. 'k • III 114 '1 114 J. II. • II ·1.5 ••• ... • I" 117 ••o. faa nil. 'Il • II' .16 ••• ... • , '4 'II ,II. • I.' .. .. 'Kl III .I! SOUl SOUT .11 9. I" JIl • , • SINP •• .. " IIHUI .,. • I.'" IIM1A D•• • 1"[ftA' .. InUR IQlI " ILl&<- Jl' • , ~ INtrlll tt lR..OR...... • '. .. aWlT. om JK. • ... 2"HZ It 'OC...... I , IC3, .. CLOCK m OH' ~ GHI IiiND .l!.\. "., J>

-I ••• i £ - I I~~.14LBI4 E 5 0 " u. 11 .cas 14L814 • • • lJ2~3~------1 RTC_RD- 24 RD7178 YDD 13 - fY t CDHTRDL RTC-UR~ I UR vSS 14 • ILL__~1~87p~f--r : CS YBACKUP il ~ ~ 2 A4ALE 8 OSCIN 918 J 1~02 C3 ADORESS 0':. DSCDUT ~ ~ vI A<4'.) II INTSRC ~JL 32.'••KH, DATA TRf C'I-.-C2 0<31"') --.ell ~ 1 I 2 ...~ :> S108 , . r

~ ADDRESS Ai 19 9 A9 D24 Al Qo 11 DATA - A2 8 Al 12 D2S QI A3 7 A2 13 D26 Q2 A4 6 A3 15 D27 Q3 AS SM 16 D2e Q4 A6 4 A5 17 D29 Q5 A7 3 A6 Ie D30 A7 Q6 AS 25 19 D31 AS Q7 A9 24 , A9 Allil 21 20 ROM_CE- AU CE All 23 All AI2 2 22 A12 DE A13 26 AI3 A14 27 AI4 A15 I AI5 ICle

CONTROL .. ,-:;~ ...... - ~ ',,~ "1/,,;. =:l ....e - ~ 7'4ALUS 3 RESET... ,R4_1 e " t IC7! I, e .. I• J • .. I'.. • Ik ~~~;45.;- liS ~1 IU' Ie.., le11 IC7t :;rcs =:h

~ I i ~ -I ••• lil i 8 i CONfROl 2 2 - ~ L i "' ...... -31."" AIIDltta. _ ,(;. It reo S''''UI _ tCI n .et fe, n .ca - ' ••un... C KUT I_I C ClOCK Ao- ~. ., I "C~ A\l£C'" H ... • IK 1 AVIC INI... ~: ., ,pu II .,~ .. ., ••:: I I I: AI I'Ll III H ,.... HI . I• • • I'll lfiACk !!L- ...... ~ IPENt aATIlI "~ • 10 ~ aU_I vt4... • ..~ NltI"'-1.I:H I~ oco S : Q 7 ,• ECI - II , Ik. 7 air"" If-I ICU H' c.,s ...... HHI~ ~ ..... FI • H> In• f10 tUI IU. "" .., DIACKI ...CIC.... IIACK.... ISACKa fi-, lUll t HALT.... r.< " . HALT I ~ AH' .n.... 'J,> H> ...... H. ~ 741\116t ~ ' ... I r,c_'lflIc~ . I I 'IACKI • rpC_..AeIC1.... •• ISACKI • IC61 .. • II II RU::'''' le6. AUX...DiC II ~ ~~ ..·.T"'"" ...... , HC vee •• ..... FI 11KHZ , UE "ACKI'" I 11'1 .-,. I ,,.C-CU 16":"00.' • AUIC..cUC •. CI ClOC: D.RCI(...... Al IC2:1 JPI ". :: .1 hi .1 A! JI 03 :: It •• I AI .,- ea • "c..eo... '--- IC3I

..~ r r ( r

i'.LSStt: 6VAUU...... -- I ji~ ~ 'to a"HZ II ~;r' ~, PIiLUll_I' URU".... 13II mt'RtetC HI'N-CUC I ;;--- ReR • LDN-CLt( I: la oa 11 83IA_CUt COHfIllOL :: ml' (~:~::~Mt>1 ~~~~o~[ ~ UlOt:: :~::~~: CYCLU :s 14 10e.I lelA_CUe • r< )(R~ ":: :~: IS IS IDD~ 11 105 14 12...... UKHZ-I ~•• ~., 106 U 11..6.... e J' I' 02 12: 11_'.... ""HZ .,: U "I •,.e...... g-CLR.. JArA---.ci• le4. leu RrtHJlQ

QR 14 amiZ 01 13 .."~ QC~ ~l~; QD If ~ x...... s

lUI

leS4

D­ OC-Cft. I:::::>-' ... ~ IlHAtH ~ slee OHrltOL

rALlUCLU :~~ :r;;-- l' en... MAS I :) II: 01 I' JtOft_IPAt'(.... ree 4 II 101 17 ere--- :::~~_9PAC[.. ::: :~::: ;;~I~ :~: ~ .u.,u~ ot....ct xttU..ACTlYE... ':: I III M"£"_lo-.- • It 106 13 fea"'" MAOk , It 02 II ru-p- III• aHTROL MAst II III II

'--­ II"'A_~'--' CYCUI leu •• 10.JOR'8 14ALU, ! Anus ,.. a ,..-..- - "lOC_STAI ,nT PALI6LI_HI.,1.!i?'·I=l1111IC:l'e I l~lJl - AllAI' I!! II •• :.; AII' 3 II 01 U rCI AU .. 13 101 11 AY[Qoo. AtS :5 14 Joe.6 INTA'" A14 ":: :::., NOIl:"AL_IlPACt"'" :~3 : 11 :~; I e 10':: A2 t· .0' 12 rPc-e.... I FCI II :~. oe: Cf'U_'iP"ilCE'ic, , l'If,,"P .. Uk a f-r-- . .. , ,", 11 114 HOL...... IHIT'" :I 1.1 ... I ~ , ~ RH' . ~ ~3': It ": • .•... _.._. _.- ..... ~.- 10.1 ~ 1341 10~ i'i HR ncul ----ii" 'Cli ft;--- ICCc"),HftU .).... HA(.... 1t"1161 I 'nHZ'" ,;: 6t F- , r{5, ,e DUCK 1~ 13RS." H CL • 1.~1 ICII ..!!!!!!. pill! II r====- ICi7 In .1 .--1i 11 '"HZ II n _r .1 11 '6~" ISACK..... 8""l IC. II : '1 CP CDII 21 ~p :~~- ::. pU.· i~ .u. fil~ .-un t,t~ CA, lit I: j c CR' •• 3 CVCLn..- H:~DA : II CR' •• • i .. ! - y.!.. ,," Jr · CR. cAl t:t A' II'" i ~:: I~:: 01~t; .~:: Q7:~ .'I:~:..:* '''IVAlU[ PRIY I De: CR' ... CA'1 I A' 81 ft- PAICONTROI. PRaY 15 D3 HR' CAl • "7 0' IS Ie! CR' I A7 Ii n [)(PECTJit CAl t ", 1Ii"'fj--- 'AIV"LUE ncu,. -z.... It O. Ii CAS 3 A6 as 14' IC 1 CR' 3 AI 0:) 14 CYCLla CAS :I AI AS ti--- '''1CONTROL LON6"- 13 OS CA" • AS U 11 IC. CA" .. AS a .. n III"'" .....-:-. , CR' :: :: &I HIIH-CLI< -- , CAl t A4 83.J S1"-DH_1U1 CAl I ".. ClI II PSYNC HOL...... C" I 1.3 at 'I HIIH_O£ Sf"JlCJl"'t-~ :7 CAl I A3 ae.1 '"..ACTlYE'" C•• I Re 81.1 LoN-CLIl: CAe I:: :~ II PlIIN C"I 7 Ae 01.. HA' CAl ~ .:~ '1 Al CI. t LDN..Gr ~:~ ::~ CI.' ,u..... CAl QI • CR' pill! ••• IC. II am- ...... ~ :E~ I; : NA...... C illilll ,illilll p!!!!1 HAOle 3 II' 5 I ~: ~: ·s I lent... e DI y"::" n '"HZ ---ii TJ 1KHZ II -·suer..... I DI 11$1 II cP -~- ~~' pi C, KRIY n D3 HR' r=-f,- r aVTl:J,lDR'" I"·" .. ~nl Uh f---- r" "UAK... 13 IS CRt t2 At CRt U "t I CAt 2! At 5 .1 D6 HA> '1_1"0_10- 'HURO'" ~ ~:: I~ 87:~ ~:: ~:: e: AI Of:~ nH..ACTl \1(_ :1 "' H" I: A' Ol:: ION_cr... '"EIIIt CAl I A1 86 UI HR' CAl I A1 eI' IS U..[H'.V CAl e A1 1t6., .u.... "I&i- ~a CAS .21 It' G5 •• HR< CA1 ., A' CIS J4 lI..JATA CAD ,AIG:I ...... Ase -- CAoI .. All a .. 13 HR> CAt .. AS Ot IJ HOLl..H... CA4 .. .. U .. , ..rSH_IUiiI I CIl3 S A4 01 II ~ C", ,:::; .. HR. CAl _ s:~::~ SMT." - 2 ~JII.CLK " CAl ,"3 02. ~ en... CAe • AI 01 .1 HAl'" ~-!1Il1 1 13"'-1 1 , - 3 U! 101 21 0. • .. era... HR~ CAl 7 AI 'Ill. - CAl '1 AI 01' ~·~Al 121"_1 alHTA LONG... .. 13 IDe jf-- Hili U' .:~ ~ CA. I A' CA' • AI CAl 01 -. CT..... s·" 10) 21 HA • - JHTA"- ,.5 10".t MA•, ~ ...... -m- ~ ::: - CACN[_ON '1.1 105.. HA ~.. DOHi~ 11 10' 11 tlA: 7..!!!!i CYCL[SI-2"'- t·8 107 II ' ~ IVI£-UOR.... II It 10. tr- ::m - - AS'" It'" 10' rr- .Mln. :a >- .~ II ::~ .--lR I·'·l C' t"A~" iii'l'ii'i) 0 • CActl'~ HU- ~ f ~ i

~ ~ lPil.1JtP ~ I 11K • I " IiE . . • RH' .11"

I ~ ~ 'I COHTRDt § - LDe.en _ ~nlJ - - LOC.STAT

SfMUS " i sue i ft .. ...-..." r r ~~- i /,--"--

• '1t9 s It I 'R. t •P.!!:.!!!!:I' I CIC G ' 16"HZ.... CLA I. tIC II CL~ a e r llf ~I lUI ~CUI :~ ., RlC..ah-o- 13 It$3 ; u '0' JI RTC.Jtfl.... ItTC-llL.... 4 U 10' o. .1 AS' '-" S ~: I' AII' Ron_o""", , n 0' •• MAil t D 'R :I FRZ_UCH[ "., 0' 14 )(A18 Q ,. ICD"' _CACH[.... • 11 0' .0. ::=,~~:~~i::- J CIC II 6 12 It Q ' MAS'" , .1 ::

I !!!:!!!:! AU'" ~ Je"!I-AClIyt... : II .9 ".UJlI'" "... rLU&H.Jr. 3 I' 01.1 IlMAmI_IU'... IH..JlUU", ." 0" .:: :::.1 ."AU•..u..... 0" s 1:1 103" I"A.JL'"_IUP ~' c..... 'Ii 104 IS ,""'-,"LlK_US ::1 •sup.. ~74 "'2 III c> ,U'I' 1 11 '01 14 FUH_ U4e,"ltgS ·rUH-CJL • II 101 U rUH .so i.o- t It 02 Ie ADSI .....u LU_CLK :J etc D' • SOUT .. "I >. :~ ~~::~~[ DU' ·u :: ~ . 'aU DAJA

L ~L~ ~ II CLI( r llf CDS .... ~ 11 101 'HOLD'" InLR[SCT'" .. Ie 102 *- [RROR- :I 13 QI ~ rHLDA ..- ,14 Q2 - RHC... ~ • lH-RUn... 1 IS Q:t [)C,eer_AI ltUK_IUiI ::; I~~ 71 61'H-OH_IUS Ie STH_ACl'Ivt... 18 104 DHA L----;c!5:1

- COtfTROL C) 6l8. -_ LoC_tTL ILD...£NTA,-V----.;1 rC2...P CACHJ_tTArul 'CU!:I3I) III 2°1!13) SU'I_.... Y03 "DDU" CACHt-COHTJI At ~e CI\CH£-ClL .01 ""lUS ••• C~ leiS

VALID I II '1-. I I' I' CONtROL ! ~I

.f. _

71:"1_35 7CIU~3S IUIIUJ,I["'11I II'II'''_U[... 1I1ur . u..ciE.... t lI'ur 81..£[.... t n ..ATCHI .....' ~A.IIO ~ ~A.lI0i iCi !U!:.!!l Fce...... ~ ~ 1CI28...2$ IC4'] le31 10? 171lUel AU U6IJ.1E... 21 ut 106. TlAI' ~!A~'~'===j :: R lOS:: ~I::~ ~ Atl 104 U 1114" tlAtl:HIL... Dt 1C ••'_as 7el68_3' "CUll:) 102 It TlAn! 1"'(' I 3) IAl...... Nt.... A 102 UTtAI4 1\(2•• 13) IIJE' ~ I:J-Cc.... t n ::~ ~n I L-r-- t TlAt3 L....-.J I ~A.l.IO ..I.!£lW D(118) I A. Ie, ~ i 1p.4Iur liE! leu

1CI68-3' ?e168_3S IIATA..ut... IIJAr IlAT.~Nt..... llgr 02_1:[.... t tt . DI_U'" , tr

RU3IU) '(714) "AlCH...... I ~.·AA.... IlOa I ~ leal Ieee 7CI28-2::1. TlAI!:If . 3I t 7 -lCI TAlil_N['" ,. 107 .6 fiAt' AU 6ND.&ND.fCe...JI.&ND.&ND,A(23 IU t8 ~ :~:.s flAI' ::: • 74(52. t8 at 104 14 1IA1" nu:TR ' IIATCH...... I 1CI48_3$ i'C UIl_3::1 103 13 llA" "A<21'13) RD:IfOT-;P DllfA..lIt... Ittnt . DATA_W[- U lur AU2'.!) A ::~ ~~ ~:::: AC2."3) : ~R ~er 108 t 18AI3 lell ~ )(3.8) I .. L..-.- ~ len IC37 It!i' ..... 8'rATUa

...-.-.. AIlIIR[SS (

74AL.S541 1 L.n..EHTRV'" 6T ~ ~

rC2..? 2 18 Tl rC2 TAG1 ~ ( Ai '1'1 C A23 3 17 T1A23 "-' A2 '1'2 A22 4 16 T1A22 A3 '1'3 A21 5 15 T1A21 A4 Y4 A2El 6 14 TIA2El AS '1'5 A19 7 13 TlA19 A6 '1'6 A18 8 12 TlA18 A7 '1'7 A17 9 11 TlA17 AS '1'8 - IC3 74AL.S541 ~ lIT ~ ~ A16 2 18 TlA16 Al '1'1 A15 3 17 TlA15 A2 '1'2 A14 4 16 TlA14 A3 '1'3 A13 5 15 TlA13 A4 '1'4 6 14 T9F'C2 AS '1'5 A23 7 13 TElA?3 A6 . '1'6 A22 8 12 T0A22 A7 '1'7 (, A21 9 11 TElA21 AS '1'8 IC8 74AL.S541 ~ 6T L-.!1 Ga A2El 2 18 10A2El A1 '1'1 A19 3 17 TElA19 A2 '1'2 AIS 4 16 TElA1S A3 '1'3 A17 5 15 TElA17 A4 '1'4 A16 6 14 T0A16 AS '1'5 IUS 7 13 T0AIS A6 '1'6 A14 S 12 T0A14 A7 '1'7 ADDRE:SS A13 9 1.1' T0A13 TAGe ~ c::: AS '1'8 ...... ICIS ...J o 0:: I­ % 74AS7GEl o U 13 ? DSACK1- ...J 011l ICol 0::= 1-1- ?4AS76El %<1: 01- 15 5 DSACKa- Ul1ll1l ...J ...J I 111l 11l 0 11l 0 'w W w = 0:: IC61 = 0:: :1::1:0::1-1- l- I- UUl:l

PAL.16L.8_15 SIZl 1 I 1 SIze 2 19 D3_CE- 12 01 Al 3 18 D2_CE- 13 101 Ae 4 17 Dl_CE- 14 102 L.D-EHTRY ~ 16 DEl_CE- - 15 103 L.D-DATA 6 15 DATAJlE- 16 104 H1T- 7 14 DATA-Al1 17 105 l-e-HIT 8 13 RJJ- IS 106 SET1_El- 9 19 02 r.!i! ASl 11 118. DATA-CTL. IC22

PAL.loLe_1S Y03 1 11 V02. .2 19 TA61_~E";" 12· 01 1101 . 3 18 ·TAGElJlE- 13 101 voe 4 17 SUPVJlE- 14 102 A2 5 16 USRVJJE- IS 103 L.D-EHTRY 6 15 SET1_a- 16 104 F'C2..? 7 14 AS- 17 105 HOL.DJlD- 8 13 XAS- 18 106 XAS_OF'F' 9 12. l.D-ENTRY- 19 02 ~ 110 TAG-CTl. ICS l_e-RAHDOI'l

lElI ?41.S74 PR ---.l! D Q.-2 HIT- 11 8 CK Q CL.R 13 IC34 68RESET- CACHE_STATUS § ADDRESS ST'ATUS ~ CONTROL. CACHE_CONTROL r> ~, r r~

74AlS646 D~LG- 21 G DATA_DIR 3 DIR HIGH_ClK 1 23 D3BA_ClK CAD CDA 22 D3BA_S ~ SAB SDA DATA D(31124) DO <::> ---' A B IC69

74~41 74AlS646 DI_TO_DO- D2_G'" 21 1 G GT DATA_DIR 3 ill G2 DIR HIGH_ClK 1 23 D2BA_CU< ~ A' V~ CAB CBA 22 D2BA_S L- ~ SAB SBA IC63 D(23116) DI A B <::> IC44

74AlS646 Dl_G'" 21 G DATA_DIR 3 DIR HIGH_ClK 1 23 D1BA_CLK CAB CDA 22 D1BA_S ~ SAB SBA D(1518) AD IC57

74ALS646 D0_G- 21 G DATA-DIR 3 DIR , HIGH_ClK 1 23 DODA_ClK CAB CBA ~ SAB SBA n D<7I1:)) A D IC64 - CONTROL 74ALS573 CONTROL HOLD'" 11 - G D ADSB~HIGH 1 OE ADDRESS A<23'16) PA(23'16) PA _ C> D Q 1'C6"6 -

I 74ALS873Hl I CLR HOLD--- '"i3 G ADSB-HIGH 2 OC A< 15'U:D PA<15'12) D Q IC68

74ALS873H2 C1:R HOLD'" 1-#14 G ADSB_LO~ II OC A

74~3 HOLD'" 11 G ADSB_LO~ 1 OC A(712) PA(712) D Q - IC62 ,~. "~' /~ ~------_...-----:" "- -

74AS841 CONTROL HOLD- 13 0 G r i:iC ADDRESS A23 2 23 XA23 ID lQ A22 3 22 XA22 2D 2Q A21 4 el XA21 3D 3Q A20 5 29 XA20 4D 4Q A19 6 19 XA19 3D 5Q Ale ' 7 18 XA18 6D 6Q A17 8 17 XA17 7D 7Q A16 9 16 XA16 8D 8Q A15 10 15 XA15 9D 9Q A14 11 14 XA14 leD 10Q IC4

74AS373 HOLD'" ,11 G ,~ OC A13 2 19 XAI3 ID lQ A12 3 18 XA12 2D 2Q STATUS ree p 4 17 xrC2 3D 3Q rCl 5 16 xrci 4D 4Q rC0 6 15 xrC0 5D 3Q .z. 6D 6Q ~ R_IJ'" 8 13 XR_IJ.... XMU~ 7D 7Q -! eD 8Q ,.!.? - IC9 ,.- .. !Rf

XMU 1 2 GNDI

CONTROL XAI5 3 NCI 8MHZ 4 At5 XA14 5 8MHZ 6 At4 t XA13 7 NC2 8 At3 XA12 9 GND2 XMEM_IO~ 10 AI2 STATUS 11 MEM_IO~ XAS~ 12 NC3 13 AS C XA2t 14 GND3 XMU-ACTIYE~ t5 "'x""'M"'O~A~c-f-YA21 XA20 16 A20 XAI9 17 At9 XAI8 18 Ate XA17 .t9 At7 XA16 20 AI6 XA23 21 A23 XR_~~ ~22 GND4R_~~ rXA22 24 A22 ,. ~ NC4 RH6 ~NC526 GND5 4 5 ~ NC6 &t &t xrci 29 rCt :> z ... U xrC2 30 rC2 I-

J2