Using LVDS for Actel's Axcelerator and RTAX-S/SL Devices
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Application Note AC288 Using LVDS for Actel's Axcelerator® and RTAX-S/SL Devices Introduction This application note describes the Low Voltage Differential Standard (LVDS) I/O capabilities of Actel's Axcelerator and RTAX-S/SL device families. The application note begins by describing the LVDS signaling standard, then discusses detailed timing and board layout requirements, and finally provides a description of LVDS features unique to Axcelerator and RTAX-S/SL. Overview Low Voltage Differential Standard (LVDS) is an I/O specification originally proposed by National Semiconductor Corporation® and made into two standards: ANSI/TIA/EIA-644 and IEEE 1596.3. The original ANSI/TIA/EIA standard is primarily an electrical interface standard and provides requirements for an LVDS driver and receiver. The IEEE standard is more general and covers the implementation of LVDS drivers and receiver pairs for a variety of applications (Consult the "References" section on page 25). LVDS is a differential low voltage I/O standard that enables serial data transfer at very high rates with the following properties: • High speed • Low power (less than 2 mW) • High common-mode noise rejection • Simple termination (100 Ω resistor on driver/receiver pair) • Low signal swing (differential voltage from 247 mV (min.) to 454 mV (max.) •Low cost Using LVDS LVDS works by switching current from a current source through a differential line pair. The current loop is completed by placing a 100 Ω termination resistor across the differential line pair. This resistor creates a voltage swing across the LVDS receiver’s inputs. Since the switching current through the differential line pair is very small (on the order of 3.5 mA), power dissipation across the termination resistor is also small (less than 2 mW, as listed above). Figure 1 shows a schematic of an LVDS driver/receiver pair. Driver Current 3.5 mA Source _ + ~350 mV + Receiver _ + _ Figure 1 • LVDS Driver/Receiver Pair October 2006 1 © 2006 Actel Corporation Using LVDS for Actel's Axcelerator® and RTAX-S/SL Devices LVDS Advantages LVDS provides many benefits. Some of the most important are high speed, low cost, and enhanced noise immunity. Table 1 compares LVDS with other I/O standards. Table 1 • LVDS Advantages Compared to Other I/O Standards GTL/ TTL/ Advantages LVDS PECL RS-422 GTL+ LVTTL Comments High Speed Yes Yes No No No LVDS is very fast. Transmission rates above 1Gbps are possible. Low Noise/EMI Yes Yes No No No RS-422,GTL/GTL+, and TTL are single- ended voltage standards that are more susceptible to environmental noise and signal integrity issues. Power Consumption Yes No No No No LVDS has very low power consumption (less than 4 mA). Most of the other standards, especially PECL, have drivers that consume significant amounts of power (greater than 15 mA/driver). Power consumption increases significantly with frequency. Rate of increase is much slower with LVDS. Simple Termination Yes No Yes No No Other standards, such as PECL, GTL, and TTL, require more involved termination schemes to reduce signal integrity issues for high-speed signals. Migration Path Yes No No Yes Yes PECL and RS-422 use specific voltage so they cannot be easily migrated to lower voltage designs. LVDS is well-suited for this since it is a differential standard. However, the DC reference level of 1.25 V must be maintained. Cost Effective Yes No Yes Yes Yes PECL and ECL drivers can be more expensive to use. Transmission Distance No Yes Yes No No Because of its high speed and low voltage, LVDS is not suitable for long distance transmission (greater than 15 meters). Transmission Options No Yes Yes Yes Yes LVDS is suited for point-to-point transmission because it is a current switching standard. Application Options Yes Yes No No Yes LVDS and TTL can be used for chip-to-chip, board-to-board, rack-to-rack, and box-to- box applications. Other standards (RS-422, PECL) are more suitable for longer distance point-to-point applications. 2 Using LVDS for Actel's Axcelerator® and RTAX-S/SL Devices LVDS Electrical Specifications Table 2 shows some of the LVDS Electrical Specifications compared with other I/O standards. Detailed LVDS specifications are discussed in the Axcelerator Family FPGAs datasheet and the ANSI/TIA/EIA-644 standard. Table 2 compares LVDS electrical characteristics against other I/O standards. Table 2 • LVDS Electrical Specifications Compared to Other I/O standards Description Parameter LVDS LVPECL GTL/GTL+ TTL Comments Differential/Output VODIFF 250-450 mV 850 mV N/A 2.4 V GTL has an open Voltage drain output Receiver Input +/- 100 mV +/- 300 mV +/- 100 mV 1.2 V Threshold Data Rate ≥ 330 Mbps1 ≥ 330 Mbps < 200 Mbps < 100 Mbps Offset Voltage VOCM 1.125-1.375V N/A 1.0V N/A 2 2 2 2 Receiver Propagation tDP 1.7ns 1.7ns 1.4ns 1.5ns Delay 2 2 2 3 Transmitter tPY 1.8ns 1.7ns 800ps 2.25ns Propagation Delay AC Power ~1.5 mW/ ~5.3 mW/ N/A N/A PECL requires signal Consumption Driver4 Driver4 DC operation power Notes: 1. In Single Data Rate (SDR) mode 2. Data for specific parameter referenced from the Axcelerator Family FPGAs datasheet using the fastest -3 speed grade 3. Best-case delay based of fastest speed grade, high slew rate, drive strength = 3 4. Worst-case driver voltage VOH - VOL, with VOL = 0 V LVDS Timing Requirements Since LVDS is intended for high-speed data transmission, understanding its timing requirements ensures the integrity and quality of both transmitted and received data. Important parameters to consider are the LVDS Eye Diagram, Data Sampling Requirements, Timing Margin, Skew between LVDS channels, and the Receiver Input Skew Margin. Each of the requirements are discussed in more detail below. Bit-Error Rate (BER) The Bit-Error Rate (BER) is an important measurement of the performance of your LVDS channels. It is measured in EQ 1: Number of Bit Errors Bit Error Rate = -------------------------------------------------------()- ()Total Number of Bits EQ 1 Common requirements for BER are either ≤ 1 x 10-12 or ≤ 1 x 10-14. These correspond to one bit error in one trillion and 100 trillion bits sent, respectively. Actel recommends using Bit-Error Rate Test (BERT) equipment for measuring the BER of your LVDS channels under worst-case operating conditions. For example, using the longest cable lengths in the system, the highest operating frequency, and the noisiest environment. BERTs may take a long time depending on the transmission rate (in bits per second) of your channels. Refer to National Semiconductor's AN-1040 application note for more information about how to test for BER. Transmission line parameters such as skew and jitter, timing, and receiver skew margin can increase your BER and need careful attention. They are discussed in the "Timing Margin" section on page 6. 3 Using LVDS for Actel's Axcelerator® and RTAX-S/SL Devices Eye Diagram LVDS is an I/O signaling standard that supports different serial data transmission protocols driven over a transmission line. Several transmission line patterns are necessary to quantify the effect of noise, attenuation, and random data on the line while data is being transmitted or received. Each of these patterns affect the BER at the receiver. In particular, the following patterns should be monitored: •VOH (Output High Voltage) and VOL (Output Low Voltage) of constant '1' and '0' bits, respectively • 0-1 and 1-0 transitions rates • 0-1-0 and 1-0-1 transitions Figure 2 illustrates all these patterns. The left side of the figure shows the ideal behavior of a signal on the line. The right side shows its actual behavior seen at the receiver. If these patterns are superimposed, they form an Eye Diagram (Figure 3 on page 5). The height of the Eye Diagram shows the maximum voltage swing seen on the transmission line. Its width represents the signaling rate. For a transmission channel to be compliant with the LVDS signaling standard, the height of its Eye Diagram must meet or exceed the LVDS Differential Voltage Specification (Table 2 on page 3). Ideal Behavior Actual Behavior Constant VOH "1" Bits 0 Constant VOL "0" Bits 0 Isolated 0-1 Transition Isolated 1-0 Trasition Isolated 0-1-0 Isolated 1-0-1 Superposition of Binary Eye Above Signals Patterns 1 Unit 1 Unit Interval Interval Figure 2 • Data Transmission Patterns 4 Using LVDS for Actel's Axcelerator® and RTAX-S/SL Devices Figure 3 • LVDS Receiver Eye Diagram Axcelerator Device (vertical scale: 100 mV/div, horizontal scale: 500 ps/div) Data Sampling Window Whenever data is transmitted using the LVDS I/O, a reference clock that is source synchronous with the LVDS data stream is either regenerated at the receiver using a Phased Locked Loop (PLL) or transmitted with the data stream. Data may be latched on either the rising edge or both the rising and falling edges of the reference clock. In the latter case, the data is said to be transmitted in Double Data Rate (DDR) mode. The relationship between the time each bit is valid (also called the bit width) and the edge of the reference clock is crucial to ensure that the receiver accurately samples each bit. This relationship is shown graphically as the Data Sampling Window in Figure 4. In the ideal situation, the reference clock should be centered in the middle of the Data Sampling Window to provide maximum setup and hold time margins at the receiver. Ideal Position of Clock Edge Data Sampling Window Figure 4 • Ideal Clock Position 5 Using LVDS for Actel's Axcelerator® and RTAX-S/SL Devices Timing Margin The Timing Margin refers to the amount of extra delay available during which the receiver can accurately sample data.