(12) United States Patent (10) Patent No.: US 8,171,377 B2 Dell Et Al
US008171377B2 (12) United States Patent (10) Patent No.: US 8,171,377 B2 Dell et al. (45) Date of Patent: May 1, 2012 (54) SYSTEM TO IMPROVE MEMORY 6.732,289 B1 5/2004 Talagala et al. ................... T14?6 RELIABILITY AND ASSOCATED METHODS 6.738,947 B1* 5/2004 Maeda ......... T14f785 6.851,086 B2 2/2005 Szymanski ........ T14f781 7,017,099 B2 3/2006 Micheloni et al. ............ 714/752 (75) Inventors: Timothy J. Dell, Colchester, VT (US); 7,047.478 B2 5/2006 Gregorietal. ... 714,773 Luis A. Lastras-Montano, Cortlandt 7,100,096 B2 8/2006 Webb, Jr. et al. ............... 714.52 Manor, NY (US); Barry M. Trager, 7,117,421 B1 10/2006 Danilak .. T14f763 Yorktown Heights, NY (US); Shmuel 7.356,753 B2 * 4/2008 Chen ............................. 714/755 Winograd, Scarsdale, NY (US) (Continued) (73) Assignee: International Business Machines FOREIGN PATENT DOCUMENTS Corporation, Armonk, NY (US) JP 100911394 4f1998 WO WO2005062478 A1 7/2005 (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 OTHER PUBLICATIONS U.S.C. 154(b) by 1127 days. IEEE (Signal Processing Systems Design and Implementation, SIPS 06), Wei Liu et al., “Low-Power High-Throughput BCH Error Cor (21) Appl. No.: 12/023,374 rection VLSI Design for Multi-Level Cell NAND Flash Memories”, pp. 303-308, Oct. 2006. (22) Filed: Jan. 31, 2008 (Continued) (65) Prior Publication Data Primary Examiner — Fritz Alphonse US 2010/0287.445A1 Nov. 11, 2010 (74) Attorney, Agent, or Firm — Ido Tuchman (51) Int. Cl. GI IC 29/00 (2006.01) (57) ABSTRACT (52) U.S.
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