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Algorithms and Hardware Designs for Decimal Multiplication

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Algorithms and Hardware Designs for Decimal Multiplication Algorithms and Hardware Designs for Decimal Multiplication by Mark A. Erle Presented to the Graduate and Research Committee of Lehigh University in Candidacy for the Degree of Doctor of Philosophy in Computer Engineering Lehigh University November 21, 2008 Approved and recommended for acceptance as a dissertation in partial ful¯llment of the requirements for the degree of Doctor of Philosophy. Date Accepted Date Dissertation Committee: Dr. Mark G. Arnold Chair Dr. Meghanad D. Wagh Member Dr. Brian D. Davison Member Dr. Michael J. Schulte External Member Dr. Eric M. Schwarz External Member Dr. William M. Pottenger External Member iii This dissertation is dedicated to Michele, Laura, Kristin, and Amy. iv Acknowledgements Along the path to completing this dissertation, I have traversed the birth of my third daughter, the passing of my mother, and the passing of my father. Fortunately, I have not been alone, for I have been traveling with God, family, and friends. I am appreciative of the support I received from IBM all along the way. There are several colleagues with whom I had the good fortune to collaborate on several papers, and to whom I am very grateful, namely Dr. Eric Schwarz, Mr. Brian Hickmann, and Dr. Liang-Kai Wang. Additionally, I am thankful for the guidance and assistance from my dissertation committee which includes Dr. Michael Schulte, Dr. Mark Arnold, Dr. Meghanad Wagh, Dr. Brian Davison, Dr. Eric Schwarz, and Dr. William Pottenger. In particular, I am indebted to Dr. Schulte for his mentorship, encouragement, and rapport. Now, ¯nding myself at the end of this path, I see two roads diverging... v Contents List of Tables ix List of Figures xi List of Acronyms xiii Abstract 1 1 Introduction 3 1.1 Motivation for Decimal Computer Arithmetic . 4 1.2 Overview of Research . 9 1.3 Signi¯cance of Research . 11 1.4 Outline of Dissertation . 13 2 Background of Decimal Computer Arithmetic 15 2.1 History of Decimal Computer Arithmetic . 16 2.1.1 Decimal Numbers . 16 2.1.2 Binary Numbers . 16 2.1.3 Fixed-point Numbers . 17 2.1.4 Scaled Fixed-point Numbers . 18 2.1.5 Floating-point Numbers . 19 2.1.6 Early Computer Arithmetic Systems . 20 2.2 Software Support of Decimal Arithmetic . 23 2.3 Processor Support of Decimal Arithmetic . 27 2.4 IEEE 754-2008 Standard . 30 2.4.1 Di®erences Between BFP and DFP . 32 2.4.2 Decimal Formats . 34 2.4.3 Rounding . 37 2.4.4 Exceptions . 38 3 Related Research 41 3.1 Decimal Encodings . 42 3.1.1 Digit Encodings . 42 vi 3.1.2 Signi¯cand Encoding . 45 3.2 Decimal Addition . 48 3.2.1 Bias, Binary Addition, and Correction . 49 3.2.2 Binary Addition and Correction . 52 3.2.3 Direct Decimal Addition . 53 3.2.4 Redundant Addition . 55 3.2.5 Subtraction via End-Around Carry Addition . 59 3.3 Decimal Multiplication . 63 3.3.1 Digit-by-Digit Multiplication . 63 3.3.2 Word-by-Digit Multiplication . 67 3.3.3 Word-by-Word Multiplication . 75 3.3.4 Decimal Floating-point Multiplication . 76 4 Iterative Multiplier Designs 78 4.1 Fixed-point Designs . 80 4.1.1 Multiplier Employing Decimal CSAs . 80 4.1.2 Multiplier Employing Signed-Digit Adders . 93 4.1.3 Summary of Iterative DFXP Designs . 111 4.2 Floating-Point Design . 112 4.2.1 Algorithm . 112 4.2.2 Features . 115 4.2.3 Implementation and Analysis . 131 4.2.4 Summary . 134 5 Parallel Multiplier Designs 135 5.1 Fixed-point Designs . 136 5.1.1 Multiplier Employing Decimal Carry-Save Adders . 136 5.1.2 Multiplier Employing Binary Carry-Save Adders . 142 5.1.3 Summary of Parallel DFXP Designs . 148 5.1.4 Combined Binary/Decimal, Fixed-point Design . 149 5.2 Floating-point Design . 158 5.2.1 Algorithm . 158 5.2.2 Features . 161 5.2.3 Implementation and Analysis . 165 5.2.4 Summary . 167 5.3 Analysis of Iterative and Parallel Designs . 168 6 Conclusion 171 6.1 Summary . 172 6.2 Future Research . 175 6.3 Closing . 179 A Glossary 197 vii B Notation 209 C Vita 215 viii List of Tables 1.1 Successive Division of Nine by Ten [1] . 6 2.1 Time Line of Early Computer Systems and Notable Events [2] . 22 2.2 Software Support of Decimal Arithmetic . 25 2.3 Contemporary Processor Support of Decimal Arithmetic . 29 2.4 Preferred Exponent of Select Decimal Operations . 34 2.5 DFP Format Parameters . 36 2.6 DFP Format Ranges . 36 2.7 Combination Field for DFP Representations . 37 2.8 Rounding Mode Descriptions . 38 3.1 Select Binary-Coded Decimal Encodings . 43 3.2 Some Binary-Coded Decimal Values . 44 3.3 Some Signed-Digit Codes . 45 3.4 Encoding a Densely Packed Decimal Declet [3] . 46 3.5 Decoding a Densely Packed Decimal Declet [3] . 47 3.6 Generation of Primary Multiples from Di®erent Multiples Sets . 72 4.1 Generation of Primary Multiples from A, 2A, 4A, and 5A . 88 4.2 Area and Delay of Iterative DFXP Multiplier (Decimal CSAs) . 92 4.3 Complexity of Digit-by-Digit Products for Ranges of Decimal Inputs . 96 4.4 Restricted-Range, Signed-Magnitude Products . 103 4.5 Restricted-Range, Signed-Digit Sums [4] (All Digits Are Decimal) . 106 4.6 Rounding Modes, Conditions, and Product Overrides for Overflow . 123 4.7 Area and Delay of Iterative Multipliers (DFXP vs. DFP) . 134 5.1 Multiplier Operand Digit Recoding Scheme [5] . 138 5.2 Area and Delay of DFXP Multipliers (Iterative vs. Parallel) . 141 5.3 Multiplier Operand Digit Recoding Schemes [6] . 145 5.4 Area and Delay of DFXP Multipliers (Iterative vs. Parallel) . 148 5.5 Binary Multiplier Operand Booth Radix-4 Recoding Scheme . 152 5.6 Area and Delay of Various Parallel DFXP Multipliers [7] . 157 5.7 Area and Delay of Parallel Multipliers (DFXP vs. DFP) . 166 5.8 Area and Delay vs. Pipeline Depth of Parallel DFP Multiplier . 166 ix 5.9 Area and Delay of Multipliers (Iterative vs. Parallel, DFXP vs. DFP) 168 B.1 Notation and Nomenclature of DFP Entity Components and Fields . 210 B.2 Notation of Operands and Data . 211 B.3 Unary Arithmetic Operations and Symbols . 212 B.4 Binary Arithmetic Operations, Symbols, and Operand Names . 212 B.5 Logic Operations and Symbols . 213 B.6 Truth Tables of Logic Operations . 213 B.7 Operator Precedence . 214 x List of Figures 2.1 Fixed-point Example . 18 2.2 Scaled Fixed-point Example . 19 2.3 Floating-point Example . 20 3.1 Generalized Flow of DFXP Addition . 48 3.2 Successive Correction Example . 50 3.3 Bias and Correction Example . 51 3.4 Carry-save Addition Example . 56 3.5 Signed-digit Addition Example . 58 3.6 Generalized Flow of DFXP Multiplication . 63 3.7 Generalized Design of DFXP Digit-by-digit Multiplication . 65 3.8 Generalized Design of DFXP Word-by-digit Multiplication . 68 3.9 Generalized Design of DFXP Word-by-word Multiplication . 76 4.1 Preliminary Iterative DFXP Multiplier Design . 82 4.2 Flowchart of Iterative DFXP Multiplier Using Decimal CSAs . 85 4.3 Iterative DFXP Multiplier Design Using Decimal CSAs . 91 4.4 Flowchart of Iterative DFXP Multiplier Using Signed-Digit Adders . 95 4.5 Example of Recoding into Signed Decimal Digits . 95 4.6 Example for Iterative DFXP Multiplier Using Signed-Digit Adders . 97 4.7 Recoder Block: (a) Single Digit, (b) n-Digit Operand . 99 4.8 Digit Multiplier Block: (a) Single Digit, (b) n-Digit . 102 4.9 Iterative DFXP Multiplier Using Signed-Digits Adders . 109 4.10 Flowchart of Iterative DFP Multiplier Using Decimal CSAs . 114 4.11 Top Portion of Iterative DFP Multiplier Design . 116 4.12 Rounding Scheme . 128 4.13 Bottom Portion of Iterative DFP Multiplier Design . 132 5.1 Flowchart of Parallel DFXP Multiplier Using Decimal CSAs [5] . 137 5.2 Partial Product Reduction Tree Employing Decimal CSAs [5] . 140 5.3 Flowchart of Parallel DFXP Multiplier Using Binary CSAs [6] . 143 5.4 Partial Product Reduction Tree: Radix-10 Recoding, Binary CSAs [6] 147 5.5 Flowchart of Parallel BFXP/DFXP Multiplier Using Binary CSAs [7] 151 5.6 Binary/Decimal Multiplier Operand Recoding Example [7] . 152 xi 5.7 Combined Bin/Dec Partial Product Reduction Tree (33 Products) [7] 154 5.8 Split Bin/Dec Partial Product Reduction Tree (33 Products) [7] . 156 5.9 Flowchart of Parallel DFP Multiplier Using Binary CSAs [8] . 159 5.10 Parallel DFP Multiplier Design [8] . 162 B.1 DFP Storage Fields . 210 xii List of Acronyms ASIC - Application-speci¯c Integrated Circuit BCD - Binary Coded Decimal BID - Binary Integer Decimal BFXP - Binary Fixed-Point BFP - Binary Floating-Point CLB - Combinatorial Logic Block CMOS - Complimentary Metal-Oxide Semiconductor CSA - Carry-Save Adder DFXP - Decimal Fixed-Point DFP - Decimal Floating-Point DPD - Densely Packed Decimal HDL - Hardware Description Language IC - Integrated Circuit LSB - Least Signi¯cant Bit LSD - Least Signi¯cant Digit LUT - Look-Up Table MSB - Most Signi¯cant Bit MSD - Most Signi¯cant Digit NaN - Not-a-Number NFET - Negative-channel Field-E®ect Transistor FET - Field-E®ect Transistor PFET - Positive-channel Field-E®ect Transistor QNaN - Quiet Not-a-Number SNaN - Signaling Not-a-Number XS3 - Excess-3 binary coded decimal xiii Abstract Although a preponderance of business data is in decimal form, virtually all floating- point arithmetic units on today's general-purpose microprocessors are based on the binary number system. Higher performance, less circuitry, and better overall error characteristics are the main reasons why binary floating-point hardware (BFP) is chosen over decimal floating-point (DFP) hardware.
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