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Parallel to Serial VID Translation on AMD Processors Using the PIC16F506

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Parallel to Serial VID Translation on AMD Processors Using the PIC16F506 APPLICATION DESCRIPTION Author: Kyle Gaede Microchip Technology Inc. The PIC16F506 is the main controller used to translate Thomas Madaelil the PVID codes and transmit the VID using the Serial Advanced Micro Devices VID Interface (SVI) to the PWM controller. Some key features of the PIC16F506 include low-cost baseline architecture, up to 8 MHz internal oscillator with 500 ns INTRODUCTION instruction cycles, wide 2V-5V operating voltage range, internal flash memory, and 14-pin package with 12 I/O. This white paper describes a method to convert tradi- Refer to the PIC12F510/16F506 Data Sheet tional parallel voltage identification (VID) codes to (DS41268) for more information. serial VID codes. The CPU outputs VID codes to adjust Figure 1 below shows the flow diagram for this transla- the output voltage from the core CPU voltage regulator. tor application. On power-up, the PIC16F506 initializes As feature set requirements cause the main CPU to internal registers, enables the bypass (which routes the evolve into larger pin count packages, traditional paral- SVI I/O around the PIC16F506), and continuously sam- lel VID (PVID) code implementations require an exces- ples CORE_TYPE. If CORE_TYPE indicates a PVID sive number of I/Os to continue to be feasible. The CPU, then the controller turns off the bypass, checks Serial VID (SVID) implementation offers a two wire the power-up default pre-PWROK metal VID code from interface to implement power supply voltage changes the CPU, and outputs the appropriate default state to without growing the I/O count. The PIC16F506 trans- the SVID PWM controller. lates PVIDs to SVIDs so that a single platform, with a SVI CPU core power supply pulse-width modulation After PWROK is asserted, the controller continuously controller, can support processors that output PVIDs checks for VID code changes. When the controller and processors that output SVIDs. Refer to AMD Volt- detects a VID change, the controller converts the PVID age Regulator and Voltage Regulator Module (VRM) to a SVID data pattern and sends the SVID data to the Specification, #40182 for more information of how to PWM controller. support a PVID CPU and a SVID CPU in the same plat- form. © 2007 Microchip Technology Inc. DS41309A-page 1 Parallel to Serial VID Translation on AMD Processors FIGURE 1: FLOW DIAGRAM FOR PVID TO SVID TRANSLATION Reset Initialize, Enable Bypass Core_Type_L = No Parallel (Low)? Yes Disable Bypass No PWROK No Core_Type_L = Yes Read Pre-PWROK Convert to Output Asserted? Parallel (Low)? Metal VID Metal Serial VID Metal Serial VID Yes Read Parallel VID VID Changed? Yes Convert to Serial Transmit Serial VID VID No APPLICATION SCHEMATIC IN-CIRCUIT SERIAL Figure 2 shows the basic connections for the PROGRAMMING™ (ICSP™) PIC16F506 to support PVID to SVID translation. This The application board can also implement ICSP to sup- schematic only shows the connections to the port reprogramming the device after board assembly. PIC16F506. Please refer to the AMD Voltage Regulator This is useful to support firmware changes during early and Voltage Regulator Module (VRM) Specification, prototype periods after board assembly. If ICSP func- #40182 and the AM2r2 Processor Motherboard Design tionality is desired, a reference schematic is provided in Guide, #41645 for more details of how to support a Figure 3 which shows the proper connections. PVID processor and a SVID processor with one platform. DS41309A-page 2 © 2007 Microchip Technology Inc. © FIGURE 2: APPLICATION SCHEMATIC FOR PIC16F506 (NOIN-CIRCUIT PROGRAMMING 2007 Microchip Technology 2007MicrochipInc. Parallel to Serial VID Translation onAMD ProcessorsParallel to Serial VID Translation SUPPORT) CPU_VID(3) CPU_VID(2) 3.3V_ALW 3 1 3 1 Q17 Q19 FDV301N FDV301N 2 2 NOPOP 10K 0 0 NOPOP 10K C1 2 2 3.3V_ALW 0.1uF 3.3V_ALW Q18 SVID_BYPASS Q20 1 1 R24 R23 R21 R22 3 3 FDV301N FDV301N GND 1 R4 R3 R5 R6 R2 U1 10K 10K 10K 10K 10K R20 10K 10K R15 10K R16 10K R17 CPU_VID0_L_PIC_3.3 13 VDD 10 CPU_VID3_L_PIC_3.3 GND GND RB0/AN0/C1IN+/ICSPDAT RC0/C2IN+ CPU_VID1_L_PIC_3.3 12 9 CPU_VID4_L_PIC_3.3 RB1/AN1/C1IN-/ICSPCLK RC1/C2IN- CPU_VID2_L_PIC_3.3 11 8 CPU_VID5_L_PIC_3.3 RB2/AN2/C1OUT RC2/CVREF CPU_PWROK_L_PIC_3.3 4 7 CPU_PSI_L_PIC_3.3 RB3/MCLR_L/VPP RC3 SVID_BYPASS R1 0 SVID_BYPASS_PIC 3 6 RB4/OSC2/CLKOUT RC4/C2OUT 15 CPU_SVC CPU_CORE_TYPE_L_PIC_3.3 2 5 RB5/OSC1/CLKIN RC5/T0CKI 15 CPU_SVD 3 3 GND 8,14 1 Q5 Q12 1 8,14 CPU_VID(0) CPU_VID(3) FDV301N PIC16F506 - SOIC FDV301N Connect to SVI Controller 14 2 2 CPU_VDDIO_SUS GND 3 GND 3 8,14 1 Q4 Q14 1 8,14 CPU_VID(1) CPU_VID(4) FDV301N GND FDV301N 2 2 R7 300 GND 3 GND 3 8,14 1 Q3 CPU_VID(1) Q15 1 8,14 CPU_VID(2) CPU_VID(5) FDV301N FDV301N 2 2 27 R8 GND 3 3 GND 14,15 1 Q2 Q16 1 CPU_PWROK 8 CPU_PSI_L FDV301N FDV301N 3 2 2 1 Q6 FDV301N GND GND 2 GND 1 3 Q1 CPU_CORE_TYPE 8,14 FDV301N 2 GND DS41309A-page 3 DS41309A-page 4 FIGURE 3: ALTERNATE APPLICATION SCHEMATIC WITH OPTIONAL IN-CIRCUIT Processors AMD on Translation VID Serial to Parallel PROGRAMMING SUPPORT CPU_VID(3) CPU_VID(2) 3 5V_ALW 3 1 1 Q27 Q25 FDV301N FDV301N 2 2 Programming Header NOPOP NOPOP 10K 0 10K C2 5V_ALW 2 2 5V_ALW 0.1uF 5V_ALW SVID_BYPASS R31 Q26 1 1 Q28 R29 R32 R30 0 3 3 J1 FDV301N FDV301N 1 CPU_PWROK_L_PIC_3.3 GND 2 3 4 CPU_VID0_L_PIC_3.3 1 U2 10K R10 R11 10K R12 R13 R14 10K R25 10K R26 10K R27 10K 10K R28 100K 100K 5 CPU_VID1_L_PIC_3.3 6 CPU_VID0_L_PIC_3.3 13 VDD 10 CPU_VID3_L_PIC_3.3 GND GND RB0/AN0/C1IN+/ICSPDAT RC0/C2IN+ CPU_VID1_L_PIC_3.3 12 9 CPU_VID4_L_PIC_3.3 RB1/AN1/C1IN-/ICSPCLK RC1/C2IN- CPU_VID2_L_PIC_3.3 11 8 CPU_VID5_L_PIC_3.3 RB2/AN2/C1OUT RC2/CVREF CPU_PWROK_L_PIC_3.3 4 7 CPU_PSI_L_PIC_3.3 RB3/MCLR_L/VPP RC3 GND SVID_BYPASS R9 0 SVID_BYPASS_PIC 3 6 RB4/OSC2/CLKOUT RC4/C2OUT 15 CPU_SVC CPU_CORE_TYPE_L_PIC_3.3 2 5 RB5/OSC1/CLKIN RC5/T0CKI 15 CPU_SVD 3 3 1 Q11 GND Q21 1 CPU_VID(0) 8,14 8,14 CPU_VID(3) FDV301N PIC16F506 - SOIC FDV301N Connect to SVI Controller 14 2 2 CPU_VDDIO_SUS GND 3 GND 3 1 Q10 Q22 1 CPU_VID(1) 8,14 8,14 CPU_VID(4) FDV301N GND FDV301N 2 2 300 R18 GND 3 GND 3 1 Q9 CPU_VID(1) Q23 1 CPU_VID(2) 8,14 8,14 CPU_VID(5) FDV301N FDV301N 2 2 27 R19 GND 3 GND 3 14,15 1 Q8 Q24 1 8 CPU_PWROK CPU_PSI_L FDV301N FDV301N 3 2 1 Q13 2 FDV301N GND GND 2 GND 1 3 Q7 CPU_CORE_TYPE 8,14 FDV301N 2 GND © 2007 Microchip Technology Inc. Parallel to Serial VID Translation on AMD Processors QUICK TURN PROGRAMMING (QTP) REFERENCES – PIC16F506T-I/SL020 “AMD Voltage Regulator and Voltage Regulator A preprogrammed device (QTP) will be available from Module (VRM) Specification”, AMD Publication #40182 Microchip Technology, which implements the translator “Voltage Regulation Design Guide for Processors function developed by AMD. To obtain the programmed Supporting Six-bit VID codes”, AMD Publication device, a special part number has been created so that #31525 programming support is not needed in the final applica- “PIC12F510/PIC16F506 Data Sheet” (DS41268), tion board. The full part number for the programmed http://www.microchip.com. part is PIC16F506T-I/SL020 (tape and reel) or PIC16F506-I/SL020 (tube). CONCLUSION For questions regarding the translator implementation, or to obtain pricing information, please send e-mail query to [email protected]. © 2007 Microchip Technology Inc. DS41309A-page 5 Parallel to Serial VID Translation on AMD Processors NOTES: DS41309A-page 6 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, ensure that your application meets with your specifications. PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and MICROCHIP MAKES NO REPRESENTATIONS OR SmartShunt are registered trademarks of Microchip WARRANTIES OF ANY KIND WHETHER EXPRESS OR Technology Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are FITNESS FOR PURPOSE.
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    5 4 3 2 1 AMD Socket AM2 with AMD M690T Chipset Reference Schematic D D NOTES: Page Index Page Index ------- -------------------------------------------- ------- -------------------------------------------- 1) This schematic supports the AMD Socket AM2 CPU devices. 1 Cover Page 17 SB600 PCIe, PCI, LPC, Straps, & CPU Control 2) These are "Reference Schematics" and as such they have 2 Revision History 18 SB600 ACPI, GPIO, USB, and Audio Interfaces not been verified by an actual board build. 3 Block Diagram 19 SB SATA, IDE, SPI, and HW Management Interfaces 3) This reference schematic supports AMD M960T revision 4 Clock Structure 20 SB600 Power A12 or later. If A12 or later revision is not used, please 5 Power Configuration (1) 21 CRT Connector see your customer support representative for the 6 Power Configuration (2) 22 Broadcom Ethernet Controller necessary application notes for workarounds. 7 Reset & Voltage Sequence 23 Realtek Audio Codec C 4) This reference schematic supports SB600 revision 8 Socket AM2 HT Interface 24 LPC BIOS C A21 or later. If A21 or later revision is not used, please 9 Socket AM2 DDRII Memory Interface 25 USB Power and Connectors see your customer support representative for the 10 Socket AM2 Control & Debug 26 Power Main System, SB600 PCIe, & Other necessary application notes for workarounds. 11 Socket AM2 Power & Ground 27 Standby Power & Powergood 5) Unless otherwise specified, resistors have 5% tolerance. 12 SODIMM DDR2 28 Power for CPU Core 13 M690T HT, PCI, PCIe(R), PCIe Graphics Port 29 Power for DDR2 Memory and Interface 6) Unless otherwise specified, capacitors have 20% tolerance. 14 M690T PLL and Video Interface 30 Power M690T Core, PCIe Interface 15 M690T Power and Side Port Memory Interface 31 Unused Interfaces 16 Clock Generator IMPORTANT NOTICE: B 1.
  • IEEE 802.3Da SPMD TF Meeting May 19, 2021 Prepared by Peter Jones

    IEEE 802.3Da SPMD TF Meeting May 19, 2021 Prepared by Peter Jones

    IEEE 802.3da SPMD TF meeting May 19, 2021 Prepared by Peter Jones Presentations posted at: https://www.ieee802.org/3/da/index.html Agenda/Admin - Chad Jones All times in Pacific Time (PT) 7:01am: The Chair reviewed the agenda in https://www.ieee802.org/3/da/public/051921/8023da_agenda_051921.pdf. The Chair asked if there were any corrections or additions to the agenda. There being no corrections or additions, the agenda stands approved. The Chair asked if anyone hasn’t had a chance to review the minutes for April 21, 2021. None responded. The Chair asked if there were any change to be made to the April 21, 2021 minutes. None responded. The April 21, 2021 minutes were approved by unanimous consent. 7:09am: Call for patents was made, no one responded. 7:14am: opening agenda slides complete. The meeting moves on to presentations. Presentations/Discussion. 7:14am: LTspice Model Validation Chris DiMinico, MC Communications/PHY-SI LLC/SenTekse/Panduit Bob Voss, Panduit Paul Wachtel, Panduit 7:21am: presentation done, start of Q&A. 7:30am: Q&A done. 7:30am: Startup sequence Michael Paul, ADI 8.05am: presentation & Q&A done. 8:05am: Editors comments George Zimmerman, CME Consulting/various 8:28am: Closing remarks Next meeting: May 26, 2021 , 7:00am PT. Meeting closed – 8:31am PT Attendees (from Webex + emails) Name Employer Affiliation Attended 05/19 Alessandro Ingrassia Canova Tech Canova Tech y Anthony New Prysmian Group Prysmian Group y Bernd Horrmeyer Phoenix Contact Phoenix Contact y Bob Voss Panduit Corp. Panduit Corp. y Brian Murray Analog Devices Inc.