Parallel to Serial VID Translation on AMD Processors Using the PIC16F506

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APPLICATION DESCRIPTION Author: Kyle Gaede Microchip Technology Inc. The PIC16F506 is the main controller used to translate Thomas Madaelil the PVID codes and transmit the VID using the Serial Advanced Micro Devices VID Interface (SVI) to the PWM controller. Some key features of the PIC16F506 include low-cost baseline architecture, up to 8 MHz internal oscillator with 500 ns INTRODUCTION instruction cycles, wide 2V-5V operating voltage range, internal flash memory, and 14-pin package with 12 I/O. This white paper describes a method to convert tradi- Refer to the PIC12F510/16F506 Data Sheet tional parallel voltage identification (VID) codes to (DS41268) for more information. serial VID codes. The CPU outputs VID codes to adjust Figure 1 below shows the flow diagram for this transla- the output voltage from the core CPU voltage regulator. tor application. On power-up, the PIC16F506 initializes As feature set requirements cause the main CPU to internal registers, enables the bypass (which routes the evolve into larger pin count packages, traditional paral- SVI I/O around the PIC16F506), and continuously sam- lel VID (PVID) code implementations require an exces- ples CORE_TYPE. If CORE_TYPE indicates a PVID sive number of I/Os to continue to be feasible. The CPU, then the controller turns off the bypass, checks Serial VID (SVID) implementation offers a two wire the power-up default pre-PWROK metal VID code from interface to implement power supply voltage changes the CPU, and outputs the appropriate default state to without growing the I/O count. The PIC16F506 trans- the SVID PWM controller. lates PVIDs to SVIDs so that a single platform, with a SVI CPU core power supply pulse-width modulation After PWROK is asserted, the controller continuously controller, can support processors that output PVIDs checks for VID code changes. When the controller and processors that output SVIDs. Refer to AMD Volt- detects a VID change, the controller converts the PVID age Regulator and Voltage Regulator Module (VRM) to a SVID data pattern and sends the SVID data to the Specification, #40182 for more information of how to PWM controller. support a PVID CPU and a SVID CPU in the same platform.

FIGURE 1: FLOW DIAGRAM FOR PVID TO SVID TRANSLATION

Reset

Initialize, Enable Bypass

Core_Type_L = No Parallel (Low)?

Yes

Disable Bypass

PWROK No Core_Type_L = Yes Read Pre-PWROK Convert to Output Asserted? Parallel (Low)? Metal VID Metal Serial VID Metal Serial VID

Yes

Read Parallel VID

VID Changed? Yes Convert to Serial Transmit Serial VID VID

APPLICATION SCHEMATIC IN-CIRCUIT SERIAL Figure 2 shows the basic connections for the PROGRAMMING™ (ICSP™) PIC16F506 to support PVID to SVID translation. This The application board can also implement ICSP to sup- schematic only shows the connections to the port reprogramming the device after board assembly. PIC16F506. Please refer to the AMD Voltage Regulator This is useful to support firmware changes during early and Voltage Regulator Module (VRM) Specification, prototype periods after board assembly. If ICSP func- #40182 and the AM2r2 Processor Motherboard Design tionality is desired, a reference schematic is provided in Guide, #41645 for more details of how to support a Figure 3 which shows the proper connections. PVID processor and a SVID processor with one platform.

FIGURE 2: APPLICATION SCHEMATIC FOR PIC16F506 (NO IN-CIRCUIT PROGRAMMING SUPPORT) CPU_SVC CPU_SVD

15 15

R24 NOPOP 0

R23 10K

FDV301N FDV301N

Q20 Q19

Connect to SVI Controller

3 2 2 3

1 1

R22 NOPOP 0

10K R21

GND GND

FDV301N FDV301N

Q18 Q17

3 3 2 2 1 1 CPU_VID(3) CPU_VID(4) CPU_VID(5) CPU_PSI_L 8 8,14 8,14 8,14 CPU_VID(3) CPU_VID(2)

R20

3 2

SVID_BYPASS 10K

Q16 R17

3 2 GND 10K FDV301N 1

Q15

R16 GND 3 2 10K FDV301N 1

Q14

R15 GND 3 2 10K FDV301N 3.3V_ALW Q12 GND FDV301N CPU_PSI_L_PIC_3.3 CPU_VID3_L_PIC_3.3 CPU_VID4_L_PIC_3.3 CPU_VID5_L_PIC_3.3 10 9 8 7 6 5 U1 PIC16F506 - SOIC RC3 RC1/C2IN-

RC0/C2IN+ RC5/T0CKI

RC2/CVREF RC4/C2OUT

VDD GND

1 14

GND

C1 0.1uF GND 3.3V_ALW RB0/AN0/C1IN+/ICSPDAT RB1/AN1/C1IN-/ICSPCLK RB2/AN2/C1OUT RB3/MCLR_L/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN

4 3 2

13 12 11

300 R8

GND Q6 FDV301N

3 2

R7 27 1 CPU_VDDIO_SUS

CPU_PWROK_L_PIC_3.3 CPU_VID0_L_PIC_3.3 CPU_VID2_L_PIC_3.3 CPU_VID1_L_PIC_3.3 CPU_CORE_TYPE_L_PIC_3.3 SVID_BYPASS_PIC R6

GND Q5 FDV301N

3 2

10K R5 1

GND Q4 FDV301N

3 2

10K R4 1

GND Q3FDV301N CPU_VID(1)

3 2

10K R3 1

GND Q2 FDV301N

3 2

10K R2 1

GND Q1 FDV301N

3 2 10K 3.3V_ALW 1 R1 0 8,14 8,14 8,14 8,14 14,15 SVID_BYPASS CPU_VID(0) CPU_VID(1) CPU_VID(2) CPU_PWROK CPU_CORE_TYPE

FIGURE 3: ALTERNATE APPLICATION SCHEMATIC WITH OPTIONAL IN-CIRCUIT PROGRAMMING SUPPORT CPU_PWROK_L_PIC_3.3 CPU_VID0_L_PIC_3.3 CPU_VID1_L_PIC_3.3 GND 5V_ALW 1 2 3 4 5 6 J1 Programming Header CPU_SVC CPU_SVD

15 15

NOPOP 0 R32

R31 10K

FDV301N FDV301N

Q28 Q27

3 2 2 3 Connect to SVI Controller

1 1

NOPOP 0 R30

R29 10K

GND GND

FDV301N FDV301N

Q26 Q25

3 2 3 2 1 1 CPU_PSI_L CPU_VID(3) CPU_VID(4) CPU_VID(5) 8 8,14 8,14 8,14 CPU_VID(3) CPU_VID(2)

R28

2 3

SVID_BYPASS 10K

Q24 R27

2 3 GND 10K FDV301N

R26 Q23

GND 3 2 10K FDV301N 1

Q22

R25 GND 3 2 10K FDV301N 5V_ALW Q21 GND FDV301N CPU_PSI_L_PIC_3.3 CPU_VID3_L_PIC_3.3 CPU_VID4_L_PIC_3.3 CPU_VID5_L_PIC_3.3 10 9 8 7 6 5 U2 PIC16F506 - SOIC RC3 RC1/C2IN-

RC0/C2IN+ RC5/T0CKI

RC2/CVREF RC4/C2OUT

VDD GND

14 1

GND

C2 0.1uF GND 5V_ALW RB4/OSC2/CLKOUT RB5/OSC1/CLKIN RB0/AN0/C1IN+/ICSPDAT RB1/AN1/C1IN-/ICSPCLK RB2/AN2/C1OUT RB3/MCLR_L/VPP CPU_VID(1)

4 3 2

13 12 11

300 R19

GND Q13 FDV301N

2 3

R18 27 1 CPU_VDDIO_SUS

CPU_PWROK_L_PIC_3.3 CPU_VID0_L_PIC_3.3 CPU_VID1_L_PIC_3.3 CPU_VID2_L_PIC_3.3 CPU_CORE_TYPE_L_PIC_3.3 SVID_BYPASS_PIC R14

GND Q11 FDV301N

3 2

100K R13 1

GND Q10 FDV301N

3 2

100K R12 1

GND FDV301N Q9

3 2

10K R11 1

GND Q8 FDV301N

3 2

10K R10 1

GND Q7 FDV301N

3 2 10K 0 5V_ALW 1 R9 8,14 8,14 8,14 8,14 14,15 SVID_BYPASS CPU_VID(0) CPU_VID(1) CPU_VID(2) CPU_PWROK CPU_CORE_TYPE

QUICK TURN PROGRAMMING (QTP) REFERENCES – PIC16F506T-I/SL020 “AMD Voltage Regulator and Voltage Regulator A preprogrammed device (QTP) will be available from Module (VRM) Specification”, AMD Publication #40182 Microchip Technology, which implements the translator “Voltage Regulation Design Guide for Processors function developed by AMD. To obtain the programmed Supporting Six-bit VID codes”, AMD Publication device, a special part number has been created so that #31525 programming support is not needed in the final applica- “PIC12F510/PIC16F506 Data Sheet” (DS41268), tion board. The full part number for the programmed http://www.microchip.com. part is PIC16F506T-I/SL020 (tape and reel) or PIC16F506-I/SL020 (tube).

CONCLUSION For questions regarding the translator implementation, or to obtain pricing information, please send e-mail query to [email protected].

NOTES:

DS41309A-page 6 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, ensure that your application meets with your specifications. PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and MICROCHIP MAKES NO REPRESENTATIONS OR SmartShunt are registered trademarks of Microchip WARRANTIES OF ANY KIND WHETHER EXPRESS OR Technology Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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