IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997 2097 A 2.5-GHz BiCMOS Transceiver for Wireless LAN’s Robert G. Meyer, Fellow IEEE, William D. Mack, Senior Member IEEE, and Johannes J. E. M. Hageraats Abstract— A BiCMOS transceiver intended for spread spec- transmit and receive modes. The intermediate frequency (IF) trum applications in the 2.4–2.5 GHz band is described. The in this application is 350 MHz. Both mixers are driven by an IC contains a low-noise amplifier (LNA) with 14 dB gain and on-chip local oscillator (LO) buffer which has full-frequency 2.2 dB NF in its high-gain mode, a downconversion mixer with 8 dB gain and 11 dB NF, and an upconversion mixer with 17 dB LO and half-frequency LO input options, selectable via the gain and I df of C3 dBm out. An on-chip local oscillator (LO) LO switch at pin 11. An on-chip frequency doubler in the LO buffer accepts LO drive of 10 dBm with a half-frequency option buffer together with on-chip LC filters deliver a full-frequency allowed by an on-chip frequency doubler. Power consumption LO signal to the selected mixer with half-frequency LO inputs from a single 3-V supply is 34 mA in transmit mode, 21 mA in applied. The receive mixer differential output is converted receive mode, and 1 "A in sleep mode. to single-ended 50- operation with an external balun. This Index Terms—BiCMOS, doubler, inductor, low-noise amplifier, mixer has 8 dB gain and 11 dB single sideband (SSB) NF. The mixer, transceiver, wireless LAN. transmit mixer accepts single-ended or differential inputs and uses on-chip LC filters together with a medium power buffer I. INTRODUCTION to generate 17-dB gain and deliver 3 dBm output at 2.45 GHz to a separate power amplifier. HERE is currently a great deal of activity directed toward Pin 17 selects transmit or receive modes. In the receive realization of wireless local-area networks (WLAN’s) T mode, the LNA, receive mixer, and the selected LO buffer based on 802.11 specifications. Successful implementation of option are powered up while the transmit mixer and output such systems will require the availability of low-cost high- buffer are powered down. If the transmit mode is selected, performance transceivers operating in the 2.4–2.5 GHz band. the LNA and receive mixer are powered down while the In this paper we describe a low-cost Si IC realized in a high- transmit path is activated with the selected LO buffer option. volume BiCMOS process which contains most of the elements The current consumption of the IC from a 3-V supply is required to realize the RF transmit and receive paths of a 34 mA typical in transmit and 21 mA typical in receive. WLAN transceiver meeting 802.11 requirements. The IC is The whole chip can be powered down by the chip-enable part of a chip set based on BiCMOS technology which allows function at pin 13 with a typical sleep-mode current drain future migration to higher levels of integration in which the of 1 A. Chip enable/disable times, transmit/receive, and RF front end, synthesizers, IF amplifier, in-phase/quadrature receive/transmit switching times are 1 s typical using 50-pF (I/Q) generators, and baseband signal processing may all be external coupling capacitors. combined on a single chip. II. SYSTEM ARCHITECTURE III. CIRCUIT DESIGN CONSIDERATIONS The chip architecture is shown in Fig. 1. The 2.7 mm die is A simplified schematic of the LNA is shown in Fig. 2. In mounted in a 24-pin plastic package (TSSOP24). A low-noise the high-gain mode, the large area (72 ) device biased to amplifier (LNA) is switchable between high- (14 dB) and low- 4 mA is the amplifying device. Input impedance matching is gain ( 13 dB) modes. The high-gain mode with 2.2 dB noise achieved via bond-wire inductance emitter degeneration [1]. In figure (NF), dBm input, and dBm order to temperature compensate the gain, is biased to a input is utilized in weak signal conditions. The low-gain mode proportional-to-absolute temperature (PTAT) current derived with dBm input and dBm input can on-chip from Measured gain temperature coefficient of be selected in moderate-to-strong signal conditions. The LNA 0.002 dB/ C has thus been realized. The low-gain parallel performance is optimized for signal frequencies in the range of path is via emitter follower connected to the same output 2.3 to 2.5 GHz. The signal goes off-chip from the LNA to an pin through matching elements. When the high-gain path is external image-rejection filter and is then input to the receive disabled by turning on and other shunt MOSFET’s, mixer via pin 19, which is also shared by the upconversion connects to the input and is turned on to mixer output. This allows use of the same external filter in both improve input matching and emulate the high-gain mode input impedance. When the high-gain path is active, current-source Manuscript received June 17, 1997; revised August 1, 1997. is turned off and pulls the emitter of high, R. G. Meyer is with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA. turning it off. Thus, the path switching at the LNA is simply W. D. Mack was with Philips Semiconductors, Sunnyvale, CA 94088 USA. realized by hardwiring the two paths in parallel and alternately He is now with Maxim Integrated Products, Sunnyvale, CA 94086 USA. activating either one. J. J. E. M. Hageraats is with Philips Semiconductors, Sunnyvale, CA 94088 USA. A simplified schematic of the LO buffer is shown in Fig. 3. Publisher Item Identifier S 0018-9200(97)08268-1. When the full frequency input is selected, current source 0018–9200/97$10.00 1997 IEEE 2098 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997 Fig. 1. Transceiver architecture and pinout. Fig. 2. Simplified LNA schematic. is on and activates differential pair – Current 2.1 GHz. The resulting LO voltage at is buffered by sources and are held off using MOS switches. The followers and amplified by additional LC-tuned differential full frequency LO input at 2.1 GHz (IF at 350 MHz) is amplifier stages that drive the transmit and receive mixers with amplified by – and the on-chip LC loads tuned to an optimum LO voltage swing that is relatively independent MEYER et al.: 2.5-GHz BiCMOS TRANSCEIVER FOR WIRELESS LAN’S 2099 Fig. 3. Simplified LO buffer schematic. Fig. 4. Effect of inductor mutual coupling on LO buffer frequency response. of the external LO drive. The amplitude of the LO drive to out-of-band signals and noise. The inductors have an unloaded the mixers is chosen to optimize the dynamic range. While of about five at 2.1 GHz. Mutual coupling between the mixer noise figure tends to improve with larger LO drive inductors ( and is layout dependent) has a small voltage [5], the value of begins to degrade [4] for LO but measurable effect on the stage frequency response and voltages larger than about 600 mV pp. For half-frequency LO should be included in simulations [3]. The sensitivity of the inputs, current source is switched off and and are buffer frequency response to coupling between the inductors activated. The four devices and form a is illustrated by the computer simulations shown in Fig. 4. frequency doubling circuit [2] that feeds full-frequency LO The downconversion mixer is shown in Fig. 5. This is currents into the tuned signal path described previously. This a Gilbert-quad-based design with inductive degeneration on circuit was originally used in an application for doubling from the input differential pair provided by on-chip 1-nH spiral 10–20 MHz, but using devices with of 20 GHz it functions inductors. The inductive degeneration improves overload per- effectively at 100 times this frequency. The on-chip inductors formance and input matching with only a small degradation in are invaluable elements in this circuit giving substantial gain mixer noise figure. The second stage of LC-boosted buffering boost, improved output voltage headroom, and attenuation of in the LO path is provided by and The 300- 2100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997 Fig. 5. Receive mixer schematic. and better impedance characteristics at 2.4 GHz for rejection of common-mode signals. The dc voltage at node Bias 1 required to bias the receive mixer is generated as shown in Fig. 7. The mixer bias current mA is derived from an on-chip bandgap-stabilized current source A This requires multiplication by 25 which is achieved by ratioing emitter resistors plus base resistors. Thus K K Transistors and appear in parallel as a 24 device for bias purposes. For the same reason, the 1-K base bias resistors together add 500 to the effective base resistance of the combination. The 50-pF capacitor is a filter to attenuate bias circuit noise fed to the mixer. The current helper in the mirror is a pnp–npn “up–down” combination that allows operation down to 2.7 V on Measured and simulated (using the Spectre RF simulator) SSB NF of the receive mixer Fig. 6. Measured receive mixer gain versus LO power. were both close to 11 dB. The major noise contributors as shown by simulation were the base resistances of and followed by the base resistances of the switching quad.