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LOCKED LOOP IEEE Press 445 Hoes Lane Piscataway, NJ 08854 NANOMETER FREQUENCY SYNTHESIS BEYOND THE PHASE- LOCKED LOOP IEEE Press 445 Hoes Lane Piscataway, NJ 08854 IEEE Press Editorial Board John B. Anderson, Editor in Chief R. Abhari G. W. Arnold F. Canavero D. Goldgof B - M. Haemmerli D. Jacobson M. Lanzerotti O. P. Malik S. Nahavandi T. Samad G. Zobrist Kenneth Moore, Director of IEEE Book and Information Services (BIS) Technical Reviewers Prof. Michael Peter Kennedy, University College Cork Associate Prof. Woogeun Rhee, Tsinghua University Books in the IEEE Press Series on Microelectronic System: A complete list of the titles in this series appears at the end of this volume. NANOMETER FREQUENCY SYNTHESIS BEYOND THE PHASE- LOCKED LOOP LIMING XIU IEEE PRESS A JOHN WILEY & SONS, INC., PUBLICATION Copyright © 2012 by The Institute of Electrical and Electronics Engineers, Inc. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permissions. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifi cally disclaim any implied warranties of merchantability or fi tness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profi t or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data: Xiu, Liming. Nanometer frequency synthesis beyond the phase-locked loop / Liming Xiu. p. cm. ISBN 978-1-118-16263-7 (cloth) 1. Timing circuits. 2. Frequency synthesizers. 3. Very high speed integrated circuits. I. Title. TK7868.T5X83 2012 621.381'32–dc23 2012001531 Printed in the United States of America 10 9 8 7 6 5 4 3 2 1 CONTENTS PREFACE xi 1 CLOCK SIGNAL IN ELECTRONIC SYSTEMS 1 1.1 The Signifi cance of Clock Signal / 1 1.1.1 Clock Signal / 1 1.1.2 The Aim of This Book / 3 1.2 The Characteristics of Clock Signal / 5 1.2.1 Jitter and Phase Noise / 5 1.2.2 Clock Phase / 13 1.2.3 Clock Skew / 15 1.3 Clock Signal Driving Digital System / 18 1.3.1 Clock Signal as a Trigger / 18 1.3.2 Timing-Closure Design Constraint: The Safeguard for Reliable Operation / 18 1.3.3 Clock Jitter and Design Constraint / 21 1.3.4 Clock Skew and Design Constraint / 21 1.4 Clock Signal Driving Sampling System / 24 1.4.1 Clock Signal as a Switch / 24 1.4.2 Clock Signal and Analog-to-Digital Converter / 25 1.4.3 Clock Signal and Digital-to-Analog Converter / 28 1.5 Extracting Clock Signal From Data: Clock Data Recovery / 30 v vi CONTENTS 1.6 Clock Usage in System-on-Chip / 32 1.7 Two Fields: Clock Generation and Clock Distribution / 33 Bibliography / 34 2 CLOCK GENERATION: EXISTING FREQUENCY SYNTHESIS TECHNIQUES 37 2.1 Direct Analog Frequency Synthesis / 38 2.2 Direct Digital Frequency Synthesis / 39 2.3 Indirect Method (Phase-Locked Loop Based) / 41 2.3.1 Brief History / 41 2.3.2 The Basic Structure of the Phase-Locked Loop (PLL) / 42 2.3.3 An Example of Third-Order Type-II Charge Pump PLL / 45 2.3.4 Major PLL Architectures / 47 2.4 The Shared Goal: All Cycles Have Same Length-in-Time / 51 Bibliography / 51 3 TIME-AVERAGE-FREQUENCY 53 3.1 The Scale of Level and the Scale of Time / 53 3.2 What Is Frequency? / 54 3.2.1 How Is Frequency Implemented In Circuit Design? / 55 3.2.2 How Is Frequency Used in Electronic System? / 55 3.2.3 “Instantaneous Frequency” and “Instantaneous Period” / 55 3.3 Reinvestigating the Frequency Concept: the Birth of Time-Average-Frequency / 56 3.4 Time-Average-Frequency in Circuit Implementation / 59 3.5 Average Frequency, Time-Average-Frequency, and Fundamental Frequency / 61 3.6 The Need of a Theory / 62 3.7 The Summary: Why Do We Need Time-Average-Frequency? / 63 Bibliography / 63 4 FLYING-ADDER DIRECT PERIOD SYNTHESIS ARCHITECTURE 65 4.1 The Working Principle / 65 4.1.1 The First Structure / 65 4.1.2 One Step Forward / 67 4.2 The Major Challenges in the Flying-Adder Circuit / 68 4.2.1 The Glitch Problem / 68 CONTENTS vii 4.2.2 The Speed of Accumulator / 70 4.2.3 The Generation of the K Inputs / 70 4.3 The Circuit of Proof of Concept / 74 4.3.1 Using Two Paths to Solve the Glitch Problem / 74 4.3.2 Synchronize the Two Paths / 75 4.3.3 Pipeline for Adder Speed / 76 4.4 The Working Circuitry / 77 4.4.1 The Proof of Glitch-Free / 78 4.4.2 The Order of the Input Signals / 81 4.4.3 The Analysis of Circuit Speed / 81 4.4.4 The Analysis of Power Consumption / 82 4.4.5 The Behavioral Simulation / 82 4.4.6 The Extension to Multipaths / 85 4.5 Frequency Transfer Function, Frequency Range, Frequency Resolution, and Frequency Switching Speed / 87 4.6 The Technique of Post Divider Fractional Bits Recovery / 88 4.6.1 Post Divider Fractional Bits Recovery (PDFR) / 88 4.6.2 PDFR for Virtually Boosting the Number of Inputs K / 89 4.6.3 The Effective Fraction after Post Divider / 90 4.7 Flying-Adder PLL: FAPLL / 90 4.8 Flying-Adder Fractional Divider / 91 4.9 Integer-Flying-Adder Architecture / 92 4.9.1 Integer-Only FAPLL: How Close Can It Reach an Integer? / 92 4.9.2 Incorporating Flying-Adder Fractional Divider Inside Integer-N PLL / 94 4.9.3 Integer-Flying-Adder Architecture / 95 4.10 The Algorithm to Search Optimum Parameters / 98 4.11 The Construction of the Accumulator / 99 4.12 The Construction of the High Speed Multiplex / 104 4.13 Non-2’s Power Flying-Adder Circuit / 107 4.14 Expanding VCO Frequency Range in Nanometer CMOS Processes / 109 4.15 Multiple Flying-Adder Synthesizers / 110 4.16 Flying-Adder Implementation Styles / 111 4.17 Simulation Approaches / 112 4.18 The Impact of Input Mismatch on Output Jitter / 113 4.18.1 The Cause of Mismatch and Its Characteristics / 113 4.18.2 The Mismatch Modeling / 116 viii CONTENTS 4.18.3 The Mismatch and the Frequency Control Word / 117 4.18.4 The Mismatch’s Impact on Output Period / 118 4.18.5 The Mismatch’s Impact on Output Spectrum / 123 4.18.6 Summary on Mismatch’s Impact / 125 4.19 Flying-Adder Circuit as Digital Controlled Oscillator / 127 4.20 Flying-Adder Terminology / 128 4.21 Flying-Adder Synthesizer and Time-Average-Frequency: The Experimental Evidence / 129 4.21.1 The FAPLL Structure / 129 4.21.2 Jitter Performance / 132 4.21.3 Frequency Generation Capability / 133 4.21.4 Frequency Resolution / 133 4.21.5 Frequency Spectrum / 133 4.21.6 Instantaneous Switching Demonstration / 137 4.21.7 Time-Average-Frequency Demonstration / 137 4.21.8 PDFR Demonstration / 144 4.21.9 XIU-Accumulator Evaluation / 144 4.21.10 Input Mismatch Observation / 146 4.21.11 The Flying-Adder Fractional Divider Used Inside PLL / 149 4.21.12 The Integer-Flying-Adder PLL / 151 4.22 Time-Average-Frequency and Setup Constraint: Revisit / 154 4.23 Sense the Frequency Difference: The Time-Average-Frequency Way / 156 4.24 Flying-Adder and Direct Digital Synthesis (DDS): The Difference / 157 4.25 Flying-Adder for Phase (Delay) Synthesis / 158 4.26 Flying-Adder for Duty Cycle Control / 162 4.27 Flying-Adder Synthesizer in Reducing the Number of PLLs in SoC / 163 Bibliography / 164 5 DIGITAL-TO-FREQUENCY CONVERTER 167 5.1 Two Ways of Representing Information / 167 5.2 The Converters for Transforming Information / 168 5.3 The Two Cornerstones of the Digital-to-Frequency Converter / 170 5.4 The Theoretical Foundation of Flying-Adder Digital-to-Frequency Converter / 172 5.4.1 Flying-Adder DFC Mathematical Model and Its State Variables / 173 CONTENTS ix 5.4.2 Flying-Adder DFC as a Finite State Machine (FSM) / 174 5.4.3 The Periodicity in Discrete Time Domain / 175 5.4.4 The Periodicity in Continuous Time Domain / 176 5.4.5 The Time-Average-Frequency / 184 5.4.6 Pulse and Cycle in Time-Average-Frequency Signal / 185 5.4.7 Timing Irregularity in the Time-Average-Frequency Signal / 186 5.4.8 The Sample and Hold Method for Modeling DFC Output / 188 5.4.9 Frequency Spectrum of DFC Output / 190 5.4.10 Amplitude of the Time-Average-Frequency / 191 5.4.11 Relates the Mathematic Model with Real Circuit / 193 5.5 Convert the Spurious Energy to Noise
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