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Reconfigurable Computing Based on Commercial Fpgas UNIVERSIDAD POLITÉCNICA DE MADRID ESCUELA TÉCNICA SUPERIOR DE INGENIEROS INDUSTRIALES Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables. TESIS DOCTORAL Yana Esteves Krasteva Máster en Ingeniería Electrónica, Universidad Técnica de Sofía, Bulgaria 2009 DEPARTAMENTO DE AUTOMÁTICA, INGENIERÍA ELECTRÓNICA E INFORMÁTICA INDUSTRIAL ESCUELA TÉCNICA SUPERIOR DE INGENIEROS INDUSTRIALES Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables. TESIS DOCTORAL Autor: Yana Esteves Krasteva Máster en Ingeniería Electrónica, Universidad Técnica de Sofía. Director: Eduardo de la Torre Arnanz Doctor Ingeniero Industrial por la Universidad Politécnica de Madrid. 2009 Tribunal Tribunal nombrado por el Mgfco. y Excmo. Sr. Rector de la Universidad Politécnica de Madrid, el día de julio de 2009. Presidente: Dr. Javier Uceda Antolín, Universidad Politécnica de Madrid. Vocal: Dr. Manfred Glesner, Technische Universität Darmstadt. Vocal: Dr. Juan Carlos López López, Universidad de Castilla-La Mancha. Vocal: Dr. João Canas Ferreira, Universidade do Porto. Secretario: Dr. Félix B. Tobajas Guerrero, Universidad de Las Palmas de Gran Canaria. Suplente: Dr. Celia López Ongil, Universidad Carlos III de Madrid. Suplente: Dr. Ángel de Castro Martín, Universidad Autónoma de Madrid. Realizado el acto de defensa y lectura de la tesis el día 27 de julio de 2009 en la E.T.S. Ingenieros Industriales. CALIFICACIÓN: EL PRESIDENTE LOS VOCALES EL SECRETARIO A Vladimir A mi Mami Agradecimientos Llegados al punto de rellenar esta página, he querido hacer constancia de mis pensamientos y reconocimientos. Si tengo que resumir todas las experiencias vividas en una frase esta sería: “Realmente es duro pero, a pesar de todo, vale la pena”. Para mí, la valoración de todos estos años es positiva, aunque podría escribir otra tesis proponiendo mejoras (y eso que lo de escribir no es mi fuerte...). A Vladimir: За това че измина този дълаг път с мен. За подкрепата и доверието. Благодаря ти!. A mi Abuela: За безценните учения, и затова че винаги бе, си и ще бъдеш неотлъчно до мен. Благодаря ти бабо, жалко че не ни дочака. Благодаря ти!. A mi Madre: Por trasmitirme su fuerza, darme no sólo oportunidades en la vida, sino también enseñarme a aprovecharlas. Благодаря ти майко от все сърце. Mis agradecimientos a Javi Checa por su infinita bondad y cariño y por ser un contrapeso. Благодаря ви!. A mi Hermana Irina: Por ser un apoyo y un ejemplo importante durante mi estancia en España. A su mari-novio Javi Gordo por los agradables momentos. Благодаря ви!. A mi Hermana Tania: Por ser un apoyo en la distancia y aguantar muchas tormentas en nombre de todos, always with Joost to whom I am also thankful. Благодаря ви!. A mi Padre, espero tu reencuentro. Le agradezco mi Tutor de tesis Eduardo de la Torre, por su paciencia durante el largo proceso de corrección del documento y por su bondad. Gracias! Les agradezco a todos los Profesores del departamento, muy especialmente a Teresa Riesgo, por ser la "culpable" de que haya venido a España y siempre haber apostado por mí y a Jorge por ser mi compi. Gracias! Les agradezco a mis Compañeros, especialmente a Carmen por ayudarme con el “Inglés” y por su apoyo. A Víctor, Leo, Andrés, Rubén, David, Dani y Miroslav. Las risas, las cervezas del Chiri y las reuniones en casas, como fuente de ánimos, fuerza y superación, han sido algo fundamental durante la tesis. También a Ángel, Felipe, Jaime, Ana B., Vincenzo, Benoit, Zoran y Cony. Gracias!. Thanks to the thesis reviewers, Leandro Soares Indrusiak from the University of York (England), Dirk Stroobandt from the University of Gent (Belgium) and José Silva Matos from the University of Porto (Portugal). Thank you! También me gustaría agradecer a todas las personas dentro y fuera de la UPM y del CEI, especialmente a Yolanda y Nieves, que dan apoyo a la investigación. Durante los años de mi estancia en España he vivido algunas mejoras, tanto en la situación de los "precarios" como en las oportunidades y la calidad de la investigación, lo cual me gratifica. Gracias!. Last, but not least, I would like to thank to the open research community. I consider that to share openly the knowledge is the base of a quality research. In this context, special thanks to Departamento de Fundamentos da Computação, Pontifícia Universidade Católica do Rio Grande do Sul (Brasil), to the research group lead by Fremando Moraes and Ney Calazans. Thank you! Resumen Esta tesis doctoral está enmarcada en el campo de investigación de la computación reconfigurable. Este campo ha experimentado un crecimiento abrumador en los últimos años como resultado de la evolución de los dispositivos reconfigurables, donde las Field Programmable Gate Arrays (FPGAs) son el máximo exponente desde el punto de vista comercial. De forma tradicional las empresas de electrónica han seleccionado las FPGAs como prototipos iníciales de productos de altas prestaciones. Luego el sistema final es integrado en Application Specific Integrated Circuits (ASICs) que se producen en grandes volúmenes perimiendo amortiza su alto coste de diseño y producción y aprovechando la ventaja del bajo coste por unidad. Por otro lado, los DSPs (Digital Signal Processing) y los microprocesadores han sido preferidos por su bajo coste ante las FPGAs el campo de los dispositivos con menores requisitos de cómputo. En los últimos años, este panorama está sufriendo una serie de cambios. Ahora el mercado busca mas soluciones “reconfigurables” ya que permiten reducir el tiempo de salida del producto al mercado (time-to-market), aumentar el tiempo del producto en el mercado (time-in-market) y además cubren los amplios requisitos de cómputo. El cambio que se observa, se debe a que los dispositivos programables han evolucionado de simples estructuras programables a complejas plataformas reconfigurables. Las FPGAs del estado de la técnica han alcanzado un grado de integración muy alto y además ahora contienen, dentro de su arquitectura programable, microprocesadores y lógica específica de procesamiento digital de señal. Otro factor sumamente importante para el cambio es que las FPGAs permiten el diseño de dispositivos cuyo hardware pueden ser adaptado, o actualizado, una vez que el producto ya esta entregado e instalado, obteniendo así una flexibilidad en el hardware comparable con la del software, donde la actualización post- venta de los sistemas es una práctica muy explotada de cara a la reducción de costes y la salida rápida al mercado. Por otro lado, y sobre todo en el ámbito académico, existen dispositivos reconfigurables con distinta granularidad que permites alcanzar altas prestaciones en comparación con las FPGAs comerciales de grano fino (comparable con la de los ASICs), pero están restringidas a una aplicación o grupo de aplicaciones. A pesar de que los dispositivos reconfigurables propietarios ofrecen muchas ventajas, esta opción ha sido descartada en la presente tesis debido a que, desde el punto de vista industrial requieren, aparte del diseño del ASIC reconfigurable, el desarrollo de un entorno de diseño completo. Todo esto conlleva a un elevado coste de recursos, además del alejamiento de las propuestas de la industria. La presente tesis se ha centrado en proporcionar soluciones para dispositivos comerciales, FPGAs de grano fino, con la finalidad de aprovechar las herramientas existentes y mantener las soluciones propuestas lo más cerca posible de la industria. Los dispositivos reconfigurables proporcionan diversos métodos de reconfiguración, siendo el más atractivo la reconfiguración parcial y dinámica, ya que permite adaptar el dispositivo sin interrumpir su funcionamiento y crear dispositivos auto-adaptables. Este tipo de reconfiguración será el objeto de estudio de la tesis doctoral. La reconfiguración parcial permite tener una serie de tareas hardware (módulos que se ubican en la estructura reconfigurable) ejecutándose paralelamente en la FPGA y sustituir un bloque por otro, dependiendo de las necesidades del sistema, sin alterar el funcionamiento del resto de bloques. Esta idea básica en teoría brinda la flexibilidad del software al hardware, que combinado con su paralelismo implícito hace del sistema reconfigurable una potente herramienta que puede dar pie a la creación de sistemas adaptables o incluso auto- adaptativos, supercomputadores reconfigurables y hardware bio-inspirado entre otros. Por otro lado, a pesar que algunos proveedores de FPGAs permiten la reconfiguración parcial, el uso de esta técnica aún está restringido al ámbito académico y a sistemas muy básicos. El trabajo de investigación descrito dentro de la presente tesis doctoral ha tenido por objeto el estudio de diversos aspectos de los sistemas parcialmente reconfigurables, la identificación de las principales deficiencias de las soluciones existentes y la propuesta de nuevas soluciones originales. Como resultado del estudio del estado del arte se ha visto que las soluciones existentes son poco flexibles y la escalabilidad de los sistemas que se pueden diseñar es reducida. Por ello las propuestas originales de esta tesis tienen como objetivo permitir el diseño e implementación
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