Division 1
Division Ivor Page1
13.1 Division
Division is difficult for humans and computers. In module on multi-precision arithmetic, the division algorithm is by far the most complex. The pencil and paper method for decimal values requires us to guess the next digit of the quotient at each iteration. The divisor is then multiplied by that quotient digit and the result is subtracted from the reducing dividend. The guess must be adjusted if it is too high or too lowand the multiply and subtract steps must be repeated. Here is the notation:
Dividend z = z2k−1z2k−2 ···z1z0
Divisor d = dk−1dk−2 ···d1d0
Quotient q = qk−1qk−2 ···q1q0
Remainder s = sk−1sk−2 ···s1s0 s = z − d × q sign(s)=sign(z)
To avoid overflow, z<2kd must be true. Division is achieved by repeated application of the recurrence relation:
si+1 = rsi − qi × d where r is the radix, s0 = z and, for non-negative binary operands, 0:si 1University of Texas at Dallas Division 2 Here is a decimal example: 523 ) 9743854 - 523 d*10000 ------4513854 = partial remainder - 4184 d*8000 ------329854 - 3138 d*600 ------16054 - 1569 d*30 ----- 364 remainder, quotient = 18630 After two iterations, z =(d × qi)+si = 523 × 18000 + 329854. In binary the next digit of the quotient is either 0 or 1: 10011 ) 1010110111011 = 5563/19 - 10011 d*2^8, q8=1 ------1010111011 - 10011 d*2^5, q5=1 ------1011011 - 10011 d*2^2, q2=1 ------1111 remainder = 1111, quotient = 100100100 The example shows only those iterations in which the quotient is changed. In this section we will only consider positive operands. There are two simple time-iterative division algorithms that cause a subtrac- tion or addition on every cycle. Restoring division keeps the partial remainder sj positive and performs up to k cycles in which a subtraction and, sometimes, an addition takes place. In non-restoring division each cycle requires either an add or a subtract. Division 3 13.2 Restoring Division For Operands > 0 1. Initially s = the dividend, d = the divisor, and the quotient q =0 2. left shift dpplaces until its most significant bit aligns with the most significant bit of s and set the iteration count i = p 3. subtract d from s 4. if the result is negative, add d to s undoing the previous step, else set the quotient bit, qi =1 5. right shift d one place 6. reduce i by 1 7. if i>0 got to step 3 At the end of the algorithm, s is the remainder and q is the quotient. The example on page 4 uses the restoring algorithm. 13.3 Non-Restoring Division For Operands > 0 1. Initially s = the dividend, d = the divisor, and the quotient q =0 2. left shift dpplaces until its most significant bit aligns with the most significant bit of s and set the iteration count i = p 3. if s>0 subtract d from s and set qi =1, else add d to s 4. right shift d one place 5. reduce i by 1 6. if i>0 got to step 3 7. if s<0addd to s. At the end of the algorithm, s is the remainder and q is the quotient. Here is an example of the non-restoring algorithm: Division 4 10011 ) 101011011 = 347/19 - 10011 d*2^4 ------00101011 answer positive, q4=1 - 10011 d*2^3 ------10010011 answer negative, q3=0 + 10011 d*2^2 ------11011111 answer negative, q2=0 + 10011 d*2^1 ------00000101 answer positive, q1=1 - 10011 d*2^0 ------11110010 answer negative, q0=0 + 10011 Restore remainder ----- 101 remainder=101, quotient=10010 13.4 Hardware Organization Figure 1 shows the hardware setup. Initially the dividend z is loaded into the double register u, v and the carry flip-flop is set, c = 1. The first cycle comprises a subtraction of the divisor d from u, the upper half of the divi- dend. Subtraction is achieved by is setting the carry-in of the adder to 1 and presenting the 1’s complement of the divisor to the adder. The u, v register is then left-shifted one place. If cout = 1, the result is positive and a 1 is inserted into the lsb of the v register. Otherwise a 0 is inserted. After the subtraction, c is set to the carry-out of the adder. On cycles where c =0, the partial remainder is negative and an add cycle takes place, followed by the left-shift of u, v.Afterk cycles, if c = 0 an extra add occurs to restore the remainder. The quotient is in v and the remainder is in u. If initially u>d, then the quotient is larger than k bitsandanoverflow results. This condition should be detected before the division begins. Division 5 divisor d k k-bit adder cout cin c u v lsb k k Figure 1: Shift/Add Divider 13.5 SRT Division The SRT scheme, named after its inventors, Sweeney, Robertson, and Tocher, skips over sequences of 1s or 0s in the partial result register u.Intheversion of the algorithm presented first, the quotient bits are set to 1 or 0. Other forms are possible, as we shall see. The algorithm begins with the assumption that the operands are normalized. To make this simple, let’s assume that a binary point is inserted to the left of the msb of both divisor and dividend. In practice, both will be left-justify- shifted in their respective registers. Then z =0.z2k−1z2k−2 ···z1z0 d =0.dk−1dk−2 ···d1d0 0.5 ≤ z < 1 0.5 ≤ d < 1 Although the notation assumes the two operands are binary fractions, the algorithm works perfectly for integer operands. Division is performed by iteratively executing the recurrence relation: si+1 =2si − qi × d Division 6 Initially s0 = z. If, after an addition or subtraction, si is positive and its most significant bit is zero, there is little point in doing another subtraction cycle. Therefore, when there are n leading 0s at the most significant end of si,theu, v register can be left shifted n places and a 1 followed by n−1 zeros can be shifted into the least significant end of v, setting n quotient bits. By similar reasoning, if the result is negative, and there are n 1s at the most significant end of si,theu, v register can be left shifted n places and a 0 followed by n − 1 1s can be shifted into the least significant end of v.Here is an example of 339/19 in a 16 bit system. 0.0000000101010011 = 339 0.00010011 = 19*2^8, left shift d 3 places to normalize 0.10011000 19*2^11 left shift z 3 places to match 0.0000101010011*** 339*2^3 left shift z 4 more places to normalize 0.101010011***0000 339*2^7 -0.10011000 subtract ------0.000100011***0000 shift over 3 0s, shift in 100 0.100011***0000100 -0.10011000 subtract ------1.111101***0000100 shift over 2 1s, shift in 01 1.1101***000010001 u<0, right shift u 1 place, add 1.11101***00010001 +0.10011000 ------0.10000***00010001 remainder = u/2^3 = 10000, quotient = v = 10001 First the divisor is normalized by left shifting it hd = 3 places. Then the dividend is normalized by left shifting hz = 7 places in u, v. In the example, this step is broken into 2 steps to aid the reader, so that the asterisks can be inserted to mark the position of the final remainder. At the end of the process, the remainder will occupy those bits to the left of the asterisks. The algorithm proceeds by subtracting d. If, after each addition or subtraction, the value of si in u, v is positive the algorithm shifts u, v left one place and shifts a 1 into the lsb of v. Then, if Division 7 there are p leading 0s after the point, u, v is left shifted p places while p 0s are shifted into the least significant end of u, v. If the resulting si value is negative, the algorithm shifts u, v one place left and shifts a 1 into the lsb of v. Then, if there are p leading 1s after the point, u, v is left shifted p places while p 1s are shifted into the least significant end of u, v. Then the algorithm either adds d or subtracts it from u, depending on the sign of u. The algorithm terminates when all the quotient bits have been computed. This requires a total of k + 1 shifts. If, during normalization, the dividend is shifted hz places and the divisor hd places, then the shift counter begins with value k − hz + hd + 1. In the example, this value is 8 − 7+3+1=5. After normalization, there are shifts over 3 0s and 2 1s. If, after termination, the partial remainder is negative, as in the example, the u register is right shifted one place and an addition is performed to correct the remainder. The quotient in v is not affected by this correction step. Finally, the remainder is found by right shifting the u register hd + 1 places, minus 1 if the remainder was corrected, In the example, hd + 1 = 4. We must subtract 1 since the remainder was corrected. The u register is therefore right shifted 3 places. An upper limit of k+1 addition/subtraction cycles may be required, although it has been calculated that, on average, the SRT algorithm skips over 2.67 bits in between add/subtract cycles. 13.6 Signed operands with SRT The SRT algorithm operates correctly with signed operands. In the initial normalization step, the bits shifted into the right hand end of the quotient depend on the sign of the quotient being developed, 1s for a negative quo- tient, 0s for a positive quotient. Then, during the iterations, additions or subtractions take place such that the partial remainder is always reduced to- wards zero. For example, if the partial remainder is negative and the divisor is also negative, then a subtraction takes place. In general, subtraction is used in those cycles where the signs of the partial remainder and the divisor Division 8 are the same. Addition is used when their signs differ. After termination, a correction may be necessary to deliver a remainder that has the same sign as the dividend. 13.6.1 Using a Carry-Save Adder If a carry-save adder is used, the speed advantage of shifting over several bits is lost since addition and subtraction take no longer to perform than the logic needed to calculate and manage the shifts. The SRT algorithm is therefore not used in practice. Unfortunately, if the partial remainder is kept in carry-save form with unre- solved carries, its sign is not immediately available. In the next module we shall see how to estimate its sign and discover what to do when our estimate is wrong.