High-Level Synthesis Philippe Coussy • Adam Morawiec Editors

High-Level Synthesis Philippe Coussy • Adam Morawiec Editors High-Level Synthesis From Algorithm to Digital Circuit Philippe Coussy Adam Morawiec Université Européenne European Electronic Chips & Systems de Bretagne - UBS design Initiative (ECSI) Laboratoire Lab-STICC 2 av. de Vignate Centre de Recherche 38610 Grieres BP 92116 France 56321 Lorient Cedex [email protected] France [email protected] ISBN 978-1-4020-8587-1 e-ISBN 978-1-4020-8588-8 Library of Congress Control Number: 2008928131 c 2008 Springer Science + Business Media B.V. No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Cover illustration: Cover design by Martine Piazza, Adam Morawiec and Philippe Coussy Printed on acid-free paper. 987654321 springer.com Foreword High-level synthesis – also called behavioral and architectural-level synthesis – is a key design technology to realize systems on chip/package of various kinds, whether single or multi-processors, homogeneous or heterogeneous, for the embed- ded systems market or not. Actually, as technology progresses and systems become increasingly complex, the use of high-level abstractions and synthesis methods becomes more and more a necessity. Indeed, the productivity of designers increases with the abstraction level, as demonstrated by practices in both the software and hardware domains. The use of high-level models allows designers with systems, rather than circuit, background to be productive, thus matching the trend of industry which is delivering an increasingly larger number of integrated systems as compared to integrated circuits. The potentials of high-level synthesis relate to leaving implementation details to the design algorithms and tools, including the ability to determine the precise timing of operations, data transfers, and storage. High-level optimization, coupled with high-level synthesis, can provide designers with the optimal concurrency struc- ture for a data flow and corresponding technological constraints, thus providing the balancing act in the trade-off between latency and resource usage. For complex systems, the design space exploration, i.e., the systematic search for the Pareto-optimal points, can only be done by automated high-level synthesis and optimization tools. Nevertheless, high-level synthesis has been showing a long gestation period. Despite early results in the 1980s, it is still not common practice in hardware design. The slow acceptance-rate of this important technology has been attributed to a few factors such as designers’ desire to micromanage integrated systems by controlling their internal timing and the lack of a universal standard front-end language. The former issue is typical of novel technologies: as systems grow in size it will be nec- essary for designers to show a broader system vision and fewer concerns on internal timing. In other words, this problem will naturally disappear. The Babel of high-level modeling languages has been a significant obstacle to the development of this technology. When high-level synthesis was introduced in the 1980s, the designer community embraced Verilog and VHDL as specifica- tion languages, due to their ability to perform efficient simulation. Nevertheless, v vi Foreword such languages were conceived without an intrinsic hardware semantics, making synthesis more cumbersome. C-based hardware description languages (CHDLs) surfaced in the 1980s as well, such as HardwareC and its hardware compiler Hercules. The limitations of HardwareC and similar CHDLs are rooted in the modification of the C language semantics to support hardware constructs, thus making each CHDL a different dialect of C. The introduction of SystemC in the 1990s solved the problem by not modifying the software programming language (in this case C++) and by introduc- ing a class library with a well-defined hardware semantics. It is regrettable that the initial enthusiasm was mitigated by the limited support of high-level synthesis for SystemC. The turn of the century was characterized by a renewed interest in CHDLs and in high-level synthesis from CHDLs. New companies carried the torch of educat- ing designers with new models and tools for design. Today, there are several offers in high-level synthesis tools that provide effective solutions in silicon. Moreover, some of the technical roadblocks to high-level synthesis have been overcome. Syn- thesis of C-based models with pointers and memory allocators was demonstrated and patented by Stanford jointly with NEC, thus removing the last hard technical difficulty to synthesize full C-based models. At present, the potentials of high-level synthesis are still very good, even though the designers’ community has not yet converged on a single modeling language that would lower the entry barrier of tools into the marketplace. This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. This book should be on each designer’s and CAD developer’s shelf, as well as on those of project managers who will soon embrace high-level design and synthesis for all aspects of digital system design. EPF Lausanne, 2008 Giovanni De Micheli Contents 1 User Needs ................................................. 1 Pascal Urard, Joonhwan Yi, Hyukmin Kwon, and Alexandre Gouraud 2 High-Level Synthesis: A Retrospective .......................... 13 Rajesh Gupta and Forrest Brewer 3 Catapult Synthesis: A Practical Introduction to Interactive C Synthesis .................................................. 29 Thomas Bollaert 4 Algorithmic Synthesis Using PICO ............................. 53 Shail Aditya and Vinod Kathail 5 High-Level SystemC Synthesis with Forte’s Cynthesizer ........... 75 Michael Meredith 6 AutoPilot: A Platform-Based ESL Synthesis System .............. 99 Zhiru Zhang, Yiping Fan, Wei Jiang, Guoling Han, Changqi Yang, and Jason Cong 7 “All-in-C” Behavioral Synthesis and Verification with CyberWorkBench ....................................... 113 Kazutoshi Wakabayashi and Benjamin Carrion Schafer 8 Bluespec: A General-Purpose Approach to High-Level Synthesis Based on Parallel Atomic Transactions ......................... 129 Rishiyur S. Nikhil 9 GAUT: A High-Level Synthesis Tool for DSP Applications ......... 147 Philippe Coussy, Cyrille Chavet, Pierre Bomel, Dominique Heller, Eric Senn, and Eric Martin 10 User Guided High Level Synthesis ............................. 171 Ivan AugéandFrédéric Pétrot vii viii Contents 11 Synthesis of DSP Algorithms from Infinite Precision Specifications .. 197 Christos-Savvas Bouganis and George A. Constantinides 12 High-Level Synthesis of Loops Using the Polyhedral Model ........ 215 Steven Derrien, Sanjay Rajopadhye, Patrice Quinton, and Tanguy Risset 13 Operation Scheduling: Algorithms and Applications .............. 231 Gang Wang, Wenrui Gong, and Ryan Kastner 14 Exploiting Bit-Level Design Techniques in Behavioural Synthesis ... 257 Mar´ıa Carmen Molina, Rafael Ruiz-Sautua, José Manuel Mend´ıas, and Román Hermida 15 High-Level Synthesis Algorithms for Power and Temperature Minimization ............................................... 285 Li Shang, Robert P. Dick, and Niraj K. Jha Contributors Shail Aditya Synfora, Inc., 2465 Latham Street, Suite #300, Mountain View, CA 94040, USA, [email protected] Ivan Augé UPMC-LIP6/SoC, Equipe´ ASIM/LIP6, Université Pierre et Marie Curie, Paris, France, [email protected] Thomas Bollaert Mentor Graphics, 13/15 rue Jeanne Braconnier, 92360 Meudon-la-Foret, France, Thomas [email protected] Pierre Bomel European University of Brittany – UBS, Lab-STICC, BP 92116, 56321 Lorient Cedex, France, [email protected] Christos-Savvas Bouganis Department of Electrical and Electronic Engineering, Imperial College London, South Kensington Campus, London SW7 2AZ, UK, [email protected] Forrest Brewer Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106-9560, USA, [email protected] Cyrille Chavet European University of Brittany – UBS, Lab-STICC, BP 92116, 56321 Lorient Cedex, France, [email protected] ix x Contributors Jason Cong AutoESL Design Technolgoies, Inc., 12100 Wilshire Blvd, Los Angeles, CA 90025, USA and UCLA Computer Science Department, Los Angeles, CA 90095-1596, USA, [email protected], [email protected] George A. Constantinides Department of Electrical and Electronic Engineering, Imperial College London, South Kensington Campus, London SW7 2AZ, UK, [email protected] Philippe Coussy European University of Brittany – UBS, Lab-STICC, BP 92116, 56321 Lorient Cedex, France, [email protected] Steven Derrien Irisa, universit’e de Rennes 1, Campus de beaulieu, 35042 Rennes Cedex, France, [email protected] Robert P. Dick Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA, [email protected] Yiping Fan AutoESL Design Technolgoies, Inc., 12100 Wilshire Blvd, Los Angeles, CA 90025, USA, [email protected] Wenrui Gong Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA, [email protected] Alexandre Gouraud France Telecom

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