DOCSLIB.ORG

IA-32 Intel® Architecture Software Developer's Manual

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
IA-32 Intel® Architecture Software Developer's Manual IA-32 Intel® Architecture Software Developer’s Manual Volume 1: Basic Architecture NOTE: The IA-32 Intel Architecture Software Developer’s Manual consists of three volumes: Basic Architecture, Order Number 245470-012; Instruction Set Reference, Order Number 245471-012; and the System Programming Guide, Order Number 245472-012. Please refer to all three volumes when evaluating your design needs. 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® IA-32 architecture processors (e.g., Pentium® 4 and Pentium III processors) may contain design defects or errors known as errata. Current characterized errata are available on request. Intel, Intel386, Intel486, Pentium, Intel Xeon, Intel NetBurst, Intel SpeedStep, MMX, Celeron, and Itanium are trademarks or registered trademarks of Intel Corporation and its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-7641 or call 1-800-879-4683 or visit Intel’s website at http://www.intel.com COPYRIGHT © 1997-2003 INTEL CORPORATION CONTENTS PAGE CHAPTER 1 ABOUT THIS MANUAL 1.1. IA-32 PROCESSORS COVERED IN THIS MANUAL . 1-1 1.2. OVERVIEW OF THE IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTURE . 1-2 1.3. NOTATIONAL CONVENTIONS. 1-3 1.3.1. Bit and Byte Order. .1-3 1.3.2. Reserved Bits and Software Compatibility . .1-4 1.3.3. Instruction Operands . .1-5 1.3.4. Hexadecimal and Binary Numbers . .1-5 1.3.5. Segmented Addressing . .1-5 1.3.6. Exceptions. .1-6 1.4. RELATED LITERATURE . 1-6 CHAPTER 2 INTRODUCTION TO THE IA-32 INTEL ARCHITECTURE 2.1. BRIEF HISTORY OF THE IA-32 ARCHITECTURE. 2-1 2.1.1. The First Microprocessors. .2-1 2.1.2. Introduction of Protected Mode Operation. .2-2 2.1.3. Advent of 32-bit Processors . .2-2 2.1.4. The Intel486™ Processor . .2-2 2.1.5. The Intel® Pentium® Processor . .2-3 2.1.6. The P6 Family of Processors . .2-3 2.1.7. The Intel Pentium 4 Processor . .2-5 2.1.8. The Intel® Xeon™ Processor . .2-6 2.1.9. The Intel Pentium M Processor . .2-6 2.2. MORE ON MAJOR TECHNICAL ADVANCES . 2-6 2.2.1. The P6 Family Micro-architecture . .2-7 2.2.2. Streaming SIMD Extensions 2 (SSE2) Technology . .2-8 2.2.3. The Intel® NetBurst™ Micro-Architecture . .2-9 2.2.3.1. The Front End Pipeline. .2-11 2.2.3.2. OUT-OF-order Execution Core. .2-12 2.2.3.3. Retirement Unit. .2-12 2.2.4. Hyper-Threading Technology . .2-12 2.2.4.1. Notes on Implementation . .2-14 2.3. MOORE’S LAW AND IA-32 PROCESSOR GENERATIONS . 2-14 CHAPTER 3 BASIC EXECUTION ENVIRONMENT 3.1. MODES OF OPERATION . 3-1 3.2. OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT . 3-2 3.3. MEMORY ORGANIZATION. 3-5 3.3.1. Modes of Operation vs. Memory Model. .3-7 3.3.2. 32-Bit vs. 16-Bit Address and Operand Sizes . .3-7 3.3.3. Extended Physical Addressing . .3-8 3.4. BASIC PROGRAM EXECUTION REGISTERS . 3-8 3.4.1. General-Purpose Registers. .3-8 3.4.2. Segment Registers . .3-10 iii CONTENTS PAGE 3.4.3. EFLAGS Register . .3-12 3.4.3.1. Status Flags . .3-14 3.4.3.2. DF Flag. .3-15 3.4.4. System Flags and IOPL Field . .3-15 3.5. INSTRUCTION POINTER . 3-16 3.6. OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES. 3-16 3.7. OPERAND ADDRESSING. 3-17 3.7.1. Immediate Operands. .3-18 3.7.2. Register Operands . .3-18 3.7.3. Memory Operands. .3-19 3.7.3.1. Specifying a Segment Selector. .3-19 3.7.3.2. Specifying an Offset . .3-20 3.7.3.3. Assembler and Compiler Addressing Modes . .3-22 3.7.4. I/O Port Addressing . .3-22 CHAPTER 4 DATA TYPES 4.1. FUNDAMENTAL DATA TYPES. 4-1 4.1.1. Alignment of Words, Doublewords, Quadwords, and Double Quadwords . .4-2 4.2. NUMERIC DATA TYPES . 4-3 4.2.1. Integers . .4-4 4.2.1.1. Unsigned Integers. .4-4 4.2.1.2. Signed Integers. .4-4 4.2.2. Floating-Point Data Types. .4-5 4.3. POINTER DATA TYPES . 4-7 4.4. BIT FIELD DATA TYPE . 4-7 4.5. STRING DATA TYPES . 4-8 4.6. PACKED SIMD DATA TYPES . 4-8 4.6.1. 64-Bit SIMD Packed Data Types. .4-8 4.6.2. 128-Bit Packed SIMD Data Types. .4-9 4.7. BCD AND PACKED BCD INTEGERS . 4-10 4.8. REAL NUMBERS AND FLOATING-POINT FORMATS. 4-11 4.8.1. Real Number System . .4-12 4.8.2. Floating-Point Format . .4-12 4.8.2.1. Normalized Numbers . .4-14 4.8.2.2. Biased Exponent. .4-14 4.8.3. Real Number and Non-number Encodings . .4-14 4.8.3.1. Signed Zeros . .4-16 4.8.3.2. Normalized and Denormalized Finite Numbers . ..
Load more

Recommended publications
  • Fencing Cyberspace: Drawing Borders in a Virtual World Maureen A
    University of Minnesota Law School Scholarship Repository Minnesota Law Review 1998 Fencing Cyberspace: Drawing Borders in a Virtual World Maureen A. O'Rourke Follow this and additional works at: https://scholarship.law.umn.edu/mlr Part of the Law Commons Recommended Citation O'Rourke, Maureen A., "Fencing Cyberspace: Drawing Borders in a Virtual World" (1998). Minnesota Law Review. 1923. https://scholarship.law.umn.edu/mlr/1923 This Article is brought to you for free and open access by the University of Minnesota Law School. It has been accepted for inclusion in Minnesota Law Review collection by an authorized administrator of the Scholarship Repository. For more information, please contact [email protected]. Fencing Cyberspace: Drawing Borders in a Virtual World Maureen A. O'Rourke* Introduction ............................................................................... 610 I. An Introduction to the Internet and the World W ide W eb .................................................................. 615 A. Origins of the Internet ................................................... 615 B. Development of the World Wide Web ........................... 619 C. Emergence of the Internet as a Commercial Marketplace ............................................... 624 1. Development of the Marketplace .............................. 624 2. Web Business Models ................................................ 625 a. Advertising-Based Models ................................... 626 b. Subscription-Based Models .................................
    [Show full text]
  • Intel® IA-64 Architecture Software Developer's Manual
    Intel® IA-64 Architecture Software Developer’s Manual Volume 1: IA-64 Application Architecture Revision 1.1 July 2000 Document Number: 245317-002 THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel® IA-64 processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800- 548-4725, or by visiting Intel’s website at http://developer.intel.com/design/litcentr.
    [Show full text]
  • Survey of Methodologies, Approaches, and Challenges in Parallel Programming Using High-Performance Computing Systems
    Hindawi Scientific Programming Volume 2020, Article ID 4176794, 19 pages https://doi.org/10.1155/2020/4176794 Review Article Survey of Methodologies, Approaches, and Challenges in Parallel Programming Using High-Performance Computing Systems Paweł Czarnul ,1 Jerzy Proficz,2 and Krzysztof Drypczewski 2 1Dept. of Computer Architecture, Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology, Gda´nsk, Poland 2Centre of Informatics–Tricity Academic Supercomputer & Network (CI TASK), Gdansk University of Technology, Gdan´sk, Poland Correspondence should be addressed to Paweł Czarnul; [email protected] Received 11 October 2019; Accepted 30 December 2019; Published 29 January 2020 Guest Editor: Pedro Valero-Lara Copyright © 2020 Paweł Czarnul et al. ,is is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. ,is paper provides a review of contemporary methodologies and APIs for parallel programming, with representative tech- nologies selected in terms of target system type (shared memory, distributed, and hybrid), communication patterns (one-sided and two-sided), and programming abstraction level. We analyze representatives in terms of many aspects including programming model, languages, supported platforms, license, optimization goals, ease of programming, debugging, deployment, portability, level of parallelism, constructs enabling parallelism and synchronization, features introduced in recent versions indicating trends, support for hybridity in parallel execution, and disadvantages. Such detailed analysis has led us to the identification of trends in high-performance computing and of the challenges to be addressed in the near future. It can help to shape future versions of programming standards, select technologies best matching programmers’ needs, and avoid potential difficulties while using high- performance computing systems.
    [Show full text]
  • Over View of Microprocessor 8085 and Its Application
    IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 6, Ver. II (Nov - Dec .2015), PP 09-14 www.iosrjournals.org Over view of Microprocessor 8085 and its application Kimasha Borah Assistant Professor, Centre for Computer Studies Centre for Computer Studies, Dibrugarh University, Dibrugarh, Assam, India Abstract: Microprocessor is a program controlled semiconductor device (IC), which fetches, decode and executes instructions. It is versatile in application and is flexible to some extent. Nowadays, modern microprocessors can perform extremely sophisticated operations in areas such as meteorology, aviation, nuclear physics and engineering, and take up much less space as well as delivering superior performance Here is a brief review of microprocessor and its various application Key words: Semi Conductor, Integrated Circuits, CPU, NMOS ,PMOS, VLSI I. Introduction: Microprocessor is derived from two words micro and processor. Micro means small, tiny and processor means which processes something. It is a single Very Large Scale of Integration (VLSI) chip that incorporates all functions of central processing unit (CPU) fabricated on a single Integrated Circuits (ICs) (1).Some other units like caches, pipelining, floating point processing arithmetic and superscaling units are additionally present in the microprocessor and that results in increasing speed of operation.8085,8086,8088 are some examples of microprocessors(2). The technology used for microprocessor is N type metal oxide semiconductor(NMOS)(3). Basic operations of microprocessor are fetching instructions from memory ,decoding and executing them ie it takes data or operand from input device, perform arithmetic and logical operations and store results in required location or send result to output devices(1).Word size identifies the microprocessor.E.g.
    [Show full text]
  • Appendix D an Alternative to RISC: the Intel 80X86
    D.1 Introduction D-2 D.2 80x86 Registers and Data Addressing Modes D-3 D.3 80x86 Integer Operations D-6 D.4 80x86 Floating-Point Operations D-10 D.5 80x86 Instruction Encoding D-12 D.6 Putting It All Together: Measurements of Instruction Set Usage D-14 D.7 Concluding Remarks D-20 D.8 Historical Perspective and References D-21 D An Alternative to RISC: The Intel 80x86 The x86 isn’t all that complex—it just doesn’t make a lot of sense. Mike Johnson Leader of 80x86 Design at AMD, Microprocessor Report (1994) © 2003 Elsevier Science (USA). All rights reserved. D-2 I Appendix D An Alternative to RISC: The Intel 80x86 D.1 Introduction MIPS was the vision of a single architect. The pieces of this architecture fit nicely together and the whole architecture can be described succinctly. Such is not the case of the 80x86: It is the product of several independent groups who evolved the architecture over 20 years, adding new features to the original instruction set as you might add clothing to a packed bag. Here are important 80x86 milestones: I 1978—The Intel 8086 architecture was announced as an assembly language– compatible extension of the then-successful Intel 8080, an 8-bit microproces- sor. The 8086 is a 16-bit architecture, with all internal registers 16 bits wide. Whereas the 8080 was a straightforward accumulator machine, the 8086 extended the architecture with additional registers. Because nearly every reg- ister has a dedicated use, the 8086 falls somewhere between an accumulator machine and a general-purpose register machine, and can fairly be called an extended accumulator machine.
    [Show full text]
  • SAP Solutions on Vmware Vsphere Guidelines Summary and Best Practices
    SAP On VMware Best Practices Version 1.1 December 2015 © 2015 VMware, Inc. All rights reserved. Page 1 of 61 SAP on VMware Best Practices © 2015 VMware, Inc. All rights reserved. This product is protected by U.S. and international copyright and intellectual property laws. This product is covered by one or more patents listed at http://www.vmware.com/download/patents.html. VMware is a registered trademark or trademark of VMware, Inc. in the United States and/or other jurisdictions. All other marks and names mentioned herein may be trademarks of their respective companies. VMware, Inc. 3401 Hillview Ave Palo Alto, CA 94304 www.vmware.com © 2015 VMware, Inc. All rights reserved. Page 2 of 61 SAP on VMware Best Practices Contents 1. Overview .......................................................................................... 5 2. Introduction ...................................................................................... 6 2.1 Support ........................................................................................................................... 6 2.2 SAP ................................................................................................................................ 6 2.3 vCloud Suite ................................................................................................................... 9 2.4 Deploying SAP with vCloud Suite ................................................................................ 11 3. Virtualization Overview ..................................................................
    [Show full text]
  • Oracle Solaris and Oracle SPARC Systems—Integrated and Optimized for Mission Critical Computing
    An Oracle White Paper September 2010 Oracle Solaris and Oracle SPARC Servers— Integrated and Optimized for Mission Critical Computing Oracle Solaris and Oracle SPARC Systems—Integrated and Optimized for Mission Critical Computing Executive Overview ............................................................................. 1 Introduction—Oracle Datacenter Integration ....................................... 1 Overview ............................................................................................. 3 The Oracle Solaris Ecosystem ........................................................ 3 SPARC Processors ......................................................................... 4 Architected for Reliability ..................................................................... 7 Oracle Solaris Predictive Self Healing ............................................ 7 Highly Reliable Memory Subsystems .............................................. 9 Oracle Solaris ZFS for Reliable Data ............................................ 10 Reliable Networking ...................................................................... 10 Oracle Solaris Cluster ................................................................... 11 Scalable Performance ....................................................................... 14 World Record Performance ........................................................... 16 Sun FlashFire Storage .................................................................. 19 Network Performance ..................................................................
    [Show full text]
  • An 8085 Microprocessor Based Monitor System for a 750 Cc Honda Motorcycle
    Rochester Institute of Technology RIT Scholar Works Theses 1988 An 8085 Microprocessor based monitor system for a 750 cc Honda motorcycle Robert H. Leet Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Leet, Robert H., "An 8085 Microprocessor based monitor system for a 750 cc Honda motorcycle" (1988). Thesis. Rochester Institute of Technology. Accessed from This Thesis is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. Rochester Institute of Technology School of Computer Science and Technology An 8085 Microprocessor Based Monitor System For A 750 cc Honda Motorcycle By Robert H. Leet A thesis, submitted to The Faculty of the School of Computer Science and Technology, in partial fulfillment of the requirements for the degree of Master of Science in Computer Science Approved by: Protapa Reddy Dr. Protapa Reddy Peter G. Andrews Dr. Peter Anderson Rayno N,eimi Dr. Rayno Niemi March 24, 1988 I Robert H. Leet prefer to be contacted each time a ~equest for reproduction is made. I can be reached at the following address: 15417 Preston Road #1152 Dallas, Texas 75248 Ma r c h 2 5, 1 9 8 8 Abstract This system replaces the analog speedometer and tachometer gauge cluster of a 750 cc Honda motorcycle with a computerized monitor system based on the INTEL 8085A microprocessor and family of peripherals. The system adds the enhanced functionality of engine temperature, battery charging, fuel level, turn signal, and kick stand monitoring and status display.
    [Show full text]
  • Cluster Suite Overview
    Red Hat Enterprise Linux 4 Cluster Suite Overview Red Hat Cluster Suite for Red Hat Enterprise Linux Edition 1.0 Last Updated: 2020-03-08 Red Hat Enterprise Linux 4 Cluster Suite Overview Red Hat Cluster Suite for Red Hat Enterprise Linux Edition 1.0 Landmann [email protected] Legal Notice Copyright © 2009 Red Hat, Inc. This document is licensed by Red Hat under the Creative Commons Attribution-ShareAlike 3.0 Unported License. If you distribute this document, or a modified version of it, you must provide attribution to Red Hat, Inc. and provide a link to the original. If the document is modified, all Red Hat trademarks must be removed. Red Hat, as the licensor of this document, waives the right to enforce, and agrees not to assert, Section 4d of CC-BY-SA to the fullest extent permitted by applicable law. Red Hat, Red Hat Enterprise Linux, the Shadowman logo, the Red Hat logo, JBoss, OpenShift, Fedora, the Infinity logo, and RHCE are trademarks of Red Hat, Inc., registered in the United States and other countries. Linux ® is the registered trademark of Linus Torvalds in the United States and other countries. Java ® is a registered trademark of Oracle and/or its affiliates. XFS ® is a trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other countries. MySQL ® is a registered trademark of MySQL AB in the United States, the European Union and other countries. Node.js ® is an official trademark of Joyent. Red Hat is not formally related to or endorsed by the official Joyent Node.js open source or commercial project.
    [Show full text]
  • Programmable Digital Microcircuits - a Survey with Examples of Use
    - 237 - PROGRAMMABLE DIGITAL MICROCIRCUITS - A SURVEY WITH EXAMPLES OF USE C. Verkerk CERN, Geneva, Switzerland 1. Introduction For most readers the title of these lecture notes will evoke microprocessors. The fixed instruction set microprocessors are however not the only programmable digital mi• crocircuits and, although a number of pages will be dedicated to them, the aim of these notes is also to draw attention to other useful microcircuits. A complete survey of programmable circuits would fill several books and a selection had therefore to be made. The choice has rather been to treat a variety of devices than to give an in- depth treatment of a particular circuit. The selected devices have all found useful ap• plications in high-energy physics, or hold promise for future use. The microprocessor is very young : just over eleven years. An advertisement, an• nouncing a new era of integrated electronics, and which appeared in the November 15, 1971 issue of Electronics News, is generally considered its birth-certificate. The adver• tisement was for the Intel 4004 and its three support chips. The history leading to this announcement merits to be recalled. Intel, then a very young company, was working on the design of a chip-set for a high-performance calculator, for and in collaboration with a Japanese firm, Busicom. One of the Intel engineers found the Busicom design of 9 different chips too complicated and tried to find a more general and programmable solu• tion. His design, the 4004 microprocessor, was finally adapted by Busicom, and after further négociation, Intel acquired marketing rights for its new invention.
    [Show full text]
  • APPLICATION NOTE Ap·113
    APPLICATION Ap·113 NOTE February 1981 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subjectto restrictions stated in Intel's software license, or as defined in ASPR 7-104.9 (a) (9). Intel Corporation a!=;sumes no resDonsibilitv for the use of anv circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation. The following are trademarks of Intel Corporation and may only be used to identify Intel products: BXP Intelevision MULTIBUS* CREDIT Intellec MULTIMODULE i iSBC Plug-A-Bubble ICE iSBX PROMPT ICS Library Manager Promware im MCS RMX Insite Megachassis UPI Intel Micromap ~Scope System 2000 and the combinations of ICE, iCS, iSBC, MCS or RMX and a numerical suffix. MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corporation. *MULTIBUS is a patented Intel bus. Additional copies of this manual or other Intel literature may be obtained from: Intel Corporation Literature Department SV3-3 3065 Bowers Avenue Santa Clara, CA 95051 © INTEL CORPORATION, 1981 AFN-013008-1 Ap·113 Getting Started With Contents the Numeric Data INTRODUCTION Processor iAPX 86,88 Base .............................
    [Show full text]
  • Introduction to Cpu
    microprocessors and microcontrollers - sadri 1 INTRODUCTION TO CPU Mohammad Sadegh Sadri Session 2 Microprocessor Course Isfahan University of Technology Sep., Oct., 2010 microprocessors and microcontrollers - sadri 2 Agenda • Review of the first session • A tour of silicon world! • Basic definition of CPU • Von Neumann Architecture • Example: Basic ARM7 Architecture • A brief detailed explanation of ARM7 Architecture • Hardvard Architecture • Example: TMS320C25 DSP microprocessors and microcontrollers - sadri 3 Agenda (2) • History of CPUs • 4004 • TMS1000 • 8080 • Z80 • Am2901 • 8051 • PIC16 microprocessors and microcontrollers - sadri 4 Von Neumann Architecture • Same Memory • Program • Data • Single Bus microprocessors and microcontrollers - sadri 5 Sample : ARM7T CPU microprocessors and microcontrollers - sadri 6 Harvard Architecture • Separate memories for program and data microprocessors and microcontrollers - sadri 7 TMS320C25 DSP microprocessors and microcontrollers - sadri 8 Silicon Market Revenue Rank Rank Country of 2009/2008 Company (million Market share 2009 2008 origin changes $ USD) Intel 11 USA 32 410 -4.0% 14.1% Corporation Samsung 22 South Korea 17 496 +3.5% 7.6% Electronics Toshiba 33Semiconduc Japan 10 319 -6.9% 4.5% tors Texas 44 USA 9 617 -12.6% 4.2% Instruments STMicroelec 55 FranceItaly 8 510 -17.6% 3.7% tronics 68Qualcomm USA 6 409 -1.1% 2.8% 79Hynix South Korea 6 246 +3.7% 2.7% 812AMD USA 5 207 -4.6% 2.3% Renesas 96 Japan 5 153 -26.6% 2.2% Technology 10 7 Sony Japan 4 468 -35.7% 1.9% microprocessors and microcontrollers
    [Show full text]