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1 V, 1.9 Ghz CM08 Mixers for Wireless Applications 1 V, 1.9 GHz CM08 Mixers for Wireless Applications A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Department of Electrical and Computer Engineering Universi@ of Toronto 2001 O Copyright by Song Ye 2001 The author has granted a non- L'auteur a accordé une Licence non exclusive Licence allowing the exclusive permettant à la National Li'brary of Canada to Bibliothèque nationale du Canaâa de reproduce, loan, distniute or sel reproduire, prêter, distriiuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic fonnats. la forme de microfiche/film, de rep~oductionsur papier ou sur format électronique. The author tetains ownershrp of the L'auteur conserve la propriété du copyright in îhis thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantial extracts fiom it Ni la thèse ni des extraits substantiels may be priuted or othennrise de ceîlexi ne doivent êeimprimés reproduced without the author's ou autremat reproduits sans son p-ssion. autorisation. 1 V, 1.9 GHz CMOS Mixers for Wiless Applications Master of Applied Science, 2000 Song Ye Department of Electricai and Computer Engineering University of Toronto Abstract This thesis deais with the design and implementation of 1 V, 1.9 GHz mixers using CMOS technology for CDMA applications. The use of CMOS ailows the implementation of the mixers on the same chip with the rest of the anaiog and digital circuits economically while achieving high performance. The mixers topologies explored are a dual-gaie mixer and a back-gûte mixer. The duai-gate mixer is designed in a 0.5 um SOI process and the back-gate mixer is designed in a 0.25 um standard bulk CMOS process. Equations describing the nonlinear behavior of the CMOS duai-gate mixer are derived. The anaiysis yields guidelines for improving third-order intermodulation distortion of the mixer. The dual-gate mixer exhibits 1.8 dB conversion gain, -0.8 dBm IIP3 and 9.8 dB noise figure at 1.9 GHz while operating from a 1 V supply with a power consumption of 3 mW and a die area of 1.44 mm2. The back-gate mixer utilizes the inherent lateral bipolar transistor in CMOS. Device simulations were performed to analyze the behavior of the laterai bipolar transistor and extract a madel for it. The characteristic of the transistor were verified through measurements. The mixer circuit only draws 1.3 mW from a 1 V supply. The measurement shows a conversion gain of 6.5 dB. an IIP3 of -3.5 dBm and a noise figure of 9.7 dB at 1.9 GHZ. III= c~parea is 1A mm2. 1 would like to express my sincere gratitude to Professor C. Andre T. Salama for his insightful guidance and invaluable assistance throughout the course of this work. 1 also would like to thank Professors John Long and Wai Tung Ng for their technical advice and help. 1 am indebted to Dr. Koji Yano from Yamanashi University for his technical advice and help in anaiyzing the lateral bipolar in the back-gate mixer. My appreciation extends to al1 the staff and students in the Microelectronic Research Lsiboratory. 1 am specially grateful to Dana Reem for her technical assistance during the chip testing. Thanks go to Anthoula Kampouris, Richard Barber, Milena Khazak, Farhang Vessal, Rick Kubowicz, Dusan Suvakovic, Mehrada Ramezani, Sotoudeh Harnedi-Hagh, Zhixian Jiao, Jeewika Ramezani, Polly Tang for al1 their help. Thanks also to my wonderful friends who made my life in Uoff so pleasant and unforgettable. Especially, 1 would like to express my appreciation to John Ren, Wei An, Heng Jin, Yucai Zhang for valuable discussion both technically and personally, and the rest of my friends: Shuo Chen, Mike Sheng, Hongfei Lu, Franklin Zhao, Edward Chun Keung Yu, 1-Shan Michael Sun for constructive discussions and cheefil chats. My deepest appreciation goes to my parents for their constant support and encouragement. To my mother-in-law for taking care of my son. To my newbom son, Bmce, for keeping quiet while 1 sleep. Finally, to my wife Lang, thank you for your patience, support and love. This work was supported by the Natural Sciences and Engineering Research Councii of Canada, Micronet, CITO, Gennum, Mitel, Norte1 Networks and PMC Sierra. Table of Contents 1.1 Architecture of Wireless Receivers ........................................................................1 1.2 Murer Development ................................................................................................ 3 1.3 Performance Parameters of a Mixer ..................................................................... 4 1.3.1 Conversion Gain ............................................................................................4 1.3.2 Gain Compression ..........................................................................................4 1.3.3 Third-Order Intermodulation Distortion (iP3) ............................................... 6 1.3.4 Noise Figure (NF) .......................................................................................... 8 1.3.5 Port Retum Loss ............................................................................................9 1.3.6 Port Isolation ..................................................................................................9 1.3.7 Power Consurnption ....................................................................................... 9 1.3.8 Summary ...............................................................................................10 1.4 Mixer Topologies ..................................................................................................10 1.5 Why CMOS Mixers .............................................................................................. 12 1.6 Previous Work on CMOS Mixers ....................................................................... 13 1. 7 Objective of the Thesis ......................................................................................... 14 1.8 Outline of the Thesis ............................................................................................. 16 CEAPTER 2 A CMOS on SOI DuabGate Mixer .........................................................20 2.1 Technology Consideration .................................................................................... 19 2.2 Duai-Gate Mixers ..................................................................................................20 2.3 Topology of the Duai-Gate Mixer ........................................................................20 2.4 Anaiysis of the CMOS Duai-Gate Mixer .............................................................. 21 2.4.1 Intermodulation ............................................................................................21 2.4.2 Conversion Gain ..........................................................................................23 2.5 Duai-Gate Mixer Design ....................................................................................... 23 2.5.1 Design Flow ................................................................................................. 23 2.52 Design Considerations ................................................................................23 2.5.3 Complete Design ..........................................................................................27 2.6 Simulation Results ................................................................................................28 2.7 Layout ................................................................................................................... 31 2.8 Experimental Results .......................................................................................... 32 2.8.1 RF Port RemLoss ....................................................................................33 2.8.2 LO Port Return Loss ...................................................................................-34 2.8.3 IF Port Retuni Loss ......................................................................................35 2.8.4 Conversion Gain and PldB .......................................................................... 36 2.8.5 IIP3 ............................................................................................................... 37 2.8.6 Noise Figure .................................................................................................39 2.8.7 LO-IF. LO-RF.RF-IF Isolation ................................................................... 39 2.9 Sumrnary ............................................................................................................... 41 CHAPTER 3 A Back-Gate Mixer Using CMOS Lateral Bipolar Transistor .-.-..... A5 3.1 Introduction ........................................................................................................... 45 3.2 Technology Consideration .................................................................................... 46 3.3 Structure and Operation of the CMOS Lateral Bipolar Transistor ....................... 46 3.4 Topology of the Back-Gate Mixer ................... .. .............................*..........**...-A7 3.5 Device Design ..................................................................................................... ..48 3.5.1 Device Structure ........................................................................................... 48 3.5.2 Device Mode1 ............................................................................................... 50 3.5.3 Experirnental Device Characterization .......................................................
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