2019 IEEE 37th VLSI Test Symposium (VTS)

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Special! Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy, Jayesh Pandey, Sam Jiang

NVIDIA Corp, 2788 San Tomas Expressway, Santa Clara, CA 95051, USA {pavand, myilmaz, msonawane, schadalavada, ssarangi, bbhaskaran, sbajpai, vreddy, jpandey, sajiang}@nvidia.com

Abstract - Safety is one of the crucial features of autonomous Xavier AI SOC and delivers 30 TOPS (Tera Operations Per drive platforms, and semiconductor chips used in these Second) of performance while consuming only 30 watts of architectures must guarantee functional safety aspects mandated by power. It includes various processors for redundant and diverse ISO 26262 standard. To monitor the failures due to field defects, deep learning algorithms. For applications that require ultimate in-system-structural-tests are automatically run during key-on performance, NVIDIA DRIVE AGX Pegasus™ achieves 320 and/or key-off. Upon detection of any permanent defects by the in- TOPS of deep learning with an architecture built on two system-test (IST) architecture, Drive platform responds to achieve NVIDIA Xavier™ processors and two next generation GPUs the fail-safe state of the system. In this paper, we present the IST based on Turing architecture [2]. architecture that helps with achieving highest functional safety levels on the NVIDIA Drive platform. Automotive ICs are screened with high-quality test methods to achieve near-zero DPPM (Defective Parts Per Keywords— automotive, functional safety, ISO 26262, in- Million). Even with such high standards of testing, there can be system-test, MBIST, LBIST, ATPG, power, permanent faults reliability defects that will manifest during the in-system field operation due to environmental or operating conditions [3]. I. INTRODUCTION The ISO 26262 standard [4] defines functional safety for all The design complexity of SOCs (System-On-Chip) and electronic and electrical equipment used in automotive safety- GPUs (Graphic Processing Unit) used in Autonomous driving related systems. These functional safety features form an applications is on a steady rise. Companies are moving to integral part of each automotive product development phase. lower semiconductor technology nodes to meet the high- ISO 26262 also defines the various ASIL (Automotive Safety performance requirements of these mission critical Integrity Level) standards applicable to the lifecycle of these applications. These SOC and GPU chips are tested during systems. Different ASIL levels (A, B, C, and D) have different production testing to screen for manufacturing defects and only test coverage targets, with ASIL-D being the most stringent known good die are used on system boards designed for drive among these and requiring the highest test coverage. platform applications. NVIDIA ICs used in automotive applications have built-in Automotive drive platform applications are considered functional safety mechanisms such as ECC or functional highly safety critical [1] and any failure of the integrated redundancy. IST supplements these safety mechanisms to circuits (ICs) used in these systems could be life threatening. achieve the highest possible ASIL level for permanent fault NVIDIA Drive AGX platform (Fig. 1) is architected from the coverage targets. ground up for safety. It is an AI (Artificial Intelligence) super computer that can run an array of deep neural networks IST involves execution of structural ATPG (Automatic simultaneously and is designed to safely handle highly Test Pattern Generation) vectors, i.e., deterministic scan automated and fully autonomous driving. Drive AGX platform compression and Logic Built-In Self-Test (LBIST), and a has different configurations that can support various comprehensive set of MBIST (Memory Built-In Self-Test) performance needs. Drive AGX Xavier™ includes a single algorithms during key-on and/or key-off to determine a pass or a fail status. IST can cover all fault models applicable to lower geometry FinFET technologies. The challenge was to translate the execution of these vectors into a fully self-contained functional feature that could be repeatedly used in an automotive system for the life time of the vehicle within the test-time and power budgets. In this paper, we present details of the IST operation and challenges we had to overcome. Section II lists goals of IST. High-level IST architecture is presented in Section III. Section IV includes the challenges we faced and corresponding solutions. We conclude the paper with silicon results and final Fig. 1. NVIDIA Drive AGX Pegasus™ Platform remarks.

978-1-7281-1170-4/19/$31.00 ©2019 IEEE !

II. GOALS The! primary goals of IST architecture can be categorized as follows: • High quality test: To achieve the highest ASIL safety level, the design under test (DUT) needs to have a very high permanent test coverage. Additionally, we expect that comprehensive set of fault models needs to be supported by test to detect lower geometry FinFET design defects [5][6][7]. • Low latency: The high-quality test patterns are quantified by highest test coverage achieved with shortest possible test time and smallest test data volume. • Architecture flexibility: The architecture should be fully scalable for varied clock frequencies and data rates to adapt to power, storage, and latency requirements. It should also support different design configurations. • TDP (Thermal Design Power) budget: We need to make sure we stay within the limits of the functional TDP during IST execution. • Debug and diagnosis: The architecture should support all modes of debug and diagnosis and provide traceability for field returns.

III. HIGH LEVEL IST ARCHITECTURE The IST architecture enables structural testing of a complex SOC system to detect permanent faults in the field. It can be used for supplementing functional safety mechanisms for permanent fault coverage goals as specified in ISO 26262 [4]. It is fully scalable and can meet the various requirements over the life-cycle of the product. IST supports key-on and key-off testing, updating test configurations and their application sequence, and targeting comprehensive fault models under different test conditions, e.g voltage and clock frequencies. The scheme also maintains a high level of in-field diagnostic granularity of scan and MBIST test patterns. This architecture is not limited to the in-field application of test patterns. It can also be used for System Level Test (SLT) to screen for defects to further improve test quality. For example, it can help in bridging the gap between ATE environment and the platform specific operating conditions. IST uses a combination of hardware and software components to test a Xavier SOC standalone and/or a discrete Turing GPU paired with Xavier SOC. Fig. 2 shows an overview of IST architecture where test data and results are stored off-chip in the eMMC (Embedded Multi-Media Card) flash memory on the platform. The eMMC memory size requirements are based on desired test-quality and the cost of the platform. For the DRIVE-AGX platforms, the test-data for Fig. 2. In-System Test Architecture the Turing dGPU will also be stored in the eMMC flash memory which is connected to the Xavier SOC. The data will For IST, production ATE test patterns should be translated be transported from the Xavier SOC to the Turing over PCIe. into a packet format that can be stored on eMMC memory, The hardware (HW) controller has a direct communication then fetched and decoded by HW controllers on chip. Test data path with the flash memory. application during production testing is from primary pins of

! the SOC and/or GPU using ATE platforms. The test data Our manufacturing test programs ensure that defective parts application during IST is enabled by intercepting the are not shipped to customers, and the design-for-testability multiplexers! inside the IP being tested. Customized software (DFT) structures we insert throughout the chip ensure that tools were developed to create and store IST test programs on these tests are of the highest quality with quantifiable coverage eMMC memory. and low latency. The challenge was to translate this expertise of manufacturing testing into a fully self-contained functional IST HW controllers on Xavier and Turing communicate feature that could exercise the same high-quality structural tests with various on-chip as well as platform components to in an automotive system. Furthermore, IST needs to run these execute the tests utilizing the IEEE 1500, Scan compression tests while a subset of the logic stays functional. [8][9], XLBIST [10], and MBIST systems on the chip. The HW controllers are programmed via IEEE 1500 as well as via software registers. The controllers can handle platform A. Test-Data and Test-Latency Limitations interrupts, e.g., thermal interrupts, and power cycling to meet The key-on and key-off application of IST mandates a very the performance and latency requirements specified for a given low test-latency relative to ATE tests. Furthermore, external system. memory requirements should be minimized to reduce platform cost. Based on the request to execute IST either during key-on or key-off, the system software configures the chip to platform One of the first options for in-field testing is BIST specific operating conditions, e.g. clock frequencies, power & mechanisms: LBIST and MBIST. MBIST has a proven track voltage settings, coverage target. The testing conditions and record of getting comprehensive coverage of memory test application sequence is flexible and can be updated over structures with low test latency, whereas for LBIST, we cannot the product life cycle. tell the same. The XLBIST test patterns require minimal test- data, but these non-deterministic patterns, in general, do not The high-level IST operational sequence is illustrated in yield high test coverage on complex SOCs, especially under Fig. 3. Custom designed HW controllers execute MBIST, constraints of low latency and strict power budgets. The ATPG/XLBIST tests based on the test data packets fetched deterministic ATPG (SEQ+) [8][9] test patterns can achieve from the eMMC and store the results back into eMMC for higher test coverage under the same constraints. However, the processing by system software. Once IST is completed, the amount of test data requirement can be prohibitive for in-field HW controller triggers a complete platform shutdown. System applications. software reads the results from eMMC at the next platform boot and takes necessary action. If on-chip execution of Test latency can be reduced by running scan shift at higher planned tests fail, HW controllers are designed to unload frequencies. However, difficulty of timing very fast scan shift enough details, so that the cause of the failure can be paths and increased test power, limits the usage of this option. determined using debug and diagnosis software, which is part Regardless of whether we use sequential hardware of post-production support. compression or LBIST, Xs are always problematic for DFT. Our analysis on earlier chips showed that by eliminating all Xs, IV. CHALLENGES we can save up to 70% scan compression test-time (latency) Drive AGX platforms are one of the most advanced and test-data, while also increasing test-coverage to near systems used for automotive applications to date. Xavier SOC perfect levels [11]. and Turing GPU are among the largest ICs available today. The best X-elimination strategy is to ensure that there are Ensuring that there are no faults occurring in this hardware no X-leaks in the post synthesis design. This means that the during the years long lifetime of an automotive system under design is fixed for as many X-leaks in the RTL as possible. all kinds of environmental conditions and usage is no easy task. Post-synthesis X-clamping was only used for a few corner cases because of the timing impact on functional logic.

Power on/off Request DUT Power controller Thermal Sensors We developed a software that automated X-source finding and pinpointed all X sources in the RTL. This quick feedback

Cold Boot Prepare for IST Configure DUT is critical for achieving an X-free design within project for IST timelines. Once an X source is found, RTL owners reviewed

Normal Operation Configure safe results and used automated DFT tools to fix those in the RTL. (including IST result state IO

Check) Further test-optimization was achieved by using test-point (TP) Prepare for for PrepareIST OK insertion and ATPG tool specific enhancements. Setup Power Rails Configure Thermal IST Execution Request The amount of test-time and test-data savings we achieved Execute IST by these optimizations allowed us to bring down IST latency

Shutdown and test-data volume to within the automotive platform budgets, even when aggressive test-power solutions are used. Power Removed

DUT is OFF B. Test-Power Constraints Fig. 3. In-System-Test Functional to Test Mode Sequence One of the primary challenges for IST was to fit the high- toggle structural patterns into the power-supply noise (PSN),

! peak/average power, and thermal budgets of the product. The system-level platform and Power Distribution Network (PDN) Xavier System Platform are designed! for functional use-cases. Typically, the amount of JTAG Mask simultaneous switching activity is higher for structural patterns.

Without any low power features, the latency would be the JTAG shortest, but PSN would be high, resulting in higher operating Val 1 voltage and increased power. It was a challenge to ensure that SW REG Scannable the IST patterns were within the power budget and robust Logic 0 across all Process-Voltage-Temperature (PVT) variations for 0/1 the given system-level platform design. Another key learning XXXX COMPONENT 1 from pre-silicon power estimates was that the total power for IST patterns is dominated by leakage power, which led to a IST new solution. Isolated Functional COMPONENT 2 To constrain the amount of simultaneous switching during Unit scan capture, a clock-gating based hardware low-power capture (LPC) controller was used [12]. The allowed power budget is Scannable Logic 1 programmable during ATPG and is decided based on the chip COMPONENT 3 design. LPC was enabled to constrain the amount of toggle 0 during the capture phase of LBIST and SEQ+, that lowered peak power and PSN substantially. Since MBIST patterns also IST Master contribute to high dynamic power and PSN, a similar clock- HW Controller gating scheme was used for MBIST to clock-gate the logic that did not participate in an MBIST operation [13]. Since the time spent during a shift operation is much higher Fig. 4. IO Safe State than the time spent on capture, the shift operation is a contributor to not only to PSN but also to the overall dynamic special handling of the scan chains, scan enable, wrapper power. A shift staggering scheme [14][15] was deployed where boundary register, LPC [12] for these functional units. phase-staggered clocks are applied such that (i) no two The non-functioning IOs (unused during IST operation) neighboring partitions toggle on the same clock edge (local); should be held in a pre defined safe state during IST to prevent (ii) number of flops toggling per edge is balanced (to solve any corruption to the platform components due to random global PSN). toggle from scannable logic. To guarantee that, the system One of the limiting factors for operating voltage for IST is software is expected to program these IOs and their controllers the amount of PSN the DUT is subject to. After PSN is to the required state before transitioning into the IST mode, lowered to its most optimized value, the system is e.g., programming the unused IO interfaces to a safe or idle characterized for the overall power. Since leakage power was a state, flushing all pending transactions from/to IO peripherals dominant portion at the given operating voltage, power gating which are inactive during IST. Once we transition into IST was used as follows – (i) all SRAMs were power-gated during mode, JTAG will override all the IO control signals using the scan tests; (ii) the blocks are dynamically power-gated after same software programming values so that the IOs continue to testing. remain in the pre defined safe state, as shown in Fig. 4. Depending on the board configuration, some of the IOs may C. Isolation Methodology need to drive a pulse waveform to be in a safe state. This is ensured by isolating the respective functional units from scan. During IST operation, the logic that is part of IST backbone Other pads may need a direct hardware control from the IST should remain functional and fully isolated while the rest of the controller for a reliable system operation. DUT is tested. Special care must be taken for IST backbone with respect to unit interfaces, clock and reset signals, and test signals, e.g., scan enable, LPC, so that these units can be D. RTL Insertion of Scan Backbone Logic screened for manufacturing defects on ATE and remain To address the verification challenges associated with functional in IST. typical ATPG simulations and in order to have a timing friendly design early in the project lifecycle, a new flow was For the units that are supposed to be functional, care must developed, wherein the scan backbone logic along with the be taken to prevent X propagation into unit inputs. At the same compression logic was inserted in the RTL. Post the RTL time, the unit outputs feeding into any scannable logic need to insertion, the gate level insertion was limited to stitching scan be clamped to avoid any X-inference by the ATPG tools. chains and hooking them to the RTL DFT wrappers. Failure to do so will result in reduced coverage and increased pattern count, since the functional unit will be treated as a The RTL DFT wrappers contained dummy scan flops source of X during ATPG. This isolation scheme needs to be between the decompressor and compressor to generate dummy extended to any critical control signals, e.g., clocks, reset. The ATPG patterns that could facilitate the early verification of the scan architecture [8][9] had to be modified to accommodate the coexistence of the IST and the scan backbone logic.

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Fig. 5. DFT RTL Build Flow

To insert DFT structures in RTL, the Scan DFT IPs had to be built with rest of the functional units during regular RTL build (Fig. 5). The Scan DFT IPs are divided mainly into two categories - static and dynamic. Static components are those that are independent of design size and fixed like 1500 register, standard mux-ing logic and scan low power controllers, etc. while compression logic like PRPG, MISR, etc. are dynamic and depend on the number of flops. Fig. 6. ATPG Verification Flow As can be inferred, the dynamic components have dependency on rest of the functional units being built and are IST backbone whereas shift and capture clocks are propagated generated from EDA tools which can be time consuming. To to rest of the logic. minimize the latency of the DFT IP RTL build time, the DFT For the X-injection and X-propagation enabled RTL RTL was split into two parts – online build and offline build. simulations, the existing Synopsys NLP (Native Low Power) During online build, all the static components, top level flow was used as a reference and repurposed to inject X’s on wrappers with fully specified interface and connectivity are clock domains to prove the correctness of the logic under X- generated. After this, the offline build step is introduced which pessimism. To determine the effectiveness of these reads in the built RTL and derives the required data to simulations, a flow was developed to compute and analyze the generate the dynamic components. The dynamic components X-pessimism coverage. are then inserted into the DFT RTL wrappers generated from the online build. The top-level scan interface is fully As part of the verification strategy, in the IST mode, the standardized and pre-determined upfront and doesn’t vary goal was to reuse the ATPG patterns generated for regular across netlist milestones. All the required collaterals to ATE operation. Care was taken to ensure the PI (Primary perform ATPG on the dummy scan flops in the RTL are also Input) constraints always matched between the regular ATE written out. mode and the platform setup used for the IST mode. The goal was to verify that scan patterns generated using ATPG tools E. Verification via the scan backbone logic and stored as memory packets can traverse through all the stages of the IST backbone and execute Verifying this complex isolation scheme and all the corner correctly (Fig. 6). For early verification feedback, as described cases associated with it has been a challenge. A new in the previous section, the APTG patterns were generated for verification strategy and infrastructure was developed to the dummy scan flops in RTL and simulated to verify the new robustly verify this complex feature using several techniques scan DFT IPs along with the IST backbone logic. like X-injection and X-propagation enabled RTL simulations, hybrid (RTL + gate) simulations, formal verification, FPGA, The complete verification of the scan inserted netlists in the and gate level emulation. Separate IST timing and IR-drop presence of the isolation logic is only possible in a gate level analysis were done to ensure coexistence of test and functional simulation. Since gate level simulations are highly memory worlds for the chip operation. The constraints must be intensive and consume significant resources, a different carefully setup such that functional clocks are propagated to approach was adopted, wherein only the target IP contains

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when we run the formal checks specifically tuned for verifying IST logic isolation, only the IST isolated logic ! sequential cells are used as compare points. In addition to that, all formal constraints are removed, except the control signals, i.e., ist_mode, that indicate IST mode of operation. The goal is to verify that once ist_mode is enabled, IST isolated logic behavior is equivalent to RTL design. Fig. 7a shows an example with two flip-flops (before scan insertion) that are supposed to be functional during IST. Actual functional connections on Q and D ports are not included. Two implementations are displayed: Fig. 7b connects scan_enable directly to the SE ports of these flip- flops. This is an incorrect implementation, because these flip- flops will not be isolated during scan shift. Fig. 7c shows the correct implementation, where scan_enable is gated-off with ist_mode signal before it is connected to SE ports. During IST formal verification runs, the implementation in Fig. 7b will fail, because it will not match the golden netlist. On the other hand, the implementation in Fig. 7c will pass because with the constraint ist_mode=1, it will result in equivalent circuits.

F. Architecture Flexibility and Debug & Diagnosis SEQ+ scan compression architecture natively supports various diagnostic resolution levels [8][9], i.e., MISR signature can be unloaded per shift, per pattern, or per test. Furthermore, SEQ+ supports self-test and diagnosis of SEQ+ control structures. The challenge was to design a control structure that enables seamless on-chip usage of these features in the IST application under automotive platform constraints. Architecture flexibility was also needed for test scheduling and hybrid application of ATPG/XLBIST. IST supports serial, concurrent, pseudo-concurrent, and burst application of MBIST, ATPG, XLBIST, or mix of these tests, on SOC and GPUs.

V. SILICON RESULTS

Fig. 7a. Nonscan Netlist The IST feature has been validated successfully in the system. The feature went through a rigorous testing and Fig. 7b. Scan Inserted Netlist – Incorrect Implementation characterization process to ensure a reliable operation for various platform PVT conditions. A thorough analysis was Fig. 7c. Scan Inserted Netlist – Correct Implementation done to make sure the post silicon results matched the pre- silicon goals listed in Section II. synthesized gates while the rest of the DUT is regular RTL (referred to as hybrid simulations). This helped in saving A comprehensive summary of PSN and power significant resources and reduced the turn-around time for measurements for Xavier SOC and Turing GPU are presented simulations. Any coverage gaps that arise due to this approach, in this section. Silicon PSN measurements were recorded using were addressed during gate level emulation. To supplement the on-die probe points. The goal of these measurements was to gate level simulation and emulation effort, formal verification validate the various low power features implemented to reduce was used to check for the equivalence of the IST functional the amount of simultaneous toggle during IST, as described in units between hierarchical synthesized netlist and the flattened Section IV-B. scan inserted netlist. Fig. 8. compares the average system-level power as Special IST formal verification checks were setup and run measured on silicon for the Drive-AGX Platform. On Xavier, to verify the scan isolation done during gate level scan we present data for patterns X1 and X2. X1 includes only low insertion flow. So far, all the IST logic is verified using RTL dynamic power schemes, whereas for the production pattern verification techniques as described in earlier sections. X2, the leakage power reduction schemes were applied as well. Furthermore, RTL is compared to synthesized, but pre-scan As a result, in pattern X2, an additional power reduction of inserted (non-scan) gate level netlist using regular functional 23% is observed against pattern X1. All values are normalized RTL-to-nonscan formal verification runs. Post scan insertion, with respect to pattern X1 for Xavier. For Turing, we compare

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Fig. 8. Average power as measured in silicon

Fig. 10. Test cycle reduction due to multiple optimizations the average power of pattern T1 with the production pattern T2, where both leakage reduction and serialization were used. enhancements (marked as OLD) and after (marked as NEW). The 48% reduction in power was imperative to fit the In each case, the OLD version of the IP is from an earlier chip. functional power budgets for Turing. The NEW version is used in the Pegasus Platform. The OLD In Fig. 9, we compare the low power pattern’s PSN against and NEW versions have almost the same functionality, but the a pattern that was not power optimized (without low power NEW version has a newer and significantly larger design. All features). The chart shows the reduction in PSN for the rails on numbers in this chart are normalized with respect to the OLD Xavier followed by the power rail on Turing. A reduction of version of a given IP. Normalized scan cell counts are shown about 20% to 47% in PSN was observed on Xavier for its on the secondary Y-axis, and it signifies the overall circuit size. respective voltage rails while a 70% reduction was observed on Normalized total test-cycle counts are shown on primary Y- Turing. The % reduction in the Turing die is higher, given the axis, and it represents the overall test-time for a given IP. Test- fact that Turing contains a higher amount of logic on a single cycle is further divided into two groups: XTOL cycles (test rail. All values are normalized with respect to the worst-case cycles wasted for X-tolerance) and useful cycles (useful test pattern without low power features. While targeting high cycles). coverage with the low power patterns, the latency for the As seen in Fig. 10, all IPs have significantly increased in system increased, as expected. Post characterization, the size (i.e., scan cell counts). Assuming all other factors patterns were tuned to ensure that the latency budget was met remained the same, the total test time for a given IP will based on the requirements, while also minimizing average increase proportionally to the number of scan flops. But this power and PSN. This helped with testing the devices at lower assumption was broken due to the aggressive optimizations voltages for better defect detection. that were implemented. IP1, IP2, and IP3 have more than As discussed in Section IV-A, we utilized a set of doubled in size, but the total test-time (i.e., test-cycle count) optimizations to reduce test-time/test-data and further improve was reduced by 25%-60%. For all IPs, the test coverage has test-coverage. In the order of their impact, these optimizations significantly increased to near perfect levels. include X-elimination, test-point insertion, and various ATPG tool enhancements. Fig. 10 summarizes the results of these VI. CONCLUSION efforts and shows a comparison of similar IPs before these The NVIDIA DRIVE-AGX platform is the most advanced automotive platform in the industry today. To productize a new and complex IST architecture was not an easy task, considering the number of challenges that had to be dealt with in both the design space and the verification space. The IST architecture has been designed as an extension of the existing test architecture(s) at NVIDIA, so that it enables consistent approaches for both manufacturing defect screening as well as permanent defect detection for in-field applications. It also has the capability to debug and diagnose the failures or faults caused by permanent defects in the field during the life time of the automotive platforms. The IST architecture can be extended to applications beyond the automotive space, that require periodic in-field testing of the hardware for reliability purposes.

Fig. 9. PSN as measured in silicon

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ACKNOWLEDGMENT [8] Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub We! would like to specifically thank our colleagues across Abdollahian, “Advanced Test Methodology for complex SOCs”, IEEE multiple teams – DFX engineering, clocks and VLSI design, International Test Conference (ITC), 2016 system architecture, silicon solutions group, operations, [9] Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit automotive software, safety, functional verification and Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon emulation, who helped us in productizing IST. We would also E. Colburn, “Flexible scan interface architecture for complex SoCs”, IEEE VLSI Test Symposium (VTS), 2016 like to thank Synopsys for an excellent EDA support. [10] Peter Wohl, Jon Colburn, John Waicukauski, Greg Maston, "XLBIST: X-Tolerant Logic BIST", IEEE International Test Conference (ITC) REFERENCES 2018 [1] Ch. Eychenne, Y. Zorian, “An effective functional safety infrastructure [11] Mahmut Yilmaz, Animesh Khare, Rahul Garg, Mayank Parasrampuria, for system-on-chips”, International Symposium on On-Line Testing and Nitin Yogi, Jaison Kurien, Rahul P R, Shantanu Sarangi, Krishna Rajan, Robust System Design (IOLTS), 2017 “X elimination to improve the quality of scan compression”, International Test Conference (ITC)-India, 2017 [2] NVIDIA Drive AGX Platform, https://developer.nvidia.com/drive [12] Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu, “A clock- [3] Y.-H. Lee, P. J. Liao, K. Joshi, D. S. Huang, "Circuit-based reliability gating based capture power droop reduction methodology for at-speed consideration in FinFET technology", International Symposium on the scan testing”, Design, Automation & Test in Europe (DATE), 2011 Physical and Failure Analysis of Integrated Circuits (IPFA), 2017 [13] Bonita Bhaskaran, Sailendra Chadalavada, Shantanu Sarangi, Nithiin [4] ISO 26262 standard, https://www.iso.org/standard/43464.html Valentine, Venkat Abilash Reddy Nerallapally, Ayub Abdollahian, “At- [5] Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, speed capture global noise reduction & low-power memory test Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, Anja architecture”, IEEE VLSI Test Symposium (VTS), 2017 Fast, "Cell-Aware Test," in IEEE Transactions on Computer-Aided [14] Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Design of Integrated Circuits and Systems, vol. 33, no. 9, pp. 1396- Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, 1409, Sept. 2014. Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha, “Dynamic [6] F. Forero, J. Galliere, M. Renovell and V. Champac, "Analysis of short clocking architecture for concurrent testing and peak power reduction”, defects in FinFET based logic cells," IEEE Latin American Test IEEE VLSI Test Symposium (VTS), 2016 Symposium (LATS), 2017 [15] Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub [7] A. Srivastava, A. D. Singh, V. Singh and K. K. Saluja, "Exploiting path Abdollahian, Kaushik Narayanan, Krishnendu Chakrabarty, Amit delay test generation to develop better TDF tests for small delay Sanghani, “A programmable method for low-power scan shift in SoC defects," IEEE International Test Conference (ITC), 2017 integrated circuits”, IEEE VLSI Test Symposium (VTS), 2016