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Hard Disk Controller: the Disk Drive's Brain and Body

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Hard Disk Controller: the Disk Drive's Brain and Body Hard Disk Controller: the Disk Drive’s Brain and Body James Jeppesen; Walt Allen; Steve Anderson; Michael Pilsl Infineon Technologies; Memory Products, Network and Computer Storage 600 South Airport Road; Suite #205; Longmont, Colorado USA (James.J eppesen; Walt.Allen; Steve.Anderson; Michael.P ilsl) @infineon.c orn Abstract Servo Control, Central Processing Unit (CPU), Buffer Memory, and CPU memory. See Figure 1 for a block Integration of the Hard Disk Controller (HOC) today diagram of a disk drive. has taken on an extensive amount of functionality. From the host interface, error correction code, disk sequencer, 2.1. Host Interface microprocessor(s), servo control logic, buffer controller, to the embedded memory, the HDC has become a true The host interface’s primary function is to provide a system on a chip. Depending on the product, embedded standard protocol for the Disk Drive to talk to a host DRAM is used as bufferingf or data between the host and system. The host system can be anything from a server or media and possibly for storing controller firmware. By PC to a simple peripheral or consumer product--such as a bringing all these blocks into one chip, pin counts can printer or digital camera. There exists a number of distinct be reduced and higher dataflow speeds can be obtained protocols in the disk drive industry for performing this link. by decreasing the interconnect delays. However, the Some of the major interfaces are ATA, SCSI, and Serial challenge for designers is in test and verification of the interfaces. The main driver between selecting which design during development and production. interface to use is cost to performance. The design trend for the host interface is to have multiple interface blocks. 1. Introduction Each block supports a particular host protocol and has a standard back end interface to the rest of the HDC. This Computer mass storage devices once took up an area allows for maximum synergy among designs. Depending about the size of a 2-drawer legal file cabinet back in the on the interface chosen and the performance desired, the 1980’s. A current drive produced for digital cameras is size of the host interface can vary dramatically from a few smaller than a credit card, about the depth of a 3 % inch thousand gates to over a hundred thousand gates. floppy, and holds at least 10 times the data-all at a Currently, the host interface is the only block that is reduced cost. In 1995, a -400 MB drive cost nearly $500. covered by any kind of published industry standard--albeit Now, a 20 GB drive can be bought for only $150. What has many different public standards. These standards define enabled the manufacturers to achieve such changes? One physical transfers, required registers, and command sets. area is system integration. The hard disk controller (HDC) has experienced rapid 2.2. Buffer Controller integration as driven by cost reductions. Moving from a six-chip design, the current HDC solution is one chip. The main function of the buffer controller is to provide Future products will integrate the readwrite channel into arbitration and raw signal control to the bank of buffer the HDC further reducing the total number of parts the memory. This memory can be Static Random Access hard disk drive (HDD) will require to perform its function. Memory ( S U M ) , Dynamic Random Access Memory The paper presented here will look at the current scale of (DRAM), or Embedded memory. Typically the host integration and the testability issues created by this interface, disk sequencer, ECC, and CPU all need access to integration. this buffer memory. The buffer controller, under some priority scheme, will prevent these blocks from colliding 2. HDC Functional Block Description while accessing the memory buffer. This block may also contain logic to help with the automation of moving data to and from the host. The size of this block can vary The Hard Disk Controller today is made up of the depending on the number of memory configurations following common blocks: Host Interface, Buffer supported by a single controller. The system throughput Controller, Disk Sequencer, Error Correction Code (ECC), and performance can be greatly affected by this block. 0-7695-1200-3/01$10.00 Q 2001 IEEE 262 Head Disk Assembly PCB I I ATA, etc. Servo Control 8 Variable Store Motor Control Demodulator Figure 1. Hard disk drive subsystem 2.3. Disk Sequencer the data rate from and to the disk must remain constant. The sequencer is in charge of pulling data from registers, data The main task of the disk sequencer is to oversee and buffers, and the ECC block at precise times in a disk write manage the transfer of data between the disk interface operation, and in charge of sending the NRZ data to the (referred to in this paper as the NRZ pins) and the data correct blocks during a disk read operation. The disk buffer. The term, NRZ, is defined as non-return to zero. sequencer is often referred to as the disk formatter. The NRZ bus has become a normal name for the 8-bit data interface between the read/write channel and the HDC. For 2.4. ECC (Error Correction Code) a disk write operation, the disk sequencer takes user data, appends additional fields such as ECC bytes, and writes In terms of a single function, the ECC is one of the largest out the newly formatted data to the media interface blocks of an HDC controller. This block is responsible for through the NRZ pins. (NRZ is defined as non-return to appending ECC symbols to the user data and also to check zero.) Conversely for a disk read operation, the disk and, if needed, correct the user data before it is returned to sequencer reads formatted data from the NRZ pins and the host. The ECC size is greatly affected by the chosen converts it back into user data that is then sent to the host correction capable of the hardware and the amount of interface. The process is complicated by the fact that disk software intervention required to perform the correction. media has servo wedges written on it that cannot be over Along with ECC syndromes, this block often contains some written by user data. (Servo wedges, typically 50-80 per type of Cyclic Redundancy Check (CRC) function to keep revolution, contain gain control information for the the probability of miscorrection to an acceptably low level. readwrite channel; cylinder/track location information; Current disk drives are specifying a nonrecoverable read and head alignment patterns. The servo wedges are written error of 1 in lOI4 bits read [2]. at the factory by special equipment called, “Servo Writers.”) The user data sometimes must be split on either 2.5. Servo Control side of these servo wedges. The disk sequencer handles the split data fields for both read and write operations. The servo control block has a lot of different definitions Furthermore, since the spinning disk cannot be throttled, depending on the particular implementation. In this paper, 263 the servo block refers to general logic used in aiding the Integration of more and more HDC functional blocks into spinning of the discs and in the positioning of the actuator a single chip is not without issues. While integration can on the disc. It does not refer to the power devices lead to cost savings, if not managed appropriately, it can necessary to drive the spindle motors. This block is lead to cost increases, or even failure of the project. uniquely customized to the particular customer’s strategy As each module was integrated over the years, the for motion control d the Head Disk Assembly (HDA). externally observable connections were no longer available Therefore, it is difficult to standardize and thus lends itself for test. This forced the designer to find alternative methods to an Application Specific Standard Product (ASSP) for testability without adding significant cost to the final strategy. product. The testability issues have different objectives: development tests for the designer to prove function; wafer 2.6. CPU (Central Processing Unit(s)) tests which ensure the die was successfully manufactured; final assembly tests to verify the customer receives a The CPU of the HDC can be implemented in multiple functional part; and fnally a means for the customer to ways. Single %bit, 16-bit, or 32-bit microprocessors and develop and debug application firmware/software on the Digital Signal Processors (DSP) have been used, as well as embedded microprocessor. We will now look at the process combinations of these cores. These cores are used to for developing the product in greater detail and each of the control the overall system or may have a very specific task. testability objectives. The CPU has the highest gate count of all the logic blocks except memory. It is also the most complex from a 3.1. Development Phase simulation and integration standpoint. The development phase sets the objectives for the 2.7. Buffer Memory project. Major concerns include team make-up, features required for the product, and test methodology from both a The buffer memory is used as a temporary storage of producer and customer viewpoint. the user’s data either on its way to the disc or returning to Team make-up has implications on the overall design the host. This memory may also serve as variable storage methodology. If multi-sites are involved in the design of the or even code execution space for the CPU. This memory project, functions must be carefully chosen to streamline the traditionally has been made up of both SRAM and DRAM.
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