RDT64 (Retro Dumb-Terminal) User's Manual
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RETRO DUMB-TERMINAL RDT64-1 CIRCUIT BOARD USER’S MANUAL 2020.11.12 Lucid Technologies http://www.lucidtechnologies.info/ Email: [email protected] Copyright © 2020 by Lucid Technologies All rights reserved The information in this manual has been carefully checked and is believed to be accurate. However, Lucid Technologies makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document. Lucid Technologies reserves the right to make changes in the products contained in this manual in order to improve design or performance and to supply the best possible product. Lucid Technologies assumes no liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. RDT64, Retro Dumb-Terminal 2 CONTENTS 1.0 Introduction 1.1 Specifications 2.0 VGA Terminal Design 2.1 Counting pixels and lines 2.2 Generating the video 2.3 Video color 2.4 Video static RAM 2.5 Keyboard interface 2.6 Host serial port 3.0 Software Description 3.1 Settings 4.0 RDT64-1 Circuit Board Assembly 4.1 Preparation 4.2 Assembly checklist 4.3 Circuit board checkout 5.0 Customization Appendix A RDT64-1 Printed Circuit Board (PCB) Parts List Appendix B RDT64-1 System Parts List Appendix C RS-232 Serial Interface Connector Appendix D PS/2 Keyboard Connector Appendix E VGA Display Connector Appendix F References Appendix G Response to Control Characters from Host Appendix H Response to Escape Sequences from Host Appendix I Character EPROM Appendix J Default Font Appendix K Schematics Appendix L Circuit Board Image RDT64, Retro Dumb-Terminal 3 1.0 Introduction The RDT64 (Retro Dumb-Terminal) is just what the name implies. It is a classic text-only dumb-terminal. But thanks to modern components and programmable logic it packs a lot of functionality into a small package. It contains five programmable chips: two 8-bit PIC microcontrollers, two ATF16V8 generic array logic (GAL) chips, and an EPROM. Several of the ideas for the RDT64 came from the first computer I built, a digital group Z80 and its TVC-64 video card. 1.1 Specifications ! Power " +5 VDC at 300 mA " Coaxial 2.1 mm power jack, center positive ! Serial communications with Host " RS-232 levels " 8 data bits, no parity, 1 stop bit (8N1) " 9 pin, female, DCE connector " Baud rates: 1200, 2400, 4800, 9600. ! Keyboard " Standard PS/2 keyboard ! Display " Standard VGA display ! VGA signal " Modified VGA text mode - 64 characters per line, 25 lines, 1600 characters on screen RDT64, Retro Dumb-Terminal 4 2.0 VGA Terminal Design Anyone who has worked with computer displays knows there is not a single VGA (Video Graphics Array) display format. So called “standard VGA” has an active display area 640 pixels wide by 480 pixels high. DOS text mode VGA is 640 pixels wide by 400 pixels high; 80 characters by 25 lines. The RDT64 has an active area 512 pixels wide by 400 pixels high; 64 characters by 25 lines. The horizontal timing specifications for the Standard, Text mode and RDT64 VGA are shown in Table 2.1 and the accompanying diagram. Table 2.1 Horizontal Timing Specs VGA TYPES “Standard” “Text Mode” RDT64 Horizontal Pixels 640 640 512 Vertical Scan Lines 480 400 400 Horizontal Sync Polarity NEG NEG NEG Pixel Clock (MHZ) 25.175 25.175 20.0 † A = Scan line time (ìs) 31.77 31.77 32.0 B = Sync pulse length (ìs) 3.81 3.81 3.6 C = Back porch (ìs) 1.9 1.9 2.0 D = Active video time (ìs) 25.42 25.42 25.6 E = Front porch (ìs) 0.64 0.64 0.8 ______________________ ________ __________| VIDEO |________| VIDEO (next line) |-C-|----------D-----------|-E-| __ ______________________________ ___________ |___| |___| HSYNC |-B-| |-----------------A----------------| † The ideal clock frequency for the RDT64 is 20.14 MHZ but clock oscillators at that frequency are not available. However, 20 MHZ is only 0.7% below the ideal frequency and well within the synchronization range of VGA monitors. RDT64, Retro Dumb-Terminal 5 The vertical timing specifications for the Standard, Text mode and RDT64 VGA are shown in Table 2.2 and the accompanying diagram. Table 2.2 Vertical Timing Specs VGA TYPES “Standard” “Text Mode” RDT64 Horizontal Pixels 640 640 512 Vertical Scan Lines 480 400 400 Vertical Sync Polarity NEG POS POS Vertical Frequency (Hz) 59.9 70.0 69.6 O = Total frame time (ms) 16.68 14.27 14.37 P = Sync pulse length (ms) 0.06 0.06 0.064 Q = Back porch (ms) 1.05 1.11 1.12 R = Active video time (ms) 15.25 12.71 12.8 S = Front porch (ms) 0.32 0.38 0.384 ______________________ ________ __________| VIDEO |________| VIDEO (next frame) |-Q-|----------R-----------|-S-| __ ______________________________ ___________ |___| |___| VSYNC |-P-| |----------------O-----------------| 2.1 Counting pixels and lines VGA controllers are based on two counters; a horizontal or pixel counter, and a vertical or line counter. The horizontal counter (74HC4040, U11) counts the pixels in each line. Refer to Appendix K for the RDT64 schematics. Programmable logic (ATF16V8, U12) starts and ends the horizontal blanking signal (HBLANK) and the horizontal synchronization signal (HSYNC) at specific values of the pixel count. Figure 2.1 shows the structure of a VGA frame and the signals that define it. Both the horizontal and vertical blanking signals span three sub-parts: the Front Porch, the Sync, and the Back Porch. At the upper-left corner both counters equal zero. As the first scan line is sent to the VGA monitor the pixel counter increases. When the pixel counter equals 512 the HBLANK signal begins and the active (displayed) region of the line ends. When the pixel count equals 528 the HSYNC pulse begins - it ends when the pixel count equals 600. Finally, RDT64, Retro Dumb-Terminal 6 when the pixel count reaches 640, the pixel counter is reset to zero, and the line counter is incremented. Note that the HBLANK signal does not go to the VGA monitor, it is used to disable the video output of the RDT64. Figure 2.1 Diagram of VGA frame timing. In a similar fashion, the vertical counter (74HC4040, U6) counts the scan lines in each screen. Programmable logic (ATF16V8, U7) starts and ends the vertical blanking signal (VBLANK) and the vertical synchronization signal (VSYNC) at specific values of the line count. When the line counter equals 400 the VBLANK signal begins and the active (displayed) region of the frame ends. When the line count equals 412 the VSYNC pulse begins - it ends when the line count equals 414. Finally, the line counter is reset to zero, when the line count reaches 449. Note that the VBLANK signal does not go to the VGA monitor, it is used to disable the video output of the RDT64. The HBLANK and VBLANK signals are OR’ed together in U7 to produce the BLANK signal. BLANK is used to gate the Red, Green and Blue video signals to the VGA connector (J3). RDT64, Retro Dumb-Terminal 7 2.2 Generating the video The ASCII code for each of the 1600 characters on the screen are stored sequentially in the 6116 (2k x 8) SRAM chip (U5) and the pixel map for each of the 256 possible ASCII codes is stored in the 2764 (8k x 8) EPROM (U4). See Appendix I for details on the character EPROM. The character EPROM stores a 16 x 8 pixel character map for each ASCII code. Thus, each ASCII character occupies 16 addresses which are the 16 rows, or scan lines, in each character. Let’s look at what happens at the start of a new frame - where the pixel and line counters both equal zero. The eleven address inputs of the SRAM are controlled by the counters; pixel count bits 3 to 8 (PQ3-PQ8) connect to A0-A5 respectively. These six bits count the 64 (0-63) characters in each line. Line count bits 4 to 8 (LQ4-LQ8) connect to A6-A10 respectively. These 5 bits are the character lines; each character line is composed of 16 scan lines. So, for the start of the first line, SRAM A0-A10 are all zero and the SRAM will output the ASCII code for the first character. We’ll deal with how that ASCII code gets into the SRAM later. The 8-bit ASCII value from the SRAM connects to A4-A11 of the character EPROM. A0- A3 are connected to line count bits LQ0-LQ3 respectively. Essentially A4-A11 select the ASCII character and A0-A3 select the row (scan line) in that character’s map; 0000 is the top row and 1111 is the bottom. The eight bits in the selected character row appear at the EPROM output and are connected to the parallel data inputs of the 74HC165 parallel-to-serial shift register (U3). The data is loaded into the shift register by the parallel load (PLD\) signal from U12. PLD\ pulses on every eighth bit of the 20 MHZ clock while an inverted clock signal clocks the bits out of the serial shift register. These serialized bits are the PIXELS seen on the VGA monitor. At the end of the horizontal line, following the Back Porch, U12 pulses PQ_CLR which resets the pixel counter and increments the line counter. The process repeats but this time LQ0- LQ3 is 0001 so the character EPROM will output the second row in the character map.