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Analysis and Design of Java Compression Offload on the IBM Hybrid Platform
Analysis and Design of Java Compression Offload on the IBM Hybrid Platform Thesis Wilhelm-Schickard-Institute for Informatics Eberhard-Karls-University Tübingen Author: Huiyan Roy Gartenstr. 11 72213 Altensteig Email: [email protected] 31.07.2008 Supervisor (University Tübingen) Supervisor (IBM Deutschland Entwicklung GmbH) Prof. Dr. Wilhelm Spruth Roland Seiffert, Jochen Roth Wilhelm-Schickard-Institut for Computer Science IBM Systems & Technology Group Technical Informatics Systems Software Development Sand 13 Schönaicher Str. 220, 72076 Tübingen 71032 Böblingen Germany Germany Hiermit erkläre ich, dass ich die vorliegende Arbeit selbständig und nur mit den angegebenen Hilfsmitteln verfasst habe und alle verwendeten Inhalte aus anderen Quellen als solche kenntlich gemacht habe. I hereby declare that the work presented in this thesis has been conducted independently and without any inappropriate support and that all sources of information, be it experimental or intellectual, are aptly referenced. Tübingen, 31st July, 2008 __________________________ Signature 2 Acknowledgment Acknowledgment First and foremost, I wish to express my deep appreciation and gratitude to Prof. Dr. Wolfgang Rosenstiel, Prof. Dr. Wilhelm G. Spruth and Dr. Peter Hans Roth for making it possible for me to work on this interesting and challenging thesis. Without their dedication, conviction, passion and steadfastness in bringing an extensive cooperation between the lab and University Tübingen into reality, this project wouldn't have come about. I wish this thesis to symbolize the fruit of their efforts. I would like to express my sincere thanks to the IBM supervisors Roland Seiffert and Jochen Roth for mentoring, for giving guidance and sharing ideas that were so precious to me. -
Inside IBM EDA: Fifty Years of Innovation, Photo List; 2011
Introduction 1) IBM’s Copper wiring Microscope photo of IBM’s Copper wiring on CU-11 ASIC 130nm technology 2) POWER5 - Power5 Chip Die : Date added: 2005-10-25 IBM introduces POWER5, the world's most advanced microprocessor. POWER5 will be the "brain" of a new line of powerful computer systems that will be introduced in 2004. 3) SOC Picture Cover of the IBM Journal of Research and Development, Vol 46 No. 6 Nov. 2002. 4) Animation of Power Grid Simulation Global clock networks provide the heartbeat that synchronizes operations on a processor chip. This movie visualizes the voltages and currents in the POWER6 clock network with two processor cores operating at 5 GHz, slowed down about 20 billion times for the human eye. The high speed clock signal is generated in the center of the chip, and takes more than two clock cycles traveling through wires near the speed of light to reach everywhere in both cores. The rising and falling voltages in each wire and buffer are clearly shown, with larger currents displayed using wider widths and hotter colors. Wires are simulated as transmission lines, including overshoots above and below the yellow box representing the power supply. Buffers appear as vertical cones, since their output currents are larger than their input currents. Animation by Philip Restle Reference: "The Physical Design of the POWER6 Microprocessor," Joshua Friedrich, Bradley McCredie, Norman James, Bill Huott, Brian Curran, Eric Fluhr, Gauray Mittal, Eddie Chan, Yuen Chan, Donald Plass, Sam Chu, Hung Le, Leo Clark, John Ripley, Scott Taylor, Jack DiLullo, Mary Lanzerotti, Proceedings of the International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. -
Industrievortrag, IBM Deutschland Entwicklung
IBM Deutschland Entwicklung GmbH Industrievortrag, IBM Deutschland Entwicklung DFG Kolloquium "Rekonfigurierbare Rechensysteme“ TU München, 27.05.2008 29.05.2008 © 2008 IBM Corporation IBM Deutschland Entwicklung Agenda Überblick: IBM Entwicklungslabor in Böblingen IT-Themen der Zukunft Cell/B.E. – die Basis für zukunftsorientierte Konzepte – Prozessor – Systeme 29.05.2008 2 © 2008 IBM Corporation IBM Deutschland Entwicklung Geschichte: 1952 - 1990 • Einzug ins Labor Schönaich • S/370 auf CMOS (1988) • Druckerentwicklung • Unix auf Mainframe • SW für S/360 (1962) • Mitarbeiter: 1800 • Halbleiter und ICs 1960 • Mitarbeiter: 100 1980 1952 1970 1990 • Gründung des • Speicherchips 2048 Bit • Testsysteme Entwicklungszentrums • Logik Chips • Datenbank Tools • Lochkartenmaschinen • DOS/VSE für IBM S/370 • CMOS Prozessoren • Mitarbeiter: 7 • Mitarbeiter:1500 • Mainframe Firmware • Mitarbeiter: 1800 29.05.2008 3 © 2008 IBM Corporation IBM Deutschland Entwicklung Geschichte: 1990 - 2007 • IBM WebSphere Portal Server • Process Server • IBM Software Produkte • Cell Prozessor • Linux auf zSeries • Cell Blade-Prototype • ASIC und Prozessor Design • Mitarbeiter: 1800 • Mitarbeiter: 1800 2000 2005 1998 2003 2007 • MQ Workflow • 50 Jahre IBM • Gründung des • Weltweit leistungsstärkster Entwicklung in Kompetenzzentrums und schnellster CMOS – Deutschland für virtuelle Welten und Mikroprozessor (1GHz) • Middleware & HW Web 2.0 • Mitarbeiter: 1800 Portfolio • Mitarbeiter: 1800 • Services • Mitarbeiter: 1800 29.05.2008 4 © 2008 IBM Corporation IBM Deutschland -
Multicore Session IBM (20080513) Final
Next Generation Computing Systems パネル討論:新時代におけるマルチコア戦略 Multicore:Multicore: anan IBMIBM’’ss PerspectivePerspective May 13, 2008 Toshi Sanuki, Ph.D. Next Generation Computing Systems Yamato Laboratory, IBM-Japan 2008-05-13 for IEICE-ICD & IPSJ-ARC © 2008 IBM Corporation Next Generation Computing Systems Key Industry Trends More transistors and slower clocks mean multicore designs and more parallelism required Thicker “memory wall” means that communication efficiency will be even more essential Limitations of commodity processors will further increase heterogeneity and system complexity Source: Jack Dongarra, et al, “The Impact of Multicore on Computational Science Software” http://www.ctwatch.org/quarterly/articles/2007/02/the-impact-of-multicore-on-computational-science-software/1/ 2 2008-05-13 for IEICE-ICD & IPSJ-ARC © 2008 IBM Corporation Next Generation Computing Systems Example of IBM’s Multicore Processors POWER5 POWER6 Z10 EC PU BlueGene/P Xbox360 CPU Cell/B.E. Technology 130nm 65nm 65nm 90nm 90nm 90nm (1st Gen) Die Size (mm2) 389 341 465 169 165 235 Transistor (M) 250 790 994 208 168 241 ISA Type Homogeneous Homogeneous Homogeneous Homogeneous Homogeneous Heterogeneous Cores/Chip 2 2 4 4 3 9 (1PPE+8SPE) Threads/Core 2 2 1 1 2 PPE:2 / SPE:1 L1 Cache (KB) I:64, D:32 I:64, D:64 /core I:64, D:128 I:32, D:32 I:32, D:32 /core PPE:I/D: 32 L1.5: 3,072 /PU /core SPE: LS 256 L2 Cache (MB) 1.9 (Shared) 8 (4/Core) 48 / Book 0.002 / Chip 1 (Shared) PPE: 0.5 L3 Cache (MB) 32 (External) 32 (External) ~352G /Book 8 (Shared) -- -- Clock (GHz) 1.9 - 2.3 >5.0 4.4 0.85 3.2 >3.2 Target System General Purpose Servers Workload Optimized Systems 3 2008-05-13 for IEICE-ICD & IPSJ-ARC © 2008 IBM Corporation Next Generation Computing Systems Momentum for Heterogeneity Mixed compute power, ISA, etc. -
Cloud Computing Contents
Cloud Computing Contents 1 Cloud computing 1 1.1 Overview ............................................... 1 1.2 History of cloud computing ...................................... 1 1.2.1 Origin of the term ....................................... 1 1.2.2 The 1950s ........................................... 2 1.2.3 The 1990s ........................................... 2 1.3 Similar concepts ............................................ 2 1.4 Characteristics ............................................. 3 1.5 Service models ............................................ 4 1.5.1 Infrastructure as a service (IaaS) ............................... 5 1.5.2 Platform as a service (PaaS) ................................. 5 1.5.3 Software as a service (SaaS) ................................. 5 1.6 Cloud clients .............................................. 5 1.7 Deployment models .......................................... 6 1.7.1 Private cloud ......................................... 6 1.7.2 Public cloud .......................................... 6 1.7.3 Hybrid cloud ......................................... 6 1.7.4 Others ............................................. 7 1.8 Architecture .............................................. 7 1.8.1 Cloud engineering ....................................... 7 1.9 Security and privacy .......................................... 7 1.10 The future ............................................... 8 1.11 See also ................................................ 8 1.12 References ..............................................