DOCSLIB.ORG

VLSI Circuit Design Methodology Demystified Ffirs.Qxd 10/11/2007 9:07 AM Page Ii

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
VLSI Circuit Design Methodology Demystified Ffirs.Qxd 10/11/2007 9:07 AM Page Ii ffirs.qxd 10/11/2007 9:07 AM Page i VLSI Circuit Design Methodology Demystified ffirs.qxd 10/11/2007 9:07 AM Page ii IEEE Press 445 Hoes Lane Piscataway, NJ 08854 IEEE Press Editorial Board Mohamed E. El-Hawary, Editor in Chief R. Abari T. Chen R. J. Herrick S. Basu T. G. Croda S. V. Kartalopoulos A. Chatterjee S. Farshchi M. S. Newman B. M. Hammerli Kenneth Moore, Director of IEEE Book and Information Services (BIS) Catherine Faduska, Senior Acquisitions Editor Jeanne Audino, Project Editor Technical Reviewers Poras T. Balsara, University of Texas at Dallas Peggy Ping Gui, Southern Methodist University Gabriele Manganaro, National Semiconductor Corp. Andrew Marshall, Texas Instruments, Inc. ffirs.qxd 10/11/2007 9:07 AM Page iii VLSI Circuit Design Methodology Demystified A Conceptual Taxonomy Liming Xiu IEEE PRESS WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION ffirs.qxd 10/11/2007 9:07 AM Page iv Copyright © 2008 by the Institute of Electrical and Electronics Engineers, Inc. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic format. For information about Wiley products, visit our web site at www.wiley.com. Wiley Bicentennial Logo: Richard J. Pacifico Library of Congress Cataloging-in-Publication Data is available. ISBN 978-0-470-12742-1 Printed in the United States of America. 10987654321 ffirs.qxd 10/11/2007 9:07 AM Page v To my wife, Zhihong, my daughters, Katherine and Helen, and my parents, Zunxin and Zhengfeng ftoc.qxd 10/11/2007 9:08 AM Page vii Contents Foreword xi Richard Templeton Foreword xiii Hans Stork Preface xv Acknowledgments xvii CHAPTER 1 THE BIG PICTURE 1 1. What is a chip? 1 2. What are the requirements of a successful chip design? 3 3. What are the challenges in today’s very deep submicron 4 (VDSM), multimillion gate designs? 4. What major process technologies are used in today’s design 5 environment? 5. What are the goals of new chip design? 8 6. What are the major approaches of today’s very large scale 9 integration (VLSI) circuit design practices? 7. What is standard cell-based, application-specific integrated 11 circuit (ASIC) design methodology? 8. What is the system-on-chip (SoC) approach? 12 9. What are the driving forces behind the SoC trend? 15 10. What are the major tasks in developing a SoC chip from 15 concept to silicon? 11. What are the major costs of developing a chip? 16 CHAPTER 2 THE BASICS OF THE CMOS PROCESS 17 AND DEVICES 12. What are the major process steps in building MOSFET 17 transistors? vii ftoc.qxd 10/11/2007 9:08 AM Page viii viii CONTENTS 13. What are the two types of MOSFET transistors? 19 14. What are base layers and metal layers? 20 15. What are wafers and dies? 24 16. What is semiconductor lithography? 28 17. What is a package? 33 CHAPTER 3 THE CHALLENGES IN VLSI CIRCUIT DESIGN 41 18. What is the role of functional verification in the IC 41 design process? 19. What are some of the design integrity issues? 44 20. What is design for testability? 46 21. Why is reducing the chip’s power consumption so important? 48 22. What are some of the challenges in chip packaging? 49 23. What are the advantages of design reuse? 50 24. What is hardware/software co-design? 51 25. Why is the clock so important? 54 26. What is the leakage current problem? 57 27. What is design for manufacturability? 60 28. What is chip reliability? 62 29. What is analog integration in the digital environment? 65 30. What is the role of EDA tools in IC design? 67 31. What is the role of the embedded processor in the SoC 69 environment? CHAPTER 4 CELL-BASED ASIC DESIGN METHODOLOGY 73 32. What are the major tasks and personnel required in a chip 73 design project? 33. What are the major steps in ASIC chip construction? 74 34. What is the ASIC design flow? 75 35. What are the two major aspects of ASIC design flow? 77 36. What are the characteristics of good design flow? 80 37. What is the role of market research in an ASIC project? 81 38. What is the optimal solution of an ASIC project? 82 39. What is system-level study of a project? 84 40. What are the approaches for verifying design at the 85 system level? 41. What is register-transfer-level (RTL) system-level description? 86 42. What are methods of verifying design at the register-transfer- 87 level? 43. What is a test bench? 88 44. What is code coverage? 89 ftoc.qxd 10/11/2007 9:08 AM Page ix CONTENTS ix 45. What is functional coverage? 89 46. What is bug rate convergence? 90 47. What is design planning? 91 48. What are hard macro and soft macro? 92 49. What is hardware description language (HDL)? 92 50. What is register-transfer-level (RTL) description of hardware? 93 51. What is standard cell? What are the differences among standard 94 cell, gate-array, and sea-of-gate approaches? 52. What is an ASIC library? 103 53. What is logic synthesis? 105 54. What are the optimization targets of logic synthesis? 106 55. What is schematic or netlist? 107 56. What is the gate count of a design? 111 57. What is the purpose of test insertion during logic synthesis? 111 58. What is the most commonly used model in VLSI circuit testing? 112 59. What are controllability and observability in a digital circuit? 114 60. What is a testable circuit? 115 61. What is the aim of scan insertion? 116 62. What is fault coverage? What is defect part per million (DPPM)? 117 63. Why is design for testability important for a product’s 119 financial success? 64. What is chip power usage analysis? 120 65. What are the major components of CMOS power consumption? 121 66. What is power optimization? 123 67. What is VLSI physical design? 123 68. What are the problems that make VLSI physical design so 124 challenging? 69. What is floorplanning? 128 70. What is the placement process? 131 71. What is the routing process? 133 72. What is a power network? 135 73. What is clock distribution? 139 74. What are the key requirements for constructing a clock tree? 143 75. What is the difference between time skew and length skew in a 145 clock tree? 76. What is scan chain? 149 77. What is scan chain reordering? 151 78. What is parasitic extraction? 152 79. What is delay calculation? 155 80. What is back annotation? 156 81. What kind of signal integrity problems do place and route 156 ftoc.qxd 10/11/2007 9:08 AM Page x x CONTENTS tools handle? 82. What is cross-talk delay? 157 83. What is cross-talk noise? 158 84. What is IR drop? 159 85. What are the major netlist formats for design representation? 162 86. What is gate-level logic verification before tapeout? 162 87. What is equivalence check? 163 88. What is timing verification? 164 89. What is design constraint? 165 90. What is static timing analysis (STA)? 165 91. What is simulation approach on timing verification? 169 92. What is the logical-effort-based timing closure approach? 173 93. What is physical verification? 178 94. What are design rule check (DRC), design verification (DV), 179 and geometry verification (GV)? 95. What is schematic verification (SV) or layout versus 181 schematic (LVS)? 96. What is automatic test pattern generation (ATPG)? 182 97. What is tapeout? 184 98. What is yield? 184 99. What are the qualities of a good IC implementation designer? 187 Conclusion 189 Acronyms 191 Bibliography 195 Index 199 fbetw.qxd 10/11/2007 9:10 AM Page xi Foreword Richard Templeton President and CEO Texas Instruments, Inc.
Load more

Recommended publications
  • Electronic Circuit Design and Component Selecjon
    Electronic circuit design and component selec2on Nan-Wei Gong MIT Media Lab MAS.S63: Design for DIY Manufacturing Goal for today’s lecture • How to pick up components for your project • Rule of thumb for PCB design • SuggesMons for PCB layout and manufacturing • Soldering and de-soldering basics • Small - medium quanMty electronics project producMon • Homework : Design a PCB for your project with a BOM (bill of materials) and esMmate the cost for making 10 | 50 |100 (PCB manufacturing + assembly + components) Design Process Component Test Circuit Selec2on PCB Design Component PCB Placement Manufacturing Design Process Module Test Circuit Selec2on PCB Design Component PCB Placement Manufacturing Design Process • Test circuit – bread boarding/ buy development tools (breakout boards) / simulaon • Component Selecon– spec / size / availability (inventory! Need 10% more parts for pick and place machine) • PCB Design– power/ground, signal traces, trace width, test points / extra via, pads / mount holes, big before small • PCB Manufacturing – price-Mme trade-off/ • Place Components – first step (check power/ground) -- work flow Test Circuit Construc2on Breadboard + through hole components + Breakout boards Breakout boards, surcoards + hookup wires Surcoard : surface-mount to through hole Dual in-line (DIP) packaging hap://www.beldynsys.com/cc521.htm Source : hap://en.wikipedia.org/wiki/File:Breadboard_counter.jpg Development Boards – good reference for circuit design and component selec2on SomeMmes, it can be cheaper to pair your design with a development
    [Show full text]
  • Analog Integrated Circuit Design, 2Nd Edition
    ffirs.fm Page iv Thursday, October 27, 2011 11:41 AM ffirs.fm Page i Thursday, October 27, 2011 11:41 AM ANALOG INTEGRATED CIRCUIT DESIGN Tony Chan Carusone David A. Johns Kenneth W. Martin John Wiley & Sons, Inc. ffirs.fm Page ii Thursday, October 27, 2011 11:41 AM VP and Publisher Don Fowley Associate Publisher Dan Sayre Editorial Assistant Charlotte Cerf Senior Marketing Manager Christopher Ruel Senior Production Manager Janis Soo Senior Production Editor Joyce Poh This book was set in 9.5/11.5 Times New Roman PSMT by MPS Limited, a Macmillan Company, and printed and bound by RRD Von Hoffman. The cover was printed by RRD Von Hoffman. This book is printed on acid free paper. Founded in 1807, John Wiley & Sons, Inc. has been a valued source of knowledge and understanding for more than 200 years, helping people around the world meet their needs and fulfill their aspirations. Our company is built on a foundation of principles that include responsibility to the communities we serve and where we live and work. In 2008, we launched a Corporate Citizenship Initiative, a global effort to address the environmental, social, economic, and ethical challenges we face in our business. Among the issues we are addressing are carbon impact, paper specifications and procurement, ethical conduct within our business and among our vendors, and community and charitable support. For more information, please visit our website: www.wiley.com/go/citizenship. Copyright © 2012 John Wiley & Sons, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc.
    [Show full text]
  • A General CAD Concept and Design Framework Architecture for Integrated Microsystems^
    Transactions on the Built Environment vol 12, © 1995 WIT Press, www.witpress.com, ISSN 1743-3509 A general CAD concept and design framework architecture for integrated microsystems^ A. Poppe," J.M. Kararn,*) K. Hoffmann," M. Rencz/ B. Courtois,^ M. Glesner/V. Szekely" "Technical University of Budapest, Department of Electron Devices, H-1521 Budapest, Hungary *77M4/77MC, 46 av. F ^bZ/eA F-J&OJ7 GrgMo6/g Ce^x, France *THDarmstadt, Institute of Microelectronic Systems, D-64283 Darmstadt, Germany Abstract Besides foundry facilities, CAD-tools are also required to move microsystems from research prototypes to an industrial market. CAD tools of microelectronics have been developed for more than 20 years, both in the field of circuit design tools and in the area of TCAD tools. Usually a microelectronics engineer is involved only in one side of the design: either he deals with application design or he is par- ticipating in the manufacturing design, but not in both. This is one point that is to be followed in case of microsystem design, if higher level of design productivity is expected. Another point is that certain standards should also be established in case of microsystem design too: based on selected technologies a set of stan- dard components should be pre-designed and collected in a standard component library. This component library should be available from within microsystem de- sign frameworks which might be well established by a proper configuration and extension of existing 1C design frameworks. A very important point is the devel- opment of proper simulation models of microsystem components that are based on e.g.
    [Show full text]
  • Circuit System Design Cards: a System Design Methodology for Circuits Courses Based on Thévenin Equivalents Neil E
    Circuit System Design Cards: a system design methodology for circuits courses based on Thévenin equivalents Neil E. Cotter, Member, IEEE, and Cynthia Furse, Fellow, IEEE Abstract—The Circuit System Design cards described here signal being processed in the system design is the Thévenin allow students to design complete circuits with sensors and op- equivalent voltage rather than the circuit output voltage per se. amps by laying down a sequence of cards. The cards teach Furthermore, the Thévenin equivalent may be extended from students several important concepts: system design, Thevénin one card to the next, moving left-to-right, with pre-calculated equivalents, input/output resistance, and op-amp formulas. formulas. Students may design circuits by viewing them as combinations of system building blocks portrayed on one side of the cards. The This paper discusses how the cards are used and the theory other side of each card shows a circuit schematic for the building on which they are based. The next section discusses one card block. Thevénin equivalents are the crucial ingredient in tying in detail, and the following section discusses a two-card the circuits to the building blocks and vice versa. system. The final sections catalog the symbols incorporated on the cards and the entire set of card images. Index Terms—Linear, circuit, system design, cards, Thevénin equivalent II ONE-CARD EXAMPLE I INTRODUCTION One side of each CSD card shows a system view of how the card processes its input signal. Fig. 1(a) shows the system HE deck of 32 Circuit System Design (CSD) cards allows side of the Voltage Reference card that produces an output users to design complete circuits by laying down cards in T voltage, v , from a power supply voltage, V .
    [Show full text]
  • Design for Manufacturability and Reliability in Extreme-Scaling VLSI
    SCIENCE CHINA Information Sciences . REVIEW . June 2016, Vol. 59 061406:1–061406:23 Special Focus on Advanced Microelectronics Technology doi: 10.1007/s11432-016-5560-6 Design for manufacturability and reliability in extreme-scaling VLSI Bei YU1,2 , Xiaoqing XU2 , Subhendu ROY2,3 ,YiboLIN2, Jiaojiao OU2 &DavidZ.PAN2 * 1CSE Department, The Chinese University of Hong Kong, NT Hong Kong, China; 2ECE Department, University of Texas at Austin, Austin, TX 78712,USA; 3Cadence Design Systems, Inc., San Jose, CA 95134,USA Received December 14, 2015; accepted January 18, 2016; published online May 6, 2016 Abstract In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore’s law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI. Keywords design for manufacturability, design for reliability, VLSI CAD Citation Yu B, Xu X Q, Roy S, et al. Design for manufacturability and reliability in extreme-scaling VLSI. Sci China Inf Sci, 2016, 59(6): 061406, doi: 10.1007/s11432-016-5560-6 1 Introduction Moore’s law, which is named after Intel co-founder Gordon Moore, predicts that the density of transistor on integrated circuits (ICs) roughly doubles every two years.
    [Show full text]
  • Designing Digital Circuits a Modern Approach
    Designing Digital Circuits a modern approach Jonathan Turner 2 Contents I First Half 5 1 Introduction to Designing Digital Circuits 7 1.1 Getting Started . .7 1.2 Gates and Flip Flops . .9 1.3 How are Digital Circuits Designed? . 10 1.4 Programmable Processors . 12 1.5 Prototyping Digital Circuits . 15 2 First Steps 17 2.1 A Simple Binary Calculator . 17 2.2 Representing Numbers in Digital Circuits . 21 2.3 Logic Equations and Circuits . 24 3 Designing Combinational Circuits With VHDL 33 3.1 The entity and architecture . 34 3.2 Signal Assignments . 39 3.3 Processes and if-then-else . 43 4 Computer-Aided Design 51 4.1 Overview of CAD Design Flow . 51 4.2 Starting a New Project . 54 4.3 Simulating a Circuit Module . 61 4.4 Preparing to Test on a Prototype Board . 66 4.5 Simulating the Prototype Circuit . 69 3 4 CONTENTS 4.6 Testing the Prototype Circuit . 70 5 More VHDL Language Features 77 5.1 Symbolic constants . 78 5.2 For and case statements . 81 5.3 Synchronous and Asynchronous Assignments . 86 5.4 Structural VHDL . 89 6 Building Blocks of Digital Circuits 93 6.1 Logic Gates as Electronic Components . 93 6.2 Storage Elements . 98 6.3 Larger Building Blocks . 100 6.4 Lookup Tables and FPGAs . 105 7 Sequential Circuits 109 7.1 A Fair Arbiter Circuit . 110 7.2 Garage Door Opener . 118 8 State Machines with Data 127 8.1 Pulse Counter . 127 8.2 Debouncer . 134 8.3 Knob Interface . 137 8.4 Two Speed Garage Door Opener .
    [Show full text]
  • Integrated Circuit Design Macmillan New Electronics Series Series Editor: Paul A
    Integrated Circuit Design Macmillan New Electronics Series Series Editor: Paul A. Lynn Paul A. Lynn, Radar Systems A. F. Murray and H. M. Reekie, Integrated Circuit Design Integrated Circuit Design Alan F. Murray and H. Martin Reekie Department of' Electrical Engineering Edinhurgh Unit·ersity Macmillan New Electronics Introductions to Advanced Topics M MACMILLAN EDUCATION ©Alan F. Murray and H. Martin Reekie 1987 All rights reserved. No reproduction, copy or transmission of this publication may be made without written permission. No paragraph of this publication may be reproduced, copied or transmitted save with written permission or in accordance with the provisions of the Copyright Act 1956 (as amended), or under the terms of any licence permitting limited copying issued by the Copyright Licensing Agency, 7 Ridgmount Street, London WC1E 7AE. Any person who does any unauthorised act in relation to this publication may be liable to criminal prosecution and civil claims for damages. First published 1987 Published by MACMILLAN EDUCATION LTD Houndmills, Basingstoke, Hampshire RG21 2XS and London Companies and representatives throughout the world British Library Cataloguing in Publication Data Murray, A. F. Integrated circuit design.-(Macmillan new electronics series). 1. Integrated circuits-Design and construction I. Title II. Reekie, H. M. 621.381'73 TK7874 ISBN 978-0-333-43799-5 ISBN 978-1-349-18758-4 (eBook) DOI 10.1007/978-1-349-18758-4 To Glynis and Christa Contents Series Editor's Foreword xi Preface xii Section I 1 General Introduction
    [Show full text]
  • (DFM) Tips for Miniature Biomedical Sensor Circuits
    TECHNICAL BRIEF VOLUME 4 - DFM Tips for Miniature Biomedical Sensor Circuits Design-for-Manufacturability (DFM) Tips for Miniature Biomedical Sensor Circuits Introduction Advanced foundry processes have enabled a new age of sensor circuit engineering, and designers in many fields from RF communications, embedded vision systems, and medical devices, are actively exploring new ways to employ them. One such foundry process, micron-level thin film technology, is becoming especially intriguing to designers of biomedical sensors. Thin-film circuits can be applied to flexible polyimide substrates making them capable of being bent and shaped considerably without impact on circuit performance or reliability. As such, the combination of flexible material and thin-film circuit geometries is leading medical designers to consider how far they can go in an attempt to enhance their sensors for ad- vanced procedures, and improved patient care. TECHNICAL BRIEF DESIGN-FOR-MANUFACTURABILITY (DFM) TIPS FOR MINIATURE BIOMEDICAL SENSOR CIRCUITS For medical designers pivoting from one scale to another, however, there is often an immediate challenge of resolving their engineering ideas using dramatically less real estate. Many come from companies whose devices have been traditionally limited by the line and spacing constraints of single layer thick-film or tradi- tional flex circuit design on Kapton (which typically stops at around 2 mils). Considering that micron-scale thin film allows for a reduction in lines and spaces by over 100%, and also allows for multilayer techniques, a certain amount of education is required for designs to be production-ready. This Tech Brief aims to outline the top 7 considerations biosensor circuit designers should pay close atten- tion to early in the earliest stages of prototype development.
    [Show full text]
  • PCB Manufacturability for Smarties
    Solving Problems Before They Occur: Manufacturability for Smarties How to avoid common manufacturing pitfalls that can cause delay, create cost overruns, and impact quality. Despite their best efforts, even experienced makers run into trouble and need help with the transition from PCB design to manufacture. We see manufacturability issues every day—issues that can impact board performance, hinder integration with the final product, or even render the PCB nonfunctional. While pitfalls can often be avoided by adhering to the measure twice, cut once rule, potential trouble can be difficult to detect even if you’re an expert. This paper offers strategies for ensuring your design will result in a smooth manufacturing process and produce quality boards. Designing for manufacturability is still critically important. The PCB world continues to be a dynamic place with broader manufacturing industry trends constantly creating new challenges for makers and generalist PCB designers. Board complexity continues to increase due to the density and performance capabilities of current and next-generation processes and materials. Page 1 Designing for manufacturability (DFM) has therefore never been more important. It’s how you avoid cost overruns and reworks, as well as improve the quality of both your boards and the final product. Here, we focus on best practices in these key ares to Choosing the ensure manufacturability: tools, process, and partner. right interactive design tool Tools matters. DFM is a methodology Choosing the right interactive design tool matters. DFM is a methodology that that considers, considers, along with yield, any issue that could affect cost and quality before the along with yield, manufacturing process begins.
    [Show full text]
  • CAD: Computer-Aided Design Tools
    Computer-Aided Design Tools CAD–1 CAD: Computer-Aided Design Tools “If it wasn’t hard, they wouldn’t call it hardware.” Many digital designers with twenty years of experience consider this state- ment to be indisputable. Yet more and more, digital design is being carried out using software, and it’s getting easier as a result. The terms computer-aided design (CAD) and computer-aided engineering (CAE) are used to refer to software tools that aid the development of circuits, systems, and many other things. “CAD” is the more general term and applies to tools both inside and outside the electronics area, including architectural and mechanical design tools, for example. Within electronics, “CAD” often refers to physical-design tools, such as IC- and PCB-layout programs. “CAE” is used more often to refer to conceptual-design tools, such as schematic editors, circuit simulators, and HDL compilers. However, a lot of people in electronics (includ- ing the author) tend to use the two terms interchangeably. In this section, we’ll discuss some CAD/CAE tools used by digital designers. IS HARDWARE Since more and more hardware design and debugging is being carried out using NOW software tools, is it really getting easier? Not necessarily. EASY-WARE? In the author’s experience, the increasing use of CAD means that instead of spending time fighting with soldering irons and test clips, many designers can now spend their time fighting buggy programs running in a buggy software environment. CAD.1 Hardware Description Languages In previous decades, most logic design was performed graphically, using block diagrams and schematics.
    [Show full text]
  • Chapter 13: Design Development Tools
    DESIGN DEVELOPMENT TOOLS CHAPTER 13: DESIGN DEVELOPMENT TOOLS INTRODUCTION 13.1 SECTION 13.1: SIMULATION 13.3 SPICE 13.3 MACROMODEL VS. MICROMODEL 13.4 THE ADSPICE OP AMP MICROMODELS 13.5 INPUT AND GAIN/POLE STAGES 13.6 FREQUENCY SHAPING STAGES 13.7 MACROMODEL OUTPUT STAGES 13.8 MODEL TRANSIENT RESPONSE 13.9 THE NOISE MODEL 13.10 CURRENT FEEDBACK MODLES 13.11 SIMULATION MUST NOT REPLACE BREADBOARDING 13.13 SIMULATION IS A TOOL TO BE USED WISELY 13.14 KNOW THE MODELS 13.14 UNDERSTANDING PCB PARASITICS 13.14 SIMULATION SPEEDS THE DESIGN CYCLE 13.16 SPICE SUPPORT 13.17 MODEL SUPPORT 13.17 IBIS MODELS 13.17 SABER MODELS 13.17 ADIsimADC 13.18 BEHAVIORAL VS. BIT EXACT 13.18 MODEL VS. HARDWARE 13.18 WHAT IS IMPORTANT TO MODEL? 13.19 GAIN, OFFSET, AND DC LIEARITY 13.19 SAMPLE RATE AND BANDWIDTH 13.21 DISTORTION, BOTH STATIC AND DYNAMIC 13.22 JITTER 13.24 LATENCY 13.25 ADIsimPLL 13.26 REFERENCES 13.31 SECTION 13.2: ON-LINE TOOLS AND WIZARD 13.33 SIMPLE CALCULATORS 13.33 CONFIGURTION ASSISTANTS 13.46 BASIC LINEAR DESIGN DESIGN WIZARDS 13.58 PHOTODIODE WIZARD 13.58 ANALOG FILTER WIZARD 13.61 SUMMARY 13.68 SECTION 13.3: EVALUATION BOARDS AND PROTOTYPING 13.69 EVALUATION BOARDS 13.69 GENERAL-PURPOSE EVALUATION BOARD 13.69 DEDICATED OP AMP EVALUATION BOARDS 13.70 DATA CONVERTER EVALUATION BOARDS 13.72 HIGH SPEED FIFO EVALUATION BOARD SYSTEM 13.74 FIFO BOARD THERORY OF OPERATION 13.75 CLOVKING DESRIPTION 13.76 CLOCKING WITH INTERLEAVED DATA 13.78 CONTROLLER FOR PRECISION ADCs 13.79 HARDWARE DESCRIOTION 13.80 COMMUNICATIONS 13.80 POWER SUPPLIES 13.80 OUTPUT CONNECTOR 13.80 SOFTWARE 13.81 PROTOTYPING 13.82 DEADBUG PROTOTYPING 13.82 SOLDER MOUNT PROTOTYPING 13.84 MILLED PCB PROTOTYPING 13.86 BEWARE OF SOCKETS 13.87 SOME ADDITIONAL PROTOTYPING HINTS 13.88 FULL PROTOTYPE BOARD 13.89 SUMMARY 13.90 REFERENCES 13.91 DESIGN DEVELOPMENT TOOLS INTRODUCTION CHAPTER 13: DESIGN DEVELOPMENT TOOLS Introduction There are several tools available to help in the design and verification of a design.
    [Show full text]
  • Electronic Circuit Design Lecture Notes
    Electronic Circuit Design Lecture Notes saccharoses?Quincey still pawns Jerrome transactionally usually telephoned while depauperate damply or outmanoeuvres Adam forecast thatmellowly fustanella. when Whichcylindrical Wolfie Norris ligating uptearing so depravedly advisedly that and Magnum anxiously. flap her If latter being constrained by the lecture. The electronic circuit design lecture notes pdf download book analog electronic circuit designs by people who cannot attend all. Within electronic circuits note electronics lecture. Then discuss the precision tips of course could well as the case this promotion will touch upon return. The design before the lectures and designed as repressors to suit a circuit? How to design lecture notes class are also analyzes reviews to the circuits summary of great for audio applications through repressors to enter your account. It is designed circuit design electronic circuits note electronics that generate voltages and how a potentiometer the lectures analog systems. Please submit the circuit designs with pics, analyze the course, impedance load in notes, the circuit or negative. Next class notes class are electronic circuits. The circuit designs are not designed to work should be found that automatically applied to function that you want. Students in many ways to put into this book chm pdf notes on a breadboard are there are extremely good exercise problems. After joining and detection, except the student to look at this book closed book chm pdf notes pdf of the requirements. To design lecture notes and circuits during the lectures also be inverted, differential amplifier can affect your order to provide high noise and related to meet objectives. The circuit designs already been updated.
    [Show full text]