Hot-Carrier-Reliability Design Guidelines for CMOS Logic Circuits

Home , Circuit design

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 3, MARCH 1994 253 Hot-Carrier-Reliability Design Guidelines for CMOS Logic Circuits

Khandker N. Quader, Student Member, IEEE, Eric R. Minami, Wei-Jen Huang, Ping K. KO, Member, IEEE, and Chenming Hu, Fellow, IEEE

Abstract- Long-term ring-oscillator hot-carrier degradation term ring oscillator degradation results and BERT simulation. data and simulation results are compared to demonstrate that This will be followed by derivations of hot-carrier-reliability a circuit reliability simulator BERT can predict CMOS digital design rules for digital applications and comparisons of circuit circuit speed degradation from transistor dc stress data. We present generalized hot-carrier-reliabilitydesign rules that trans- degradation calculated using the design rules presented here late device-level degradation rate to CMOS circuit lifetime. The with BERT simulations and experimental data. Finally, we design rules, which consist of lifetime and speed degradation will present techniques for using the design rules for quick factors, can roughly predict CMOS circuit degradation during estimates of circuit lifetime. the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ f trise and 11. HOT-CARRIERFUNDAMENTALS lo/ f t~lrespectively. Typically, the NMOSFET and PMOSFET Static (dc) hot-carrier degradation has been extensively speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 studied [5]-[SI; lingering controversy regarding dynamic (ac) MHz operating frequency and for an input rise time of 0.35 ns, degradation is also rapidly dissipating. Although different the NMOSFET and PMOSFET time factors are 120 and 300, mechanisms for enhanced dynamic degradation have been respectively. noted in the past [9], [lo], recent studies on the dynamic degradation of MOSFET’s in an actual circuit environment I. INTRODUCTION [ 1 11-[ 141 have concluded that the quasi-static model, which considers ac stress merely as a series of short dc stresses strung HE understanding of the relationship between circuit life- together, is still valid for real circuits. Inductive noise [15] time to device dc stress lifetime is becoming increasingly T and error in substrate and gate current models can contribute important for deep submicron technologies since criteria such more variation to the degradation than remaining enhanced as a lo\% drain current change in ten years are no longer ac degradation in actual circuits. BERT is a reliability sim- viable. Hot-carrier-reliability simulators, such as the substrate ulator for hot-carrier as well as oxide and electromigration current simulator [l], BERT [2], HOTRON [3], and RELY reliability simulation [16], [ 171. It uses a quasi-static approach [4], have been developed to predict CMOS circuit reliability; however, the simulation process is time consuming and is best to predict hot-carrier-induced CMOS circuit degradation, and suited for overall product reliability simulation towards the includes both NMOSFET and PMOSFET hot-carrier models. end of the design phase. A simple guideline for estimating hot- The amount of degradation, AD, such as the change in drain carrier reliability is still desirable. Although a circuit designer current (AId/Id), suffered by an MOS device due to hot- can do first-order estimates of speed, power consumption, and carrier stressing is given by [5] circuit area, no analytical tool is available yet during the design AD = F (Age) (1) phase to quickly evaluate and optimize circuits for hot-carrier sensitivity. In this paper, we present a generalized set of design where the function F can be experimentally determined and rules that can help the circuit designer to incorporate the effects the parameter “Age” (amount of stress experienced by each of hot-carrier degradation during the initial design phase and device) is used to quantify device degradation during cir- can help device reliability engineers to quickly estimate overall cuit operation. The NMOSFET and PMOSFET Ages can be product reliability from simple dc stress experiments. expressed as [2], [18], [19] We will first give a brief overview of hot-carrier effects and the circuit reliability simulator, BERT(BErke1ey Reliability Tools), followed by the correlation between experimental long- (3) Manuscript received July 26, 1993; revised October 27, 1993. This work was supported by SRC under Contract 92-MJ-148 and ISTO/SDIO through ONR under Contract N00014-92-J-1757, MICRO, AMD, Philips, Rockwell, where W is the device width, H and m are the gate-bias and HP. This paper is an expanded version of a paper presented at the 1993 dependent degradation parameters, Isub3Ig, and Ids are the IEEE Custom Integrated Circuits Conference. substrate, gate, and drain currents, respectively, and T is The authors are with the Department of Electrical Engineering and Com- puter Science, University of Califomia, Berkeley, CA 94720. the duration of the stress. The subscripts s and g in m IEEE Log Number 9214793. and H denote substrate and gate current, respectively, and

0018-9200/94$04.00 0 1994 IEEE 254 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.29, NO. 3, MARCH 1994 the subscripts n and p refer to NMOSFET and PMOSFET, respectively. Equation (1) can be expressed as

Age = F-'(AD). (4) Substituting this in (2) and (3), we can write the NMOSFET and PMOSFET dc device lifetime r, and rp by the following expressions: gJlo-' (BERTSimulation)

1" loo IO' lo2 lo3 io4 io5 Time (min) rp = H,,F-'(AD) - (6) -mgp [;I [;I Fig. 1. Experimental and BERT-simulated frequency degradation versus The slope and intercept of the 7,1ds/W versus Isub/Ids plot stressing time for a 91-stage ring oscillator. Correlation with dc stress data for NMOSFET and the slope and intercept of the rp versus is also shown. Ig/W plot for PMOSFET give the m and H degradation parameters. In [20], it has been shown that H and m are, simulation and experimental results that suggests that circuit in general, gate-bias ( Vgd) dependent. Thus, by including degradation can be predicted using the quasi-static method. the bias dependence of H and m, BERT can accommodate All SPICE circuit simulations were performed using BSIM2 all known quasi-static models such as recently proposed low model parameters. and high gate voltage hot-carrier models [21]. Mistry et al. IV. HOT-CARRIER-RELIABILITY [21] assign physical mechanisms to the low V,, medium DESIGNRULES FOR CMOS CIRCUITS V,, and high V, regions. There are still disagreements on these assignments [22]. BERT does not assume any physical In this section, we show how circuit lifetime is related to degradation mechanism, and is capable of representing several device dc stress lifetime commonly monitored in IC industries different mechanisms. It is our experience, however, that today. Lee et al. [23] first introduced simple rules of thumb constant H and m at peak Isub condition are usually adequate. to translate discrete device degradation to actual circuit per- This is supported by experimental verification of a wide class formance degradation of inverter-based CMOS VLSI circuits. of digital circuits. During BERT simulation, Ids and Is& or I, Leblebici et al. [24] have also developed macromodels for are calculated for each device and at each time step, and then NMOSFET that relate circuit parameters such as input rise integrated to obtain the total Age of each device. Separately, time, capacitance, and device width to Age, the severity of the user provides measured transistor SPICE model parameters hot carrier damage. In this paper, we present a generalized at several different dc Ages as input to BERT. After the Age set of hot-carrier-reliability design rules that can aid circuit of each transistor in the circuit is calculated, the aged process designers as well as device and reliability engineers, and we files correspondingto the individual transistors are then used to also include the effects of PMOSFET drain current increase simulate the actual circuit degradation for a specified period on the overall performance of VLSI circuits. For simplicity, of time. we ignore the effects of "off-state'' damage [25] in this study. The design rules presented here: 1) translate device-level 111. EXPERIMENTALAND SIMULATION RESULTS linear or saturation drain current change to circuit speed change, and 2) translate dc lifetime to ac lifetime. Fig. 2 A 0.7pm, 17.5 nm oxide, LDD CMOS technology (tech- shows the simulation results of linear A Id/Id of a dc stressed nology A) and a 1.2pm, 21 nm oxide LDD CMOS technology NMOSFET device, linear A Id/Id of an NMOSFET device (technology B) were used to fabricate the ring ocsillators, internal to the ring oscillator and subjected to the ring oscillator digital circuits, and the discrete devices. Devices with L,R = stress, and Af/f of the ring oscillator with PMOSFET degra- 0.5-0.95 pm have been used in this study. The most important dation turned off. The two rules of thumb can be understood dc stresses were those done under peak substrate current from Fig. 2. The horizontal shift, called NMOSFET lifetime condition for NMOSFET and peak gate current condition for factor (NTF), represents the time required for the internal PMOSFET. Vds = 8 V was used for all stresses and Vds = 5 ring oscillator NMOSFET device to reach an equivalent dc V was used for all measurements. A Id/Id (linear or saturation), and the vertical shift, called SPICE model parameters for substrate and gate currents the NMOSFET speed degradation factor (NSF), represents the were first extracted for N- and PMOSFET's. Then, degradation factor required to translate a given A Id/Id to circuit speed parameters H and m were determined using the method degradation. Fig. 3 is the same as Fig. 2, except that it is for outlined in the previous section. Constants H and m are PMOSFET, with PTF and PSF representing the PMOSFET used for this study for simplicity. Fig. 1 shows the experi- lifetime and speed degradation factors, respectively. mental and simulated linear drain current degradation of N- and PMOSFET's and the long-term experimental and BERT- simulated ring oscillator frequency degradation for technology A. Lifetime Factor A. This is the first verification of long-term circuit degradation Figs. 4 and 5 show the gate (V,) and drain (Vd) voltage simulation. Fig. 1 also shows excellent correlation between waveforms of MOSFET's undergoing inverter stress. The QUADER er al.: HOT-CARRIER-RELIABILITY DESIGN GUIDELINES 255

lo' PMOSFET AID I ID PMOSFET AI^ / iD \\ >-A ring~w.~tre~~

C .;" 100 m Frequency degradation m \ Q P Frequency degradation fi$1 StressVdd=8v Stress V, = 8v Le,= 0.5 pm,To, = 17.5~1 T,= 17.5~11,LeE = 0.5 Fm ioo io1 io2 io3 io4 io5 Time (min.)

Fig. 2. BERT simulation showing NMOSFET contribution to hot- ~i~,3, BERT simulation showing PMOS~T to hot- carrier-reliability design rules. Ring oscillator simulation is due to only carrier-reliability design Ring oscillator simulation is due to only NMOSFET degradation. Also shown is the internal ring oscillator NMOSFET PMOSFET degradation. ~l~~ shown is the internal ring oscillator PMOSFET linear A Id/Id during ac stress. and NSF are *e NMOSFET lifetime linear A Id/Id during ac stress. PTF and PSF are the PMOWET lifetime and speed degradation factors, respectively. and speed degradation factors, respectively. lifetime factor (TF) is defined as and PMOSFET lifetime factors by the following expressions: worst-case dc Age 4 TF = (7) NTF = - (9) ac Age f . trise IO where Age has been defined earlier in (2), (3). Figs. 4 and 5 PTF = - (10) f . hall also show Age rate as a function of time. Total Age is the area under the Age rate curves shown in Figs. 4 and 5. Equations (2) where f is the frequency of operation, trise is the rise time, and (3) should be used whenever feasible, but for the purpose and tfan is the fall time. Fig. 7 shows the NMOSFET lifetime of approximate and quick estimation of lifetime factor from factor as a function of input rise time and as a function voltage waveforms, we now introduce effective ac stress time. of operating frequency. The experimental lifetime factor in The effective ac stress time is simply some effective stress Fig. 7 has been determined by using special test structures time during which the transistor undergoes near-worst-case [14], [26]. Figs. 6 and 7 show that the analytical model can dc aging rate. Thus, to first order, the lifetime factor can be predict the lifetime factor over a wide range of input rise/fall approximated by the following: time, frequency, and for different technologies. Equation (9) has a simple interpretation: the effective stress time is the cycle time time when is within a &d/4 range, as shown in Fig. 4. TF x vg effective stress time Similarly, as shown in Fig. 5, Ig is significant when Vg is 1 within a Vdd/lO range. With technology scaling, the rise/fall = (+)effective stress time time decreases, but the frequency increases. Assuming t, = tf and f = 1/30t,, NTF = 120 and = 300. Thus, NTF - -1 PTF f Teff and PTF are not expected to vary much as VLSI technology is scaled. Equations (9) and (IO) can be used to predict the where f is the frequency of circuit operation and the effective lifetime of any circuit from dc lifetime data. For example, if stress time is the duration over which significant aging occurs. f = 100 MHz and the input rise time = 0.35 ns, (9) predicts an Figs. 4 and 5 can be used to determine the criterion for NMOSFET lifetime factor of 120. Therefore, it will take 120 effective stress time. The effective stress time in (8) of any in- times the worst-case dc lifetime for an NMOSFET transistor circuit MOSFET is a function of input rise time and the output to reach the same degree of degradation that defines the end fanout factor. Fig. 6 shows the BERT-simulated NMOSFET of dc life. For example, if 10% AId/Id is reached in 0.1 year lifetime factor as a function of frequency of operation, input under worst-case dc, it will take 12 years to produce 10% rise time, and output fanout factor. The lifetime factor is A&/& under ac operation. found to be inversely proportional to the input rise time and Most digital circuits undergo inverter-like transitions, and insensitive to output fanout factor. After simulating the lifetime (9) and (10) can adequately predict lifetime factors. However, factor for varying circuit conditions, we model the NMOSFET in bidirectional circuits, such as pass gates, both the gate and 256 WEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.29. NO. 3, MARCH 1994

0 Frequency (MHz) 5 L

-4 c) 5 4 400 Symbols: BERT Simulation &3 NTF = 4lf t, * z2

91.1 21.2 21.3 21.4 21.5 21.6 21.7 -U 2 4 6 X1U Time (ns) Input Rise Time, t, (ns), Output fanout

15 30 45 60 75 300. I,I. I I. I a Frequency (MHz)

NTF = 4/f t,

To, = 2 Inm, Ld = 0.95ym

wG 100- a. I; 50- p6.1 16.2 16.3 16.4 16.5 16.6 16.7 E Time (ns) 20 2 4 6 Input rise time, tr (ns) Fig. 5. Gate and drain voltage waveforms affecting PMOSFET device deiradation. Total Age is the area under the Age rate curve. Effective stress Fig. 7. Measured NMOSFET lifetime factor as a function of input rise time that determines lifetime factor can be determined from the Age rate curve time and as a function of stressing frequency for technology B. Different and is shown by the shaded region. Significant aging occurs when If, is with frequencies have been obtained by using ring oscillators with different stages, a vdd/lo range. The input rise time variations have been obtained by using inverter chains with different capacitive loading. Input rise time curves are for f = 20 MHz. the source voltage can change during transients. Thus, the V,, waveform does not resemble the inverter-like transition are the fresh and degraded discharging current, then the fresh [311. We propose the first-order lifetime factor estimates fall time tfo and the degraded fall time tf of an inverter are for bidirectional circuits in (11) and (12), shown on the given by bottom of the previous page, where NTF and PTF are the 1 tfo =C J - dv (14) NMOSFET and PMOSFET lifetime factors and VTn(p)are LO the NMOSFET (PMOSFET) threshold voltages. 0.93,O. 1, and 1 0.35 are empirically determined constants. Equations (1 1) and tf =C J zdv. (15) (12) are the general forms for lifetime factors, and (9) and (10) Defining A I, = In0 - In, the hot-carrier-induced change in are the simplified forms for inverter-like transitions. fall time At, = tf - tfo can then be expressed as Recently, there have been reports of stressing vd, larger than Vdd due to capacitive coupling and charge redistribution [21]. Users can incorporate such effects into the design rules presented in this paper by changing the operating Vdd. Fig. 9 is a plot of A I/I versus vds for N- and PMOSFET's. The I-&, trajectory during the inverter transient is a function B. Speed Degradation Factor of Vgs;however, for the purpose of illustration, we show Consider an inverter with output load capacitance CL (Fig. A I/I for a constant V,, in Fig. 9. For typical quality oxide, 8). The time to charge or discharge CL is given by NMOSFET degradation is dominated by interface traps and A I,/Ino is negligible over part of the high vd, range, where CLdV dt = - the acceptor-type interface traps are empty [8], [14]. The I fractional change in fall time can then be approximated as where I is the charging/discharging current and dt is the time required to change the output by voltage dV. If In,, and I, QUADER et al.: HOT-CARRIER-RELIABILITY DESIGN GUIDELINES 257

TABLE I TYPICALNMOSFET AND PMOSFET SPEEDDEGRADATION FACTORS FOR EQUAL RISEAND FALLTIMES. FORTYPICAL QUALITY OXIDES THE NMOSFET AND PMOSFET SPEED DEGRADATIONFACTORS ARE 1/4 AND 1/2, RESPECTIVELY,IF SATURATION DRAIN CURRENT IS USED AS THE MONITOR Monitor a 11 Linear A Id / Id i82 AV tf==CL- In

Fig. 8. Inverter driving a capacitor CL. Ip and I, are the charging and discharging currents. t, and tf are the rise and fall times. we can express the fractional change in rise time as At, AId, -7z- (18) trO IdpO 14 12 0 NMOS, mppy oxide where A Idp/IdpO in (18) is the PMOSFET percentage change v PMOS, normal oxide in drain current (linear or saturation). We favor A Idp/IdpO h 10 measured at Vd, = V,, = vdd/2 for uniformity with NMOS- 58 FET. The total propagation delay and the hot-carrier-induced :-6 change in the propagation delay of an inverter are given by U 74 1 2 tpdO = 5 (tf0 + tr0) (19) 0 1 012345 A tpd = E (Atjo + At,,). (20) Using (9), (lo), (17)-(20), we can express the fractional Fig. 9. NMOSFET and PMOSFET A I/I behavior as a function of drain change in propagation delay as voltage for typical oxide. For the purpose of illustration, only the V,, = 5 V case is shown.

CY in (17)relates the proper average of A In/In0 (discharging current) to any specific value of the drain current A I&/I&O, e.g., linear (AIdlin/Id]inO) or saturation (AIdsat/IdsatO). The negative sign in the second term that reflects a decrease Today, A Idlin/Idlin is commonly measured and reported. in rise time is due to a PMOSFET drain current enhance- However, we favor AIdsat/Idsat measured at V,, = Vdd/2 ment. TaC,Tdc,f,tr, and tj are the circuit operating time, and vds = V&/2 for the following reason. CY varies from the equivalent dc stress time, operating frequency, rise time, 0.25 (typical) to 0.5,depending on the abundance of electron and fall time, respectively. NSF and PSF, the NMOSFET traps in the gate oxide if AIdlin/Idlin is used in (17). If and PMOSFET speed degradation factors, in (21) take the AIdsat/Idsat measured at v,, = vdd/2 and vd, = Vdd/2 following form: is used, a is a constant 0.5 [14]. If any other measurement condition for AIdsat/Idsat is used, then CY has to be adjusted accordingly. Our studies show that for two different LDD technologies, CY is a constant in the saturation region; however, the impact of the type of drain structure on CY requires further For further approximation, t,o may be taken to be equal study. to tfo. Table I shows typical values of CY, NSF, and PSF The PMOSFET drain current increases due to hot-carrier for trO = tjo. Clearly, AIdsatIddsat is related to speed stressing that then causes the rise time trO to decrease. The degradation in a more simple manner than A Idlin/Idlin. From dominant mechanism of PMOSFET is electron trapping [18], Table I, we find that for typical oxides, 10% of AId/ld [28], [29]. There has been a recent report of a buried channel in NMOSFET contributes approximately 1.25% to the speed PMOSFET on a 3.5 nm oxide technology which shows current degradation if Idlin is used and 2.5% if Idsat is used. 10% of reduction in PMOSFET’s at high V,, due to interface state a A Id/ld increase in PMOSFET contributes approximately 5% to the speed increase. These factors are consistent with generation [27].Since this does not influence current and next the simulation results shown in Figs. 2 and 3. The PMOSFET generation technologies (Tax > 8.5 nm), we have ignored this lifetime factor is much larger than the NMOSFET lifetime in our analysis. Further studies are needed to understand such factor. Appropriate NMOSFET and PMOSFET lifetime fac- behavior and its impact on circuit reliability. Fig. 9 shows that tors (9)-(lo), in conjunction with (21), have to be used to A Ip/IPo behavior is approximately constant over the entire determine the actual contribution of the PMOSFET to the vd, range. Thus, the factor a is unity for the PMOSFET, and total circuit speed change. 258 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL.29, NO. 3. MARCH 1994

C. Series-Connected Transistors Many circuits such as NAND and NOR gates have multiple transistors in series. Fig. 10 shows k NMOSFET's in series, each having the same W/Lratios and the same internal node capacitance CI . CL is the output capacitance. For series- connected gates, significant degradation occurs only in the top transistor, which is the only transistor experiencing vds = Vdd during switching [with dl the remaining transistors on (V, = Vdd)] [12]. Representing the transistors as linearized RC elements [30], [31], the fall time for series-connected Fig. 10. k NMOSFET's connected in series. The RC equivalent network is transistors can be written as shown on the right. For the worst-case stress condition, only A41 undergoes any significant stress, resulting in a change in RI. Tk = RIcioad R~(CIf Chd) -k . . . -k Rk([k- l]CI + Cload). (24) For the input transistor shown in Fig. 10, only Ad1 undergoes LeC= 0.95pm hot-carrier stressing, and as a result, RI changes to RI + AR1. The percentage change in propagation delay, due to fall time change only, is then given by

Ark AR1 r1 a -E-- - (25) d rk R1 rk' a .StressVdd=8v Stressing frequency = 20MHz ' ''.'..I ' ' """' ' For k = 1 (inverter case), (21) and (25) give 10-1 . . 102 1.03 io4 Ar1 AR A Idn Time (min.) -=1-- NSF-. (26) 71 R1 IdnO Fig. 11. Measured hot-carrier-induced change in propagation delay of IN- VERTER, two-input NAND, and two-input NOR chains. Data show that the Therefore, the change in propagation due to NAND gate speed factor is about one-third that of the INVERTER, and the A Id/Id of one of k NMOSFET's connected in series Can be NOR gate speed factor is approximately the same as INVERTER. written as TABLE I1 (27) CALCULATEDNMOSFET AND PMOSFET SPEED DEGRADATIONFACTORS OF SERIES-CONNECTEDTRANSISITORS COMPARED WITH BERT SIMULATIONRESULTS

1 Similarly, for k PMOSFET's connected in series, the fractional (NSF)k h change in propagation delay due to rise time change only is k Eq. (27) BERT Eq. (28) BERT given by 1 4.2 4.3 2.2 2.3 2 7.0 7.2 4.5 4.6 3 11.4 11.0 6.4 6.2 5 12.6 11.9 7.5 7.8 7 14.0 13.3 8.2 8.7 NSF and PSF are given by (22) and (23), respectively. Table I1 compares the speed factors of series-connected gates obtained the percentage change in propagation delay of a NAND gate from (27) and (28) with those of BERT simulations. For small is given by k, (rk/rI) was found to be approximately equal to k, where k is the number of series-connected NMOSFET's or PMOS- FET's, respectively. Thus, series-connected MOSFET's, such as the NMOSFET in a NAND gate or the PMOSFET in a NOR gate, has its speed degradation factor divided by the number of series-connected transistors kn or kp in (27) and (28). This is obvious in Fig. 11, which shows the change in propagation delay of INVERTER chain, two-input NAND chain, and two- For k-input NOR gates, since the PMOSFET transistors are input NOR chain. Fig. 11 shows that the degradation of NAND series-connected while the NMOSFET's are in parallel, the chain is about one-third that of the degradation of a similarly percentage change in propagation delay is given by loader inverter, and the degradation of the NOR chain is about the same as similarly loaded inverters. The results of Fig. 11 confirm that the speed degradation is approximately inversely proportional to the number of series-connected transistors. For k-input NAND gates, the NMOSFET transistors are series-connected, while the PMOSFET's are in parallel. Thus, QUADER et al.: HOT-CARRLER-RELIABILITY DESIGN GUIDELINES 259

channel

Fig. 12. NMOSFET transistor used as a pass gate and its cross section after undergoing hot-carrier-induced bidirectional stress. A’,, is the interface state trap density. For vd, > 0, damage is located near the drain, and for Vd, < 0. damage is located near the source. (~5~t)~and (Llt)d are the extent of the (%) hot-carrier-induced damage regions. Increase in propagation delay Fig. 13. Calculated percentage change in saturation current of an NMOSFET within an inverter chain as a function of percentage change in propagation delay. The circuit lifetime as a function of change in propagation delay shown T,,, Tdcl fl t,, and tf are the circuit operating time, the equiv- on the right y-axis has been calculated using the design rules presented here. alent dc stress time, operating frequency, rise time, and fall time, respectively. Equations (27) and (28) can also be ex- tended to determine the propagation delay of any complex increase in propagation delay. Figs. 6 and 13, in conjunction logic blocks. with dc stress data, form a set of design curves that can be used for first-order circuit lifetime estimation and for optimization D. Bidirectional Circuits of circuit blocks for hot-carrier sensitivity during the initial Transistors used as pass gates undergo bidirectional stress. design phase. For example, if a 2.5% change in propagation Fig. 12 shows an NMOSFET and its cross section after delay is acceptable, then the change in NMOSFET saturation undergoing hot-carrier-inducedbidirectional stress. For vds > drain current from Fig. 12 is 10%. The dc lifetime at 10% 0, the damage is on the drain side, and for Vds < 0, the damage change in saturation current can be determined from the is on the source side. The total drain current degradation of a dc stress data, and with NTF = 120 (100 MHz operation), MOSFET after bidirectional stress is given by [33], [341 the circuit lifetime of a technology dominated by NMOS- FET degradation is approximately 12 years for an operating AId - AId (31) V& of 5.5 V. Hot-carrier-induced PMOSFET drain current -Id0 - (Idu)++ (2)- enhancement increases the circuit lifetime, and PMOSFET where the first term represents the drain current degradation curves similar to Fig. 13 can be used to determine the circuit due to stress under positive Vds and the second term represents lifetime increase due to combined effects of NMOSFET and the drain current degradation due to stress under negative PMOSFET. Vds. The poststress NMOSFET forward mode and reverse mode drain current behavior is asymmetrical [34], while the poststress PMOSFET drain current behavior is approximately A. Circuit Reliability Prediction symmetrical [29]. PMOSFET degradation has been modeled Hot-carrier degradation of any circuit block can be estimated well by a shortening of le^, which correctly models a reduc- by using the following steps: 1) divide a desired circuit lifetime tion in VT,I&, and A &/Id and symmetry with respect to with the lifetime factor to obtain the equivalent dc stress time polarity [ 111, [28]. Assuming equal amounts of positive and for a logic stage, 2) obtain AId/Ido for this dc stress time, 3) negative stresses, the percentage change in propagation delay divide A Id/Id by the speed degradation factor of each stage of a CMOS pass gate after bidirectional stress can then be of the circuit block (such as inverter, NAND, NOR, etc.) and expressed as multiply by the fresh delay (T) of each stage to obtain the change in delay (AT)of each stage, and 4) sum the AT of %=(i+r)~~~--2-~~~-A Idn A’dp (32) all the logic stages in the circuit block and divide by the fresh Tpd0 IdnO IdpO block delay to obtain AT/T. where AId/Id is the current degradation due to positive (or Fig. 14 is a circuit diagram of a two-input multiplexor, and negative) stress alone and y, representing the larger A &/Id Fig. 15 is the calculated percentage change in propagation of the NMOSFET in the “reverse mode” [34], is typically 2. delay of the multiplexor as a function of circuit operating time For NMOSFET-only pass gates, A rp‘pd/rP‘pdois twice the first and as a function of circuit operating frequency. Each point term. The factor y is a function of measurement conditions has been calculated using the above procedure. From Fig. 14, and can vary from technology to technology. we see that for a 2.5% change in propagation delay in 10 years, the maximum circuit operating frequency is 50 MHz, and for a 3% change in plopagation delay, the maximum operating V. HOT-CARRIER-RELIABILITYDESIGN frequency is 80 MHz. CURVES FOR CMOS CIRCUITS Fig. 16(a) is the circuit schematic of the carry stage of a Fig. 13 shows the percentage change in Idsat of an in-circuit static CMOS ripple carry adder [35], Fig. 16(b) is an 8-b NMOSFET of an inverter chain as a function of percentage CMOS ripple carry adder, and Fig. 16(c) is the timing diagram 260 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.29. NO. 3, MARCH 1994

I TT T I

Fig. 14. Circuit diagram of a two-input multiplexor used as a test case study to show how hot-carrier reliability of any circuit block can be evaluated using the design rules presented in this paper.

. Change in delay calculated I - 6 -using hot-carrier design rules 5 -Power supply = 5.5~ 3 .To, = 17.5nm .9 3-

25 MHz CI. cin L ” lo-’ IO0 10’ IO2 Id Cout / Circuit operating time (years) (C) Fig. 15. Calculated percentage change in propagation delay of the circuit of Fig. 16. (a) Schematic of the carry stage of a static CMOS adder, (b) 8-b Fig. 14 a function of stressing time and as a function of operating frequency. as CMOS static ripple carry adder, and (c) timing diagram during stressing. A = GND and E = I-& during stressing.

during stressing. Fig. 17 shows the percentage change in the propagation delay of the carry-out signal of an 8-b ripple carry adder as a function of stressing time. The percentage change in the propagation delay of carry-out signal calculated using the analytical model presented in this paper is in good agreement with the experimental data.

8-bit adder U Stress V, = 8v VI. CONCLUSION BERT, a reliability simulator, was successfully used to Time (min.) predict the long-term hot-carrier degradation behavior of ring Fig. 17. Change in propagation delay of the carry-out signal of the 8-b ripple oscillators. Generalized hot-carrier-reliability design rules that carry adder. For all I-b adders of Fig. 16(a), 4 = GND and B = & during translate device-level degradation to CMOS circuit lifetime stressing. The solid line is obtained using the dc data and the analytical model. have been presented. The design rules, which consist of two Operating frequency = 20 MHz. factors, speed degradation and lifetime, and which include both PMOSFET and NMOSFET models, can be used for quick REFERENCES estimates of CMOS circuit lifetime. The rules can also serve [l] T. Sakurai, K. Nogami, M. Kakumu, and T. IIzuka, “Hot-carrier as useful design aids for circuit designers in evaluating hot- generation in submicrometer VLSI environment,” IEEE J. Solid-state Circuits, vol. SC-21. p. 187, 1986. carrier sensitivity of different circuit blocks. Two LDD and two [2] P. M. Lee, M. M. Kuo, K. Seki, P. K. KO, and C. Hu, “Circuit aging non-LDD technologies were used in this study. More studies simulator (CAS),” in IEDM Tech. Dig., 1988, p. 134. are needed to understand the impact of differernt types of drain [3] S. Aur, D. E. Hocevar, and P. Yang, “Circuit hot electron effect simulation,” in IEDM Tech. Dig., 1987, p. 498. structures on the model parameters. [4] W. J. Hsu, C. C. Shih, and B. J. Sheu, “RELY: A reliability simulator for Experimental results of an 8-b ripple carry adder were used VLSI circuits,” in Proc. IEEE Custom Integrated Circuits Cant, 1988, to demonstrate the validity of the analytical model. For an p. 27.4.1. [5] C. Hu, S. C. Tam, F. C. Hsu, P. K. KO, T. Y. Chan, and K. W. operating frequency of 100 MHz and for an imput ramp rate Terrill, “Hot-electron-induced degradation-Model, monitor, and im- of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are provement,” IEEE Trans. Electron Devices, vol. ED-23, p. 375, 1985. 120 and 300, respectively, and the NMOSFET and PMOSFET [6] E. Takeda, Y. Ohji, and H. Hume, “High field effects in MOSFET’s, in IEDM Tech. Dig., 1985, p. 60. speed degradation factors with respect to saturation drain [7] P. Heremans, R. Bellens, G. Groeseneken, and H. Maes, “Consis- current change are 1/4 and 1/2, respectively. If 10% AId/Id tent model for the hot-carrier degradation in n-channel and p-channel of an NMOSFET is reached in 0.1 year under worst-case dc MOSFETs,” IEEE Trans. Electron Devices, vol. 35, p. 2194, 1988. [8] J. Choi, P. K. KO, C. Hu, and W. Scott, “Hot-carrier-induced degrada- stress condition, it will take 12 years to produce 10% A &/Id tion of metal-oxide-semiconductor field-effect transistor: Oxide charge under ac operation at 100 MHz. versus interface traps,” J. Appl. Phys., vol. 65, p. 354, 1989. QUADER et al.: HOT-CARRIER-RELIABILITY DESIGN GUIDELINES 26 1

K. Mistry and B. Doyle, “A model for ac hot-carrier degradation in Khandker N. Quader (M’87-S’90) was born in n-channel MOSFET’s,” IEEE Electron Device Lett., vol. 12, p. 492, Dhaka, Bangladesh. He received the B.S. degree 1991. in electrical engineering and the B.S. degree in M. Brox and W. Weber, “Dynamic degradation in MOSFET’s-Part I: physics from the Massachusetts Institute of Tech- The physical effects,” IEEE Trans. Electron Devices, vol. 38, p. 1852, nology, Cambridge, MA, in 1982, and the M.S. 1991. degree in electrical engineering from the Georgia W. Weber, M. Brox, T. Kunemund, H. Muhlhoff, and D. S. Landsiedel, Institute of Technology, Atlanta, in 1984. He is “Dynamic degradation in MOSFET’s-Part 11: Application in the circuit currently working towards the Ph.D. degree in elec- environment,” IEEE Trans. Electron Devices, vol. 38, p. 1859, 1991. trical engineering at the University of California, K. R. Mistry, T. F. Fox, R. P. Preston, N. D. Arora, B. S. Doyle, and D. Berkeley. E. Nelson, “Circuit design guidelines for n-channel MOSFET hot-carrier From 1984 to 1989 he was a Senior Circuit robustness,” IEEE Trans. Electron Devices, vol. 40, p. 1284, 1993. Design Engineer in the Memory Components Division of Intel Corporation, E. S. Snyder, D. V. Campbell, S. E. Swanson, and D. G. Pierce, “Novel where he worked on high speed SRAM’s, EPROM’s, and application- self-stressing test structures for realistic high-frequency reliability char- specific and differentiated memory products on advanced CMOS technologies. acterization,” in Proc. IEEE IRPS, 1992, p. 57. HIS current research interests are deep submicron device and circuit level K. N. Quader, P. K. KO, and C. Hu, “A new insight into correlation hot-carrier effects in bulk and SO1 MOSFET’s, device physicdmodeling, between DC and AC hot-carrier degradation behavior of MOS devices,” computer-aided reliability prediction, technology integration, and high speed in Proc. IEEE VLSI Technol. Symp., 1993, p. 13. memory devices. E. Takeda, R. Izawa, K. Umeda. and R. Nagai, “AC hot-carrier effects in scaled MOS devices,” in Proc. IRPS, 1991, p. 118. R. Tu et al., “BERT-Berkeley reliability tools,” UCB Memo. UCB/ERLM91/107, Dec. 1991. R. Tu, E. Rosenbaum, W. Chan, C. Li, E. Minami, K. Quader, P. KO, and C. Hu, “Berkeley reliability tools-BERT,” IEEE Trans. Comput.-Aided Design, Oct. 1993. Eric R. Minami was born in Fukuoka, Japan, in T.-C. Ong. K. Seki, P. K. KO, and C. Hu, “P-MOSFET gate current and 1964. He received the B.S. degree in electrical device degradation,” in Proc. IEEE Rel. Phys. Symp., Mar. 1989, p. 178. engineering and the B.S. degree in materials science P. Lee, T. Garfinkel. P. K. KO, and C. Hu, “Simulation of P- and N- from the Massachusetts Institute of Technology in MOSFET hot-carrier degradation in CMOS circuits,’’ in Proc. Int. Symp. 1986 and the M.S. degree in electrical engineering VLSI Tech., Syst., Appl., 1991, p. 191. from the University of California, Berkeley, in 1988. M. M. Kuo, K. P. M. Lee, J. Y. Choi, P. K. KO, and C. Hu, Seki, He is currently working towards the Ph.D. degree “Simulation of MOSFET lifetime and ac hot-electron stress,” IEEE in electrical engineering at the University of Cah- Trans. Electron Devices, vol. 35, p. 1004, 1988. fornia. K. Mistry and B. Doyle, “AC versus DC hot-carrier degradation in From 1989 to 1991 he was with Sony in Tokyo, n-channel MOSFET’s, IEEE Trans. Electron Devices, p. 96, 1993. Japan His current research interests are modeling P. Heremens, R. Bellens, G. Groeseneken, H. E. Maes. B. S. Doyle, and simulation of VLSI reliability effects. K. R. Mistry, M. Bourcerie, C. Bergonzoni, R. Benecchi, A. Bravis, and A. Boudou, “Comments on ‘The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot-carrier stressing of n-MOS transistors.’ with reply,” IEEE Trans. Electron Devices, vol. 39, p. 458, 1992. P. M. Lee, P. K. KO, and C. Hu, “Relating CMOS inverter lifetime to DC hot-carrier lifetime of NMOSFET’s,” IEEE Electron Device Lett., vol. 11, p. 39, Jan. 1990. Y. Leblebici, W. Sun, and S. M. Kang, “Parametric macro-modeling of hot-carrier-induced dynamic degradation in MOS VLSI circuits,” IEEE Trans. Electron Devices, vol. 40, p. 673, 1993. B. S. Doyle and K. R. Mistry, “Hot-carrier stress damage in the gate off state in n-channel transistors,” IEEE Trans. Electron Devices, vol. 39, p. 1772, 1992. 1992 EECSERL Res. Summary, Univ. California, Berkeley, pp. 17%180. T. Tsuchiya, Y. Okazaki, M. Miyake, and T. Kobayashi, “New hot- carrier degradation mode and lifetime prediction method for quarter- micrometer PMOSFET,” IEEE Trans. Electron Devices, vol. 39, p. 404, 1992. Q. Wang, M. Brox, W. H. Krautschneider, and W. Weber, “Explanation and model for logarithmic time dependence of p-MOSFET degradation,” IEEE Electron Device Lett., vol. 12, p. 218, 1991. C. C. Li, K. N. Quader, E. R. Minami, P. K. KO, and C. Hu, “A new bi-directional PMOSFET hot-carrier degradation model for circuit Ping K. KO (S’78-M’81) received the B.S. degree reliability simulation,” in IEDM Tech. Dig., 1992, p. 547. in physics with special honors from Hong Kong C. Chu and M. Horowitz, “Charge-sharing models for switch-level University in 1974, and the M.S. and Ph.D. degrees simulation,” IEEE Trans. Comput.-Aided Design, p. 202, 1983. in electrical engineering from the University of E. Minami, K. N. Quader, P. K. KO, and C. Hu, “Prediction of hot- California, Berkeley, In 1978 and 1982. respec- carrier degradation in digital CMOS VLSI by timing simulation,” in tively. IEDM Tech. Dig., 1992, p. 531. In 1982 and 1983 he was a Member of the K. Nogami, K. Sawada, M. Kinugawa, and T. Sakurai, “VLSI circuit Technical Staff at Bell Laboratories, Holmdel, NJ, reliability under AC hot-carrier stress,” in Proc. Symp. VLSI Circuits, where he was responsible for developing high-speed 1987, p. 13. MOS technologies for communication circuits. He K. Mistry and B. Doyle, “Hot-carrier degradation in n-MOSFET’s used joined the Berkeley faculty in 1984. where he is now as pass transistor,” IEEE Trans. Electron Devices, vol. 37, p. 2415, Professor in the Department of Electncal Engineering and Computer Sciences. 1990. He was Faculty Director of the Berkeley Microfabncation Laboratory from K. N. Quader, C. Li, R. Tu, E. Rosenbaum, P. K. KO,and C. Hu, “A new 1984 to 1993. He is now on sabbatical leave at the Hong Kong University approach for simulating circuit degradation due to hot-carrier effects in of Science and Technology. His present research interests include high-speed NMOSFETs,” in IEDM Tech. Dig., 1991, p. 337. VLSI technologies and devices, device modeling for circuit simulation, and N. H. E. Weste and K. Eshraghain, Principles of CMOS VLSI Design. CAD tools for IC. He has authored or coauthored one book and over 150 Reading, MA: Addison-Wesley, 1985, p. 314. research papers. 262 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.29, NO. 3, MARCH 1994

Chenming Hu (S’7 I-M’76-SM’83-F90) received the B.S. degree from the National Taiwan University and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1970 and 1973, respectively. From 1973 to 1976 he was an Assistant Profes- sor at the Massachusetts Institute of Technology. In 1976 he joined the University of Califomia, Berkeley, as Professor of Electrical Engineering and Computer Sciences. He is also the Director of the Industrial Liaison Program. While on industrial leave from the university in 1980-1981, he was Manager of Nonvolatile Memory Development at National Semiconductor. Since 1973, he has served as a consultant to the electronics industry. He has also been an advisor to many government and educational institutions. His present research areas inlude VLSI devices, silicon-on-insulator devices, hot electron effects, electromigration, circuit reliability simulation, and nonvolatile semiconductor memories. He has also conducted research on electrooptics, solar cells, and power electronics. He has several patents on semiconductor devices and technology. He has authored or coauthored three books and over 350 research papers. He has delivered more than a score of keynote addresses and invited papers at scientific conferences, and received a number of Best Paper Awards. He is an Honorary Professor of Beijing University and Tsinghua University. Dr. Hu was a Guest Editor of the PROCEEDINGSOF THE IEEE and the IEEE TRANSACTIONSON ELECTRON DEVICES.He serves on an editorial board of Semiconductor Science and Technology, Institute of Physics, England. He was an Associate Editor of the IEEE TRANSA~IONSON ELECTRON DEVICES from 1986 to 1988, and was Vice Chairman of the IEEE Electron Devices Society, Santa Clara Valley Chapter, in 198G1982. He was the first National Science Council Invited Chair Lecturer, Republic of China, in 1987. He received the 1991 Design News Excellence Award and 1991 Semiconductor Research Corporation Technical Excellence Award for leading the development of the IC reliability simulator, BERT.