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Hot-Carrier-Reliability Design Guidelines for CMOS Logic Circuits

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Hot-Carrier-Reliability Design Guidelines for CMOS Logic Circuits ~ IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 3, MARCH 1994 253 Hot-Carrier-Reliability Design Guidelines for CMOS Logic Circuits Khandker N. Quader, Student Member, IEEE, Eric R. Minami, Wei-Jen Huang, Ping K. KO, Member, IEEE, and Chenming Hu, Fellow, IEEE Abstract- Long-term ring-oscillator hot-carrier degradation term ring oscillator degradation results and BERT simulation. data and simulation results are compared to demonstrate that This will be followed by derivations of hot-carrier-reliability a circuit reliability simulator BERT can predict CMOS digital design rules for digital applications and comparisons of circuit circuit speed degradation from transistor dc stress data. We present generalized hot-carrier-reliabilitydesign rules that trans- degradation calculated using the design rules presented here late device-level degradation rate to CMOS circuit lifetime. The with BERT simulations and experimental data. Finally, we design rules, which consist of lifetime and speed degradation will present techniques for using the design rules for quick factors, can roughly predict CMOS circuit degradation during estimates of circuit lifetime. the initial design, and can help reliability engineers to quickly es- timate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ f trise and 11. HOT-CARRIERFUNDAMENTALS lo/ f t~lrespectively. Typically, the NMOSFET and PMOSFET Static (dc) hot-carrier degradation has been extensively speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 studied [5]-[SI; lingering controversy regarding dynamic (ac) MHz operating frequency and for an input rise time of 0.35 ns, degradation is also rapidly dissipating. Although different the NMOSFET and PMOSFET time factors are 120 and 300, mechanisms for enhanced dynamic degradation have been respectively. noted in the past [9], [lo], recent studies on the dynamic degradation of MOSFET’s in an actual circuit environment I. INTRODUCTION [ 1 11-[ 141 have concluded that the quasi-static model, which considers ac stress merely as a series of short dc stresses strung HE understanding of the relationship between circuit life- together, is still valid for real circuits. Inductive noise [15] time to device dc stress lifetime is becoming increasingly T and error in substrate and gate current models can contribute important for deep submicron technologies since criteria such more variation to the degradation than remaining enhanced as a lo\% drain current change in ten years are no longer ac degradation in actual circuits. BERT is a reliability sim- viable. Hot-carrier-reliability simulators, such as the substrate ulator for hot-carrier as well as oxide and electromigration current simulator [l], BERT [2], HOTRON [3], and RELY reliability simulation [16], [ 171. It uses a quasi-static approach [4], have been developed to predict CMOS circuit reliability; however, the simulation process is time consuming and is best to predict hot-carrier-induced CMOS circuit degradation, and suited for overall product reliability simulation towards the includes both NMOSFET and PMOSFET hot-carrier models. end of the design phase. A simple guideline for estimating hot- The amount of degradation, AD, such as the change in drain carrier reliability is still desirable. Although a circuit designer current (AId/Id), suffered by an MOS device due to hot- can do first-order estimates of speed, power consumption, and carrier stressing is given by [5] circuit area, no analytical tool is available yet during the design AD = F (Age) (1) phase to quickly evaluate and optimize circuits for hot-carrier sensitivity. In this paper, we present a generalized set of design where the function F can be experimentally determined and rules that can help the circuit designer to incorporate the effects the parameter “Age” (amount of stress experienced by each of hot-carrier degradation during the initial design phase and device) is used to quantify device degradation during cir- can help device reliability engineers to quickly estimate overall cuit operation. The NMOSFET and PMOSFET Ages can be product reliability from simple dc stress experiments. expressed as [2], [18], [19] We will first give a brief overview of hot-carrier effects and the circuit reliability simulator, BERT(BErke1ey Reliability Tools), followed by the correlation between experimental long- (3) Manuscript received July 26, 1993; revised October 27, 1993. This work was supported by SRC under Contract 92-MJ-148 and ISTO/SDIO through ONR under Contract N00014-92-J-1757, MICRO, AMD, Philips, Rockwell, where W is the device width, H and m are the gate-bias and HP. This paper is an expanded version of a paper presented at the 1993 dependent degradation parameters, Isub3Ig, and Ids are the IEEE Custom Integrated Circuits Conference. substrate, gate, and drain currents, respectively, and T is The authors are with the Department of Electrical Engineering and Com- puter Science, University of Califomia, Berkeley, CA 94720. the duration of the stress. The subscripts s and g in m IEEE Log Number 9214793. and H denote substrate and gate current, respectively, and 0018-9200/94$04.00 0 1994 IEEE 254 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.29, NO. 3, MARCH 1994 the subscripts n and p refer to NMOSFET and PMOSFET, respectively. Equation (1) can be expressed as Age = F-'(AD). (4) Substituting this in (2) and (3), we can write the NMOSFET and PMOSFET dc device lifetime r, and rp by the following expressions: gJlo-' (BERTSimulation) 1" loo IO' lo2 lo3 io4 io5 Time (min) rp = H,,F-'(AD) - (6) -mgp [;I [;I Fig. 1. Experimental and BERT-simulated frequency degradation versus The slope and intercept of the 7,1ds/W versus Isub/Ids plot stressing time for a 91-stage ring oscillator. Correlation with dc stress data for NMOSFET and the slope and intercept of the rp versus is also shown. Ig/W plot for PMOSFET give the m and H degradation parameters. In [20], it has been shown that H and m are, simulation and experimental results that suggests that circuit in general, gate-bias ( Vgd) dependent. Thus, by including degradation can be predicted using the quasi-static method. the bias dependence of H and m, BERT can accommodate All SPICE circuit simulations were performed using BSIM2 all known quasi-static models such as recently proposed low model parameters. and high gate voltage hot-carrier models [21]. Mistry et al. IV. HOT-CARRIER-RELIABILITY [21] assign physical mechanisms to the low V,, medium DESIGNRULES FOR CMOS CIRCUITS V,, and high V, regions. There are still disagreements on these assignments [22]. BERT does not assume any physical In this section, we show how circuit lifetime is related to degradation mechanism, and is capable of representing several device dc stress lifetime commonly monitored in IC industries different mechanisms. It is our experience, however, that today. Lee et al. [23] first introduced simple rules of thumb constant H and m at peak Isub condition are usually adequate. to translate discrete device degradation to actual circuit per- This is supported by experimental verification of a wide class formance degradation of inverter-based CMOS VLSI circuits. of digital circuits. During BERT simulation, Ids and Is& or I, Leblebici et al. [24] have also developed macromodels for are calculated for each device and at each time step, and then NMOSFET that relate circuit parameters such as input rise integrated to obtain the total Age of each device. Separately, time, capacitance, and device width to Age, the severity of the user provides measured transistor SPICE model parameters hot carrier damage. In this paper, we present a generalized at several different dc Ages as input to BERT. After the Age set of hot-carrier-reliability design rules that can aid circuit of each transistor in the circuit is calculated, the aged process designers as well as device and reliability engineers, and we files correspondingto the individual transistors are then used to also include the effects of PMOSFET drain current increase simulate the actual circuit degradation for a specified period on the overall performance of VLSI circuits. For simplicity, of time. we ignore the effects of "off-state'' damage [25] in this study. The design rules presented here: 1) translate device-level 111. EXPERIMENTALAND SIMULATION RESULTS linear or saturation drain current change to circuit speed change, and 2) translate dc lifetime to ac lifetime. Fig. 2 A 0.7pm, 17.5 nm oxide, LDD CMOS technology (tech- shows the simulation results of linear A Id/Id of a dc stressed nology A) and a 1.2pm, 21 nm oxide LDD CMOS technology NMOSFET device, linear A Id/Id of an NMOSFET device (technology B) were used to fabricate the ring ocsillators, internal to the ring oscillator and subjected to the ring oscillator digital circuits, and the discrete devices. Devices with L,R = stress, and Af/f of the ring oscillator with PMOSFET degra- 0.5-0.95 pm have been used in this study. The most important dation turned off. The two rules of thumb can be understood dc stresses were those done under peak substrate current from Fig. 2. The horizontal shift, called NMOSFET lifetime condition for NMOSFET and peak gate current condition for factor (NTF), represents the time required for the internal PMOSFET. Vds = 8 V was used for all stresses and Vds = 5 ring oscillator NMOSFET device to reach an equivalent dc V was used for all measurements. A Id/Id (linear or saturation), and the vertical shift, called SPICE model parameters for substrate and gate currents the NMOSFET speed degradation factor (NSF), represents the were first extracted for N- and PMOSFET's. Then, degradation factor required to translate a given A Id/Id to circuit speed parameters H and m were determined using the method degradation.
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